Pulse width modulation circuit capable of linearly adjusting duty cycle with voltage and related method

1. Field of the Invention

The present invention relates to a pulse width modulation circuit and related method, and more particularly, to a pulse width modulation circuit capable of linearly adjusting duty cycle with voltage and related method.

2. Description of the Prior Art

Pulse width modulation (PWM) technique is widely used for output power control, such as power management, motor control, audio amplifiers, etc. Please refer to FIG. 1 , which illustrates a schematic diagram of a PWM circuit 10 in the prior art. The PWM circuit 10 includes a reference voltage generator 102 , a triangular wave oscillator 104 , and a comparator 106 . The PWM circuit 10 is utilized for outputting a PWM signal S PWM with periodic variation of pulse width according to a result of comparing a reference voltage V R with a periodic triangular wave (or a sawtooth wave) signal V T . The prior art can control the output power by changing duty cycle of the PWM signal S PWM . Taking the U.S. patent publication document (patent publication NO. 2005/0269985) as an example, the PWM circuit 10 has a periodic triangular wave (or sawtooth wave) signal V T with fixed high and low voltage levels. As the reference voltage V R generated by the reference voltage generator 102 is linearly proportional to the input DC voltage V in , the duty cycle of the PWM signal S PWM is linearly varied with the input DC voltage V in . To make short of the matter, the duty cycle of the PWM signal S PWM can be linearly tunable by voltage levels of the input DC voltage V in .

This method has some limitations and can't meet some application requirements, especially for the cases of tuning wider range of duty cycle. Modifying the design of the reference voltage generator 102 should be a solution, but it takes much more components. Another approach is to control the high and low voltage levels of the triangular wave signal V T via the input DC voltage V in . It should be noted that the reference voltage V R is fixed for this case. In this way, the input DC voltage V in can adjust duty cycle of the PWM signal S PWM across a wider range. However, the relation between the duty cycle of the pulse width modulation signal S PWM and the input DC voltage V in , as shown in FIG. 2 , can not achieve absolutely linearity. This nonlinear relationship should contribute some unwanted influences. For example, when a PWM signal S PWM is utilized for speed control of a fan motor, it may result in a non-linear relation between the input DC voltage V in and the speed.

The primary objective of the present invention is to provide a pulse width modulation circuit capable of linearly adjusting duty cycle with voltage and related method.

The present invention discloses a pulse width modulation circuit capable of linearly adjusting duty cycle with voltage, which comprises an input voltage source for generating an input voltage, a regulator coupled to the input voltage source for generating a regulated voltage, a first voltage-dividing unit coupled to the regulator and a ground terminal for providing a first divided voltage, a second voltage-dividing unit coupled to the regulator and the ground terminal for providing a second divided voltage, a third voltage-dividing unit coupled to the input voltage source and the ground terminal for providing a third divided voltage, a voltage adder coupled to the a first voltage-dividing unit and the third voltage-dividing unit for adding the first divided voltage and the third divided voltage for generating a high level voltage, a waveform generator coupled to the voltage adder and the third voltage-dividing unit for generating an oscillating signal according to the high level voltage and the third divided voltage, and a comparator having a first input terminal coupled to the second voltage-dividing unit, a second terminal coupled to the waveform generator, and an output terminal for comparing the second divided voltage with the oscillating signal to output a pulse width modulation signal through the output terminal.

The present invention further discloses a method capable of linearly adjusting duty cycle with voltage for a pulse width modulation circuit, which the method comprises generating a regulated voltage according to an input voltage; transforming the regulated voltage into a first divided voltage and a second divided voltage, and transforming the input voltage into a third divided voltage; adding the first divided voltage and the third divided voltage for generating a high level voltage; generating an oscillating signal according to the high level voltage and the third divided voltage; and comparing the second divided voltage with the oscillating signal to output a pulse width modulation signal.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 is a schematic diagram of a PWM circuit in the prior art.

FIG. 2 is a schematic diagram showing the relationship between duty cycle of the PWM signal and input DC voltage in the modified prior art for wider tuning range of duty cycle.

FIG. 3 is a schematic diagram of a pulse width modulation circuit according to an embodiment of the invention.

FIG. 4 is a schematic diagram of waveforms showing generation of a pulse width modulation signal according to an embodiment of the invention.

FIG. 5 is a schematic diagram showing waveforms of the pulse width modulation signal under various input voltage values according to an embodiment of the invention.

FIG. 6 is a schematic diagram showing the relationship between the duty cycle of the pulse width modulation signal and the input voltage according to an embodiment of the invention.

FIG. 7 is a schematic diagram of a procedure according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a pulse width modulation circuit 30 according to an embodiment of the invention. The pulse width modulation circuit 30 utilized for adjusting duty cycle according an input voltage includes an input voltage source P, a regulator 302 , a first voltage-dividing unit 304 , a second voltage-dividing unit 306 , a third voltage-dividing unit 308 , a voltage adder 310 , a waveform generator 312 , and a comparator 314 . The input voltage source P is utilized for generating an input voltage V CC . The regulator 302 is coupled to input voltage source P for generating a regulated voltage V REG . The first voltage-dividing unit 304 is coupled to regulator 302 and a ground terminal for providing a first divided voltage V 1 . The second voltage-dividing unit 306 is coupled to regulator 302 and the ground terminal for providing a second divided voltage V 2 . The third voltage-dividing unit 308 is coupled to input voltage source P and the ground terminal for providing a third divided voltage V 3 . The voltage adder 310 is coupled to first voltage-dividing unit 304 and third voltage-dividing unit 308 for adding the first divided voltage V 1 and the third divided voltage V 3 to generate a high level voltage V H . The waveform generator 312 is coupled to voltage adder 310 and third voltage-dividing unit 308 for generating an oscillating signal OSC with high and low voltage levels are V H and V 3 , respectively. The comparator 314 is coupled to second voltage-dividing unit 306 and waveform generator 312 for comparing the second divided voltage V 2 with the oscillating signal OSC to output a pulse width modulation signal S PWM , so as to control driving component directly.

As illustrated in FIG. 3 , the first voltage-dividing unit 304 includes a first voltage-dividing output terminal O 1 , a first voltage-dividing resistor R 1 , and a second voltage dividing resistor R 2 . The first voltage-dividing output terminal O 1 is coupled to the voltage adder 310 and V 1 is the divided output voltage. The first voltage dividing resistor R 1 is coupled between the regulator 302 and the first voltage-dividing output terminal O 1 . The second voltage dividing resistor R 2 is coupled between the first voltage-dividing output terminal O 1 and the ground terminal. The second voltage-dividing unit 306 includes a second voltage-dividing output terminal O 2 , a third voltage dividing resistor R 3 , and a fourth voltage dividing resistor R 4 . The second voltage-dividing output terminal O 2 is coupled to a first input terminal of comparator 314 and V 2 is the divided output voltage. The third voltage-dividing resistor R 3 is coupled between the regulator 302 and the second voltage-dividing output terminal O 2 . The fourth voltage-dividing resistor R 4 is coupled between the second voltage-dividing output terminal O 2 and the ground terminal. The third voltage-dividing unit 308 includes a third voltage-dividing output terminal O 3 , a fifth voltage dividing resistor R 5 , and a sixth voltage dividing resistor R 6 . The third voltage-dividing output terminal O 3 is coupled to voltage adder 310 and waveform generator 312 and V 3 is the divided output voltage. The fifth voltage-dividing resistor R 5 is coupled between the input voltage source P and the third voltage-dividing output terminal O 3 . The sixth voltage-dividing resistor R 6 is coupled between the third voltage-dividing output terminal O 3 and the ground terminal.

FIG. 4 is a schematic diagram of waveforms showing generation of a pulse width modulation signal S PWM according to an embodiment of the invention. In the pulse width modulation circuit 30 , the input voltage V CC generated by the input voltage source P can be considered as an external control voltage source. In addition, the regulator 302 can provide and maintain a stable DC voltage level, V REG , which should not change with variation of load current and input voltage. Note the specification for output value of a regulator should be set within a default value. The voltage adder 310 adds the first divided voltage V 1 and the third divided voltage V 3 to generate a high level voltage V H (i.e. V H =V 1 +V 3 ). The waveform generator 312 generates an oscillating signal OSC according to high level voltage V H and the third divided voltage V 3 . The signal OSC could be a triangular or sawtooth waveform and it's high and low voltage levels would be V H and V 3 , respectively. The amplitude of the oscillating signal OSC is equal to the first divided voltage V 1 . The comparator 314 compares the second divided voltage V 2 with the oscillating signal OSC to generate a pulse width modulation signal S PWM . The duty cycle of the pulse width modulation signal S PWM can be determined as follows:

The high and low levels' relationship of the oscillating signal OSC generated by the waveform generator 312 can be expressed as follows:

V H =V 1 +V 3   (2)

By substituting the equation (2) into the equation (1), the following equation is obtained:

Duty ⁢ ⁢ Cycle = ( 1 - V 2 V 1 ) + ( K a V 1 ) · V CC ( 3 )

where V CC is the input voltage, and the K a is the ratio of voltage dividing resistors for V 3

The first divided voltage V 1 and the second divided voltage V 2 are derived from the regulated voltage V REG . The ratio of voltage-dividing resistors for V 3 is K a . One can get that V 1 , V 2 , and K a are independent to the input voltage V CC . From the equation (3), it can be appreciated that the duty cycle is linearly proportional to the input voltage V CC . The slope of equation (3) is determined by the first divided voltage V 1 and K a , the ratio of voltage dividing resistors. The values of this slope can be adjusted flexibly by setting the first divided voltage V 1 and the ratio of voltage dividing resistors Ka to meet various requirements of duty cycle control. Similarly, the desired duty cycle of the pulse width modulation signal S PWM can also be linear adjusted by setting the second divided voltage V 2 .

FIG. 5 illustrates the waveforms of the pulse width modulation signal under various input voltage values according to an embodiment of the invention. Suppose that two input voltage levels V CC1 and V CC2 are applied in the pulse width modulation circuit 30 respectively. And the voltage level of V CC1 is higher than that of V CC2 . When the input voltage level V CC1 is applied as the input voltage, OSC 1 indicates the oscillating signal, V H1 indicates the high level of the oscillating signal OSC 1 , and V 31 indicates the low level of the oscillating signal OSC 1 . Similarly, when the other input voltage level V CC2 is applied as the input voltage, OSC 2 indicates the oscillating signal, V H2 indicates the high level of the oscillating signal OSC 2 , and V 32 indicates the low level of the oscillating signal OSC 2 . The pulse width modulation signals S PWM1 and S PWM2 corresponding to the V CC1 and V CC2 are outputted from the comparator 314 respectively. Please note that both conditions have the same amplitude V 1 for the oscillating signal and the same reference voltage V 2 . It can be seen that the higher the input voltage level V CC is, the larger the duty cycle is.

FIG. 6 shows the relationship between the duty cycle of the pulse width modulation signal S PWM and the input voltage V CC according to an embodiment of the invention. Under various settings of first divided voltage V 1 (i.e. various amplitudes), the input voltage is linearly proportional to the duty cycle. As a result, the pulse width modulation circuit 30 of the present invention is capable of improving the applications of pulse width modulation effectively. For the example of utilizing the pulse width modulation circuit 30 in speed control of a fan motor, one can linearly adjust the speed of the fan motor because of the duty cycle of the pulse width modulation signal S PWM linearly changed by the input voltage V CC .

Therefore, through the pulse width modulation circuit 30 of the present invention, the duty cycle of the pulse width modulation signal S PWM has linear relation with the input voltage V CC , and the voltage levels of the oscillating signal OSC can be controlled via external input voltage, so as to linearly control the duty cycle of the pulse width modulation signal S PWM . The desired linear slope values can also be adjusted flexibly for conforming to various application requirements of the duty cycle control without additional complicated components. In other words, the present invention is capable of linearly adjusting the duty cycle of the pulse width modulation signal with input voltage and flexibility providing variations for various duty cycles.

Please note that the pulse width modulation circuit 30 , shown in FIG. 3 , is a schematic diagram according to an exemplary embodiment of the present invention. Those skilled in the art can make alternations and modifications accordingly. For example, first voltage-dividing unit 304 , second voltage-dividing unit 306 , and third voltage-dividing unit 308 can provide any desired divided voltage value by dividing the regulated voltage or input voltage with resistors or other devices. These should not be a limitation of the present invention. The waveform generator 312 can be utilized for generating all kinds of oscillating signals, such as triangular wave signals, saw tooth wave signals, ramp signals, etc. In addition, the duty cycle of the pulse width modulation signal cannot only be adjusted by setting the input voltage V CC , but also by setting the first divided voltage V 1 or the second divided voltage V 2 .

As to the operation of the pulse width modulation circuit 30 , please refer to FIG. 7 . FIG. 7 is a schematic diagram of a procedure 70 according to an embodiment of the present invention. The procedure 70 is capable of being the operating procedure for the pulse width modulation circuit 30 . The procedure 70 comprises the following steps:

Step 702 : Generate a regulated voltage V REG according to an input voltage V CC .

Step 704 : Transform the regulated voltage V REG into a first divided voltage V 1 and a second divided voltage V 2 , and transform input voltage V CC into a third divided voltage V 3 .

Step 706 : Add the first divided voltage V 1 and the third divided voltage V 3 for generating a high level voltage V H .

Step 708 : Generate an oscillating signal OSC according to high level voltage V H and the third divided voltage V 3 .

Step 710 : Compare second divided voltage V 2 with oscillating signal OSC to output a pulse width modulation signal S PWM .

According to the procedure 70 , the present invention generates the regulated voltage V REG according to input voltage V CC . After that, the regulated voltage V REG can be transformed into a first divided voltage V 1 and a second divided voltage V 2 , and the input voltage V CC can be transformed into a third divided voltage V 3 . Furthermore, the voltage adder 310 adds first divided voltage V 1 and the third divided voltage V 3 to generate a high level voltage V H . The waveform generator 312 is capable of generating an oscillating signal OSC according to high level voltage V H and the third divided voltage V 3 . Finally, the comparator 314 compares second divided voltage V 2 with oscillating signal OSC so as to output a pulse width modulation signal S PWM . The procedure 70 is utilized for illustrating the operation method of the pulse width modulation circuit 30 . The related variations and the detailed description that referred to the foregoing illustration are omitted herein.

In summary, through the pulse width modulation circuit 30 of the present invention, the duty cycle of the pulse width modulation signal S PWM has linear relation with the input voltage V CC . The voltage levels of the oscillating signal OSC can be controlled via external input voltage, V CC , so as to linearly control the duty cycle of the pulse width modulation signal S PWM . Furthermore, the desired linear slope values can also be adjusted flexibly for conforming to various variations of the duty cycle control requirements without additional complicated components.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.