Computer system

This application claims the priority benefit of Taiwan application serial no. 98106462, filed Feb. 27, 2009. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

1. Field of the Invention

The present invention relates to a computer system, and more particularly, to a computer system having a power supply shared by a plurality of mainboards.

2. Description of Related Art

Nowadays, science and technology have been well developed, and are kept developing. Unavoidably, computer systems have become necessary information processing tools which are critical in human daily life. A current computer system may satisfy almost all requirements in working, travelling, and entertainment which are personally demanded by the user. For example, personal information such as personal financial data, banking accounts and passwords, confidential documents and photographs, private letters, and intellectual creations can be saved and managed in a hard drive of the computer system.

In many cases, when using a computer system, the user may temporarily leave the computer system, and therefore the power supply of the computer system will become less efficient. Accordingly, a computer system is often provided with a power supply management mechanism for adaptively turning off some specific electronic units in the computer system, thus lowering the power consumption. In accordance with a typical power supply management mechanism, the computer system usually includes a power supply which provides two kinds of powers, main power and standby power. The main power is provided to the mainboard only when the computer system is in a booting state, while the standby power is provided to the mainboard when the mainboard is electrically connected to the power supply.

Unfortunately, in many times, the mainboard demands more than the standby power which can be provided by the power supply, so that electronic units which are usually driven by the standby power may correspondingly fail to be normally operated. As such, the operation performance of the computer system is impaired. Even though a stronger power supply can be provided for substitution for enhancing the operation performance of the computer system, this inevitably increases the hardware cost and causes a lower resource utilization efficiency.

Accordingly, the present invention is directed to provide a computer system including a plurality of mainboards. The computer system is adapted for controlling some of the mainboards to convert a main power into a plurality of standby voltages when an amount of the mainboards is greater than a predetermined value.

The present invention provides a computer system. The computer system includes a power supply, a plurality of mainboards, and a power controller. Each of the mainboards corresponds to a standby voltage, respectively. The power supply is adapted for generating a standby power, and generating a main power according to a power enabling signal. The power controller is coupled between the power supply and the mainboards, for generating the power enabling signal and a control signal according to whether an amount of the mainboards is greater than a predetermined value, and selectively outputting the control signal to at least one of the mainboards. When the mainboards receive the control signal, regardless being in a booting state or a non-booting state, the mainboards receive the main power and converts the main power into a standby voltage corresponding thereto. When failing to receive the control signal, the mainboards convert the standby power into the standby voltage corresponding thereto.

According to an embodiment of the present invention, the power supply generates a power ready signal according to the power enabling signal. When receiving the power ready signal, the mainboards convert the main power into a standby voltage corresponding thereto. Further, the mainboards output a mainboard power starting signal and therefore. The power controller generates the power enabling signal according to the mainboard power starting signal. The power controller determines whether the mainboards are in the booting state according to the mainboard power starting signal generated by the mainboards, and when the mainboards is determined as in the booting state, the received power ready signal is transmitted to the mainboards.

According to an embodiment of the present invention, the mainboards outputs mainboard identification codes to the power controller, and the power controller counts the amount of the mainboards according to the mainboard identification codes.

According to an embodiment of the present invention, the mainboards each includes a voltage converter for converting the main power or the standby power corresponding thereto into a plurality of standby voltages.

According to an embodiment of the present invention, the predetermined value is determined according to a mainboard standby driving amount of the standby power.

According to an embodiment of the present invention, the power controller is a complex programmable logic device (CPLD) or a programmable interrupt controller (PIC).

Accordingly, in accordance with the computer system of the present invention, when the amount of mainboards is greater than the predetermined value, the power controller generates the power enabling signal and the control signal. When receiving the power enabling signal, the power supply generates the main power. When receiving the control signal, the mainboards convert the main power into a plurality of standby voltages. In such a way, some of the mainboards can be dynamically selected for converting the main power into a plurality of standby voltages, thus avoiding system operation failures due to that the standby power is incapable of driving all of the mainboards.

The accompanying drawing is included to provide a further understanding of the invention, and is incorporated in and constitutes a part of this specification. The drawing illustrates embodiments of the invention and, together with the description, serves to explain the principles of the invention.

FIG. 1 is a schematic diagram illustrating a computer system according to an embodiment of the present invention.

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawing. Wherever possible, the same reference numbers are used in the drawing and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram illustrating a computer system according to an embodiment of the present invention. Referring to FIG. 1 , a computer system 100 is shown. The computer system 100 includes a power supply 110 , a power controller 120 , and mainboards 130 _ 1 through 130 _n, where n is a positive integer and may be different in accordance with the practical design of the computer system and requirement of clients. The power supply 110 is coupled to the power controller 120 and the mainboards 130 _ 1 through 130 _n. When the mainboards 130 _ 1 through 130 _n are in a non-booting state, the power supply 110 generates a standby power STP, and the mainboards 130 _ 1 through 130 _n convert the standby power STP into a plurality of standby voltages corresponding to the mainboards 130 _ 1 through 130 _n, respectively. Preferably, the mainboards 130 _ 1 through 130 _n include voltage converters (not shown in the drawing) for converting the standby power STP into a plurality of standby voltages.

Generally, the power supply 110 can be coupled to a power back-plane (not shown in the drawing), through which powers (e.g., standby power STP or main power MP) generated by the power supply 110 can be provided to the mainboards 130 _ 1 through 130 _n, respectively. The power controller 120 can be disposed on the power back-plane. When the mainboards 130 _ 1 through 130 _n are sequentially connected to the power back-plane, the mainboards 130 _ 1 through 130 _n receive the standby power STP. Therefore, the mainboards 130 _ 1 through 130 _n respectively transmit corresponding mainboard identification codes ID_ 1 through ID_n to the power controller 120 . After receiving the mainboard identification codes ID_ 1 through ID_n, the power controller 120 can obtains the amount of the mainboards 130 _ 1 through 130 _n by counting the mainboard identification codes ID_ 1 through ID_n.

The standby power STP provided by the power supply 110 is usually a power with a low current. When the mainboards 130 _ 1 through 130 _n of the computer system are in a standby state or the non-booting state, the standby power STP can provide standby voltages required for driving electronic components of the mainboards 130 _ 1 through 130 _n. However, when the amount of the mainboards 130 _ 1 through 130 _n increases, a higher current is desired for the standby power. The amount of the mainboards 130 _ 1 through 130 _n may exceeds a specific amount of mainboards (mainboard standby driving amount hereinafter) which can be driven by the standby power STP when the mainboards 130 _ 1 through 130 _n are in the standby state or the non-booting state. In this case, the electronic components of some of the mainboards 130 _ 1 through 130 _n driven by the standby power STP may be caused of failures of normal operation, or even the mainboards 130 _ 1 through 130 _n may fail of booting.

As such, according to the present invention, when the power controller 120 obtains the amount of the mainboards 130 _ 1 through 130 _n, the amount will be compared with a predetermined value. The predetermined value can be equal to or smaller than the mainboard standby driving amount. When the amount is not greater than the predetermined value, that represents the standby power STP is capable of driving all of the mainboards 130 _ 1 through 130 _n, and therefore the power controller 120 takes no action in response. When the amount is greater than the predetermined value, that represents the standby power STP is incapable of driving all of the mainboards 130 _ 1 through 130 _n by itself. In this case, additional power must be provided by the power controller 120 for substituting the standby power STP for providing to some of the mainboards 130 _ 1 through 130 _n, thus allowing all of the mainboards 130 _ 1 through 130 _n to be driven as usual. In this case, the power controller 120 generates a power enabling signal PON and transmits the power enabling signal PON to the power supply 110 . After receiving the power enabling signal PON, the power supply 130 generates the main power MP, and when the main power is readily prepared, the power supply 130 generates a power ready signal PGD. When receiving the power ready signal PGD, the power controller 120 generates a control signal, e.g., CTL_ 1 , and transmits the control signal to at least one of the mainboard 130 _ 1 through 130 _n.

Then, the mainboard 130 _ 1 is taken as an example for illustrating the computer system of the present invention. When receiving the control signal CTL_ 1 generated by the power controller 120 , regardless the mainboard 130 _ 1 is in a booting state, the non-booting state, or the standby state, the mainboard 130 _ 1 receives the main power MP outputted from the power supply 110 , and converts the main power MP into a standby voltage. Facilitated with the standby voltage converted from the main power MP, those electronic components driven by the standby power STP can be normally operated. The standby power STP and the main power MP have a same voltage level, and therefore the mainboard 130 _ 1 can utilize the voltage converter (not shown in the drawing) to convert the main power into the standby voltages. Similarly, when receiving control signals, e.g., CTL_ 2 through CTL_n, the mainboards 130 _ 2 through 130 _n take similar actions, and are not to be iterated hereby.

Further, the quantity of the control signals transmitted to the mainboards 130 _ 1 through 130 _n is determined by a difference between the amount of the mainboards 130 _ 1 through 130 _n and the mainboard standby driving amount. For example, when the amount of the mainboards is 7, and the mainboard standby driving amount is 4, there are 3 mainboards receiving the control signals. These 3 mainboards convert the main power MP into standby voltages for allowing these 3 mainboards to be normally driven. Preferably, the mainboards to which the control signals are to be transmitted can be selected from mainboards which are more frequently booted. In such a way, driving failures caused by too many mainboards can be avoided. Further selecting to transmit the control signals to those frequently booted mainboards is helpful for reducing the switching frequency of the mainboards switching between converting the main power MP and converting the standby power STP into a plurality of standby voltages, thus extending the lifespan of the switch component.

Further, the power controller 120 is adapted for isolating respective signals of the mainboards 130 _ 1 through 130 _n. Here, the condition that the amount of the mainboards 130 _ 1 through 130 _n is not greater than the mainboard standby driving amount is taken as an example for illustration. According to this condition, the standby power STP is capable of driving all of the mainboards 130 _ 1 through 130 _n. Therefore, when all of the mainboards 130 _ 1 through 130 _n are in the non-booting state or the standby state, each of the mainboards 130 _ 1 through 130 _n receives the standby power STP and converts the received standby power STP into a standby voltage corresponding thereto. When the mainboard 130 _ 1 is in the booting state, the mainboard 130 _ 1 outputs a mainboard power starting signal MSP_ 1 . When the power controller 120 receives the mainboard power starting signal MSP_ 1 , the power controller 120 generates the power enabling signal PON. When the power supply 110 receives the power enabling signal PON, the power supply 110 generates the main power MP, and when the main power is readily prepared, the power supply 110 generates the power ready signal PGD. After receiving the power ready signal PGD, the power controller 120 transmits the power ready signal PGD, e.g., PDG_ 1 , to the mainboard 130 _ 1 . After receiving the power ready signal PGD_ 1 , the mainboard 130 _ 1 starts to execute a booting operation for operating the mainboard 130 _ 1 . In this case, the mainboard 130 _ 1 is in a booting state, in which the standby voltage of the mainboard 130 _ 1 is provided by the main power MP of the power supply 110 . As such, the mainboards 130 _ 2 through 130 _n are unaffected by the starting of the mainboard 130 _ 1 .

Then, when the mainboard 130 _ 2 is started to be in the booting state, the mainboard 130 _ 2 transmits a mainboard power starting signal MSP_ 2 to the power controller 120 . Meantime, since the main power MP of the power supply 110 and the power ready signal PGD have been already generated, the power controller 120 directly transmits the power ready signal PGD, e.g., PGD_ 2 to the mainboard 130 _ 2 . After receiving the power ready signal PGD_ 2 , the mainboard 130 _ 2 starts to execute a booting operation for operating the mainboard 130 _ 2 . In this case, the booting operation of the mainboard 130 _ 2 does not affect the rest mainboards 130 _ 1 , 130 _ 3 through 130 _n. Likewise, starting operations of other mainboards, e.g., 130 _n, can be analogically learnt by referring to the foregoing depiction, and are not to be iterated hereby. Further, it should be noted that the sequence of starting the mainboards as depicted above is exemplified for illustration only, and is not provided for restricting the scope of the present invention.

Further, when the amount of the mainboards 130 _ 1 through 130 _n is greater than the mainboard standby driving amount, the power controller 120 directly generates the power enabling signal PON to enable the power supply 110 to generates the main power MP and the power ready signal PGD. In this case, when the mainboard 130 _ 1 is started to be in the booting state, the mainboard 130 _ 1 transmits the mainboard power starting signal MSP_ 1 to the power controller 120 . The power controller 120 then transmits the power ready signal PGD_ 1 to the mainboard 130 _ 1 , so that the mainboard 130 _ 1 starts to execute a booting operation for operating the mainboard 130 _ 1 . As to the rest mainboards, e.g., mainboards 130 _ 2 through 130 _n, when they are started to be in the booting state, the operations thereof are similar to the mainboard 130 _ 1 as discussed above and can be learnt by referring to the depiction above, and are not to be iterated hereby. It should be noted that with respect to any of the mainboards 130 _ 1 through 130 _n, if it converts the standby power STP into the standby voltage when it is in the non-booting state or the standby state, then it converts the main power MP into the standby voltage when it is in the booting state. In such a way, the power controller is provided for preventing interference generated between different mainboards, thus avoiding misoperation of the mainboards.

Further, the power controller 120 for example can be a complex programmable logic device (CPLD) or a programmable interrupt controller (PIC). Therefore, a simplified circuit design can be achieved, and the cost for constructing the circuit can be saved.

Briefly, the present invention provides a computer system as illustrated in accordance with the embodiment. When the amount of the mainboards is greater than a predetermined value, a power enabling signal and a control signal are generated. When the power supply receives the power enabling signal, it generates the main power. When receiving the control signal, the mainboards convert the main power into standby voltages corresponding thereto. In such a way, the computer system of the present invention is adapted for dynamically selecting some of the mainboards for converting the main power into a plurality of standby voltages, thus avoiding system operation failures due to that the standby power is incapable of driving all of the mainboards. Further, the power controller can be a CPLD or a PIC so as to simplify the circuit design and save the cost of constructing the circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.