Low drop-out regulator providing constant current and maximum voltage limit

1. Filed of Invention

The present invention relates to a regulator, and more particularly, to a low drop-out regulator.

2. Description of Related Art

A constant current is required for charging a rechargeable battery. A low drop-out (LDO) regulator with a constant current and a maximum voltage limit is utilized to charge a rechargeable battery, it can be used to power portable electronic devices, such as laptop computers, mobile phones, digital cameras and MP3 players. The conventional low drop-out regulator is complex.

An object of the present invention is to provide a simple and low cost circuit for the low drop-out (LDO) regulator with a constant current and a maximum voltage limit.

A low drop-out regulator according to the present invention comprises an unregulated DC input terminal receiving an input voltage. A regulated DC output terminal outputs an output voltage. A pass circuit is coupled between the unregulated DC input terminal and the regulated DC output terminal for supplying a power to the regulated DC output terminal. An amplifying circuit controls the pass circuit for providing a constant voltage or/and a constant current in response to the output voltage or/and an output current.

The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

FIG. 1 shows the circuit schematic of a preferred embodiment of a low drop-out regulator according to the present invention; and

FIG. 2 shows the circuit schematic of another preferred embodiment of the low drop-out regulator according to the present invention.

FIG. 1 shows the circuit schematic illustrating one embodiment of a low drop-out regulator according to the present invention. The low drop-out regulator is also a low drop-out regulation circuit. It includes a pass circuit and an amplifying circuit. The pass circuit having an output pass element 10 and a mirror pass element 15 . The low drop-out regulator further includes an unregulated DC input terminal VIN and a regulated DC output terminal VO. The unregulated DC input terminal VIN, the regulated DC output terminal VO and the output pass element 10 are used for supplying a power to the regulated DC output terminal VO. The power is an output voltage V O . A source of the output pass element 10 is coupled to the unregulated DC input terminal VIN for receiving an input voltage V IN , and a drain of the output pass element 10 is connected to the regulated DC output terminal VO for supplying the power to the regulated DC output terminal VO. It means that the pass circuit can be used for supplying the power to the regulated DC output terminal VO. The regulated DC output terminal VO outputs the output voltage V O .

Referring to FIG. 1 , the low drop-out regulator of this embodiment further comprises a resistor 31 . The mirror pass element 15 generates a mirror signal V M at the resistor 31 in response to a mirror current I M correlated to an output current I O of the output pass element 10 . A source and a gate of the mirror pass element 15 are respectively coupled to the source and a gate of the output pass element 10 . A drain of the mirror pass element 15 is coupled to a first terminal of the resistor 31 . A second terminal of the resistor 31 is coupled to a ground. The drain of the mirror pass element 15 generates the mirror signal V M correlated to the output current I O of the output pass element 10 . The output pass element 10 and the mirror pass element 15 can be P-transistor or PMOSFET according to a preferred embodiment of the present invention.

The amplifying circuit is used to control the pass circuit for providing a constant voltage or/and a constant current. The amplifying circuit includes a first amplifier 20 and a second amplifier 30 . The low drop-out regulator of this embodiment further comprises a voltage divider formed by resistors 21 and 22 . The first amplifier 20 has an output terminal for controlling the gates of the mirror pass element 15 and the output pass element 10 . A first input terminal of the first amplifier 20 has a first reference signal V R1 . A second input terminal of the first amplifier 20 is coupled to the regulated DC output terminal VO to receive a feedback signal V FB through the voltage divider. The feedback signal V FB is correlated to the output voltage V O . The resistors 21 and 22 are connected in series and coupled between the regulated DC output terminal VO and the ground. The voltage divider is further coupled to the second input terminal of the first amplifier 20 . A power source of the first amplifier 20 is coupled to the unregulated DC input terminal VIN.

Referring to FIG. 1 , the low drop-out regulator of this embodiment further comprises a current source 25 , a resistor 26 , resistor 32 , a transistor 35 and a capacitor 39 . The current source 25 is coupled between the first input terminal of the first amplifier 20 and the unregulated DC input terminal VIN. A first terminal of the resistor 26 is coupled to the current source 25 and the first input terminal of the first amplifier 20 . A second terminal of the resistor 26 is coupled to the ground. The capacitor 39 is coupled between the first input terminal of the first amplifier 20 and the ground for the soft-start function. The capacitor 39 is charged by the current source 25 . The first reference signal V R1 is developed by the current source 25 and the resistor 26 . The output voltage V O can be expressed as,

V O ⁢ R 21 + R 22 R 22 × V R ⁢ ⁢ 1 ( 1 )

where R 21 and R 22 are the resistance of the resistors 21 and 22 ; V R1 is the amplitude of the first reference signal V R1 .

The output terminal of the first amplifier 20 modulates a gate voltage of the output pass element 10 in accordance with the first reference signal V R1 and the feedback signal V FB . The output voltage V O is modulated in response to the gate voltage of the output pass element 10 modulated by the first amplifier 20 .

The second amplifier 30 is used for programming the first reference signal V R1 . A first input terminal of the second amplifier 30 has a second reference signal V R2 . A second input terminal of the second amplifier 30 receives the mirror signal V M correlated to the output current I O through the resistor 31 and the mirror pass element 15 . An output terminal of the second amplifier 30 is coupled to a gate of the transistor 35 . A drain of the transistor 35 is coupled to the capacitor 39 , the current source 25 and the resistor 26 . The resistor 32 is coupled between a source of the transistor 35 and the ground. The transistor 35 can be N-transistor or NMOSFET according to a preferred embodiment of the present invention. When the mirror signal V M is lager than the second reference signal V R2 , the output terminal of the second amplifier 30 modulates a gate voltage of the transistor 35 and a programmable current I P1 coupled to the first reference signal V R1 and the current source 25 . The programmable current I P1 is used for programming the first reference signal V R1 . The programmable current I P1 flows through the transistor 35 . In other words, the output terminal of the second amplifier 30 is used to modulate the programmable current I P1 to program the first reference signal V R1 .

The output current I O can be expressed as,

l O = k × V R ⁢ ⁢ 2 R 31 ( 2 )

where R 31 is the resistance of the resistor 31 ; V R2 is the amplitude of the second reference signal V R2 ; k is the geometric ratio of the mirror pass element 15 and the output pass element 10 . Thus, when the resistance of the resistors 31 and the amplitude of the second reference signal V R2 are constant, the output current I O is a constant current which is limited by the second reference signal V R2 .

In the exemplary embodiment show in FIG. 1 , the operation of the low drop-out regulator of the present invention is as follows. When the output current I O increases in response to the increase of a load (not shown in FIG. 1 ) coupled to the regulated DC output terminal VO, the mirror signal V M will increase in response to the increase of the output current I O . When the mirror signal V M is lager than the second reference signal V R2 , an output voltage of the output terminal of the second amplifier 30 increases. The gate voltage of the transistor 35 will increase in response to the increase of the output voltage of the second amplifier 30 . In addition, it is well known in the art that the gate voltage of the transistor 35 increases and then a drain-source current of the transistor 35 increases. It means that the programmable current I P1 increases when the gate voltage of the transistor 35 increases. Thus, once the output voltage of the second amplifier 30 increases, the gate voltage of the transistor 35 and the programmable current I P1 both increase. Further, the first reference signal V R1 will decrease in accordance with the increase of the programmable current I P1 .

Besides, when the first reference signal V R1 is smaller than the feedback signal V FB in response to the decrease of the first reference signal V R1 , an output voltage of the output terminal of the first amplifier 20 increases. In addition, it is well known in the art that the gate voltage of the output pass element 10 increases and a source-drain voltage of the output pass element 10 increases in response to the increase of the output voltage of the output terminal of the first amplifier 20 . Therefore, when the output voltage of the first amplifier 20 increases, the gate voltage and the source-drain voltage of the output pass element 10 both increase. Further, the output voltage V O decreases in response to the increase of the source-drain voltage of the output pass element 10 . According to above, once the output current I O is high, the output current I O increases, that the mirror signal V M is lager than the second reference signal V R2 , the output voltage V O decreases for achieving constant current. Further, the first amplifier 20 controls the output pass element 10 to decrease the output voltage V O when the feedback signal V FB is high that the feedback signal V FB is higher than the first reference signal V R1 .

Moreover, operation conditions of the soft-start function of the present invention are as follows. When the unregulated DC input terminal VIN receives the input voltage V IN , the capacitor 39 is charged by the current source 25 for generating the first reference signal V R1 . The first reference signal V R1 increases gradually until reaching a maximum voltage limit. The maximum voltage limit is developed by the default setting of the amplitude of the current source 25 and the resistance of the resistor 26 .

Referring to the equation (1), when the resistance of the resistors 21 and 22 is constant, the output voltage V O is correlated to the first reference signal V R1 and is limited by the first reference signal V R1 . Therefore, the output voltage V O increases gradually in respond to the increase of the first reference signal V R1 for achieving the soft-start function.

Further, referring to the equation (2), the output current I O is a constant current and is limited by the second reference signal V R2 when the resistance of the resistor 31 is constant. In conclusion, this invention disclosures a low drop-out regulator providing the constant current according to the second reference signal V R2 , the maximum voltage limit according to default setting of the amplitude of the current source 25 and the resistance of the resistor 26 , and the soft-start function.

FIG. 2 shows the circuit schematic illustrating another preferred embodiment of the low drop-out regulator according to the present invention. As shown, the low drop-out regulator of this embodiment comprises a pass circuit and an amplifying circuit. The pass circuit includes an output pass element 60 and a mirror pass element 65 . The amplifying circuit includes a first amplifier 70 and a second amplifier 80 for controlling the pass circuit for providing the constant voltage or/and the constant current. The low drop-out regulator of this embodiment further comprises a voltage divider formed by the resistors 71 and 72 , a current source 75 , a resistor 76 , resistors 81 , 82 , a transistor 85 and a capacitor 89 . The operation characteristic of the output pass element 60 , the mirror pass element 65 , the current source 75 , the resistors 76 , 82 , the transistor 85 and the capacitor 89 of this embodiment are the same as the operation characteristic of the output pass element 10 , the mirror pass element 15 , the current source 25 , the resistors 26 , 32 , the transistor 35 and the capacitor 39 of the first embodiment.

A source of the output pass element 60 is coupled to the unregulated DC input terminal VIN for receiving the input voltage V IN , and a drain of the output pass element 60 is connected to the regulated DC output terminal VO for supplying the power to the regulated DC output terminal VO. It means that the pass circuit can be used for supplying the power to the regulated DC output terminal VO. The regulated DC output terminal VO outputs the output voltage V O . A drain of the mirror pass element 65 generates the mirror signal V M at the resistor 81 in response to the mirror current I M correlated to the output current I O of the output pass element 60 . A source and a gate of the mirror pass element 65 are respectively coupled to the source and a gate of the output pass element 60 . The output pass element 60 and the mirror pass element 65 can be P-transistor or PMOSFET according to this embodiment of the present invention.

The first amplifier 70 has an output terminal coupled to control the gates of the output pass element 60 and the mirror pass element 65 . A first input terminal of the first amplifier 70 has a fourth reference signal V R4 . A second input terminal of the first amplifier 70 is coupled to the resistor 81 to receive the mirror signal V M correlated to the output current I O . The resistor 81 is coupled between the drain of the mirror pass element 65 and the ground. The resistor 81 is further coupled to the second input terminal of the first amplifier 70 . A power source of the first amplifier 70 is coupled to the unregulated DC input terminal VIN. The current source 75 is coupled between the first input terminal of the first amplifier 70 and the unregulated DC input terminal VIN. A first terminal of the resistor 76 is coupled to the current source 75 and the first input terminal of the first amplifier 70 . A second terminal of the resistor 76 is coupled to the ground. The capacitor 89 is coupled between the first input terminal of the first amplifier 70 and the ground for the soft-start function. The capacitor 89 is further coupled to the current source 75 . The fourth reference signal V R4 is developed by the current source 75 and the resistor 76 .

The output current I O shown in FIG. 2 can be expressed as,

l O = k × V R ⁢ ⁢ 4 R 81 ( 3 )

Where R 81 is the resistance of the resistor 81 ; V R4 is the amplitude of the fourth reference signal V R4 ; k is the geometric ratio of the mirror pass element 65 and the output pass element 60 . Thus, the output current I O is constant current which is correlated to and limited by the fourth reference signal V R4 . Further, the output terminal of the first amplifier 70 modulates a gate voltage of the output pass element 60 in accordance with the fourth reference signal V R4 and the mirror signal V M . The output voltage V O is modulated in response to the gate voltage of the output pass element 60 modulated by the first amplifier 70 .

The second amplifier 80 is used for programming the fourth reference signal V R4 through the resistor 82 and the transistor 85 . An output terminal of the second amplifier 80 is coupled to a gate of the transistor 85 . A first input terminal of the second amplifier 80 has a third reference signal V R3 . A second input terminal of the second amplifier 80 is coupled to the regulated DC output terminal VO to receive the feedback signal V FB correlated to the output voltage V O through the voltage divider having the resistors 71 and 72 . The resistors 71 and 72 are connected in series and coupled between the regulated DC output terminal VO and the ground. The voltage divider is further coupled to the second input terminal of the second amplifier 80 . The transistor 85 can be N-transistor or NMOSFET according to this embodiment.

A drain of the transistor 85 is coupled to the capacitor 89 , the current source 75 and the resistor 76 . The resistor 82 is coupled between a source of the transistor 85 and the ground. When the feedback signal V FB is large than the third reference signal V R3 , the output terminal of the second amplifier 80 controls the gate of the transistor 85 and a programmable current I P4 coupled to the fourth reference signal V R4 and the current source 75 . The programmable current I P4 is used for programming the fourth reference signal V R4 . The programmable current I P4 flows through the transistor 85 . In other words, the output terminal of the second amplifier 80 is used to modulate the programmable current I P4 to program the fourth reference signal V R4 .

The output voltage V O shown in FIG. 2 can be expressed as,

V O = R 71 + R 72 R 72 × V R ⁢ ⁢ 3 ( 4 )

where R 71 and R 72 are resistance of the resistors 71 and 72 ; V R3 is amplitude of the third reference signal V R3 . Thus, when the resistance of the resistor 71 and 72 is constant, the output voltage V O is limited by the third reference signal V R3 . It means that the third reference signal V R3 is the maximum voltage limit.

Referring description of FIG. 1 , the skill in the art well known that the operation of the low drop-out regulator of the present invention show in FIG. 2 is as follows. When the output voltage V O increases in response to the decrease of a load (not shown in FIG. 2 ) coupled to the regulated DC output terminal VO, the feedback signal V FB will increase in response to the increase of the output voltage V O . When the feedback signal V FB is lager than the third reference signal V R3 , an output voltage of the output terminal of the second amplifier 80 increases. A gate voltage of the transistor 85 will increase in response to the increase of the output voltage of the second amplifier 80 . In addition, it is well known in the art that a drain-source current of the transistor 85 increases when the gate voltage of the transistor 85 increases. It means that the programmable current I P4 increases when the gate voltage of the transistor 85 increases. Thus, when the output voltage of the second amplifier 80 increases, the gate voltage of the transistor 85 and the programmable current I P4 both increase. Further, the fourth reference signal V R4 will decrease in accordance with the increase of the programmable current I P4 .

Besides, when the fourth reference signal V R4 is smaller than the mirror signal V M , an output voltage of the output terminal of the first amplifier 70 increases. In addition, it is well known in the art that the gate voltage of the output pass element 60 increases and a source-drain voltage of the output pass element 60 increases in response to the increase of the output voltage of the output terminal of the first amplifier 70 . Therefore, when the output voltage of the first amplifier 70 increases, the gate voltage and the source-drain voltage of the output pass element 60 both increase. Further, the output voltage V O decreases in response to the increase of the source-drain voltage of the output pass element 60 . In other words, the output voltage V O decreases in responses to the increase of the gate voltage of the output pass element 60 . According to above, it means that once the output voltage V O increases and the feedback signal V FB is lager than the third reference signal V R3 , the output voltage V O decreases and is limited by the third reference signal V R3 for achieving maximum voltage limit function.

Once the output current I O of the output pass element 60 increases in response to the increase of the load, the mirror signal V M will increase in response to the increase of the output current I O . When the mirror signal V M is lager than the fourth reference signal V R4 , the output voltage of the output terminal of the first amplifier 70 and the gate voltage of the output pass element 60 both increases. Therefore, the source-drain voltage of the output pass element 60 increases in response to the increase of the gate voltage of the output pass element 60 . Then, the output voltage V O decreases in response to the increase of the source-drain voltage of the output pass element 60 for achieving constant current.

Once the mirror signal V M is lower than the fourth reference signal V R4 , the output voltage of the output terminal of the first amplifier 70 decreases. It means that the gate voltage of the output pass element 60 decreases. Therefore, the source-drain voltage of the output pass element 60 decreases in response to the decrease of the gate voltage of the output pass element 60 . Then, the output voltage V O increases in response to the decrease of the source-drain voltage of the output pass element 60 for providing constant voltage.

According to above, the first amplifier 70 controls the output pass element 60 of the pass circuit to decrease the output voltage V O when the output current I O is high that the mirror signal V M is higher than the fourth reference signal V R4 . The first amplifier 70 controls the output pass element 60 of the pass circuit to increase the output voltage V O when the output current I O is low that the mirror signal V M is lower than the fourth reference signal V R4 .

Moreover, operating conditions of the soft-start function of the present invention show in FIG. 2 are as follows. When the unregulated DC input terminal VIN receives the input voltage V IN , the capacitor 89 is charged by the current source 75 for generating the fourth reference signal V R4 . The fourth reference signal V R4 increases gradually until reaching a maximum limit. The maximum limit is developed by the default setting of the amplitude of the current source 75 and the resistance of the resistor 76 .

Referring to the equation (3), the output current I O is correlated to the fourth reference signal V R4 and is limited by the fourth reference signal V R4 when the resistance of the resistor 81 is constant. Therefore, the output current I O increases gradually in respond to the increase of the fourth reference signal V R4 .

Further, referring to the equation (4), the output voltage V O is a constant voltage which is limited by the third reference signal V R3 . In other words, the third reference signal V R3 is the maximum voltage limit of this embodiment. In conclusion, this invention show in FIG. 2 disclosures a low drop-out regulator providing the maximum voltage limit according to the third reference signal V R3 , the soft-start function and the constant current according to default setting of the amplitude of the current source 75 and the resistance of the resistor 76 .

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims or their equivalents.