Low dropout regulators

1. Field of the Invention

The invention relates to power regulation, and more particularly, to low dropout (LDO) regulators capable of preventing damage caused by a short circuit or a heavy load.

2. Description of the Related Art

A regulator converts an unstable power supply voltage into a stable power supply voltage. A low dropout (LDO) regulator has a low input-to-output voltage difference between an input terminal where an unstable power supply voltage is inputted and an output terminal where a stable power supply voltage is outputted. “Dropout voltage” refers to the input-to-output voltage difference, whereby the regulator ceases to regulate against further reductions in input voltage. Ideally, the dropout voltage should be as low as possible, to allow the input voltage to be relatively low, while still maintaining regulation. Thus, assuring that the input-to-output voltage difference is low and minimizing power dissipation and maximizing efficiency are important.

Generally, the conventional LDO regulator includes a protection circuit such as an over-current protection circuit so as to protect the circuit during abnormal operating conditions. For example, the over-current protection circuit maintains the output current (IOUT) of the LDO at a predetermined current value and controls the LDO to reduce the output current (IOUT) when an output voltage (VOUT) thereof is lower than a predetermined value caused by a heavy load (i.e. a short circuit occurs).

However, the foldback voltage of the conventional LDO is not accurate, the foldback voltage is affected by ambient temperature and adjustment range of the foldback voltage is limited. Further, after the output voltage is foldback, the output current correlates with the ambient temperature, other circuit parameters and process parameters, and thus, control of the output current is difficult.

Embodiments of a low dropout regulator are provided, in which a pass transistor receives an unregulated power supply voltage to generate a regulated output voltage according to a control signal, a constant overcurrent limiting circuit limits an output current through the pass transistor to below a predetermined current, and a foldback overcurrent limiting circuit enables the constant overcurrent limiting circuit to further decrease the output current, when the regulated output voltage is lower than a predetermined voltage.

The invention provides an embodiment of an overcurrent protection circuit, in which a constant overcurrent limiting circuit limits an output current through a pass transistor below a predetermined current, and a foldback overcurrent limiting circuit enables the constant overcurrent limiting circuit to further decrease the output current, when the regulated output voltage is lower than a predetermined voltage.

The invention provides an embodiment of a method for providing overcurrent protection in a regulator, in which an output current through a pass transistor in the power regulator is limited to below a predetermined current by a constant overcurrent limiting circuit, and the predetermined current is decreased to enable the constant overcurrent limiting circuit to further decrease the output current according to the decreased predetermined current, when a regulated output voltage of the pass transistor is lower than a predetermined voltage.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an embodiment of a low dropout (LDO) regulator;

FIG. 2 shows an embodiment of the LDO regulator;

FIG. 3 shows another embodiment of the LDO regulator;

FIG. 4 shows another embodiment of the LDO regulator; and

FIG. 5 shows another embodiment of the LDO regulator.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 is a schematic diagram of an embodiment of a low dropout (LDO) regulator 100 mainly comprising a pass transistor PT, a driving circuit 10 , a feedback circuit 11 , and an overcurrent protection circuit 12 . The feedback circuit 11 comprises resistors R 1 and R 2 . An unregulated power supply voltage VIN is applied to a power line. The pass transistor PT receives the unregulated power supply voltage VIN and generates an output voltage that varies depending upon a control signal VG, and outputs to a load 13 . The feedback circuit 11 detects a current flowing through the pass transistor PT and generates a feedback signal VFB. The output voltage VOUT is divided by the resistors R 1 and R 2 , and the divided voltage of the output voltage VOUT becomes the feedback signal VFB.

The driving circuit 10 compares the feedback signal VFB with a reference voltage VREF 1 from a reference voltage generator and generates the control signal VG that varies depending upon the voltage difference between the reference signal VREF 1 and the feedback signal VFB. For example, the driving circuit 10 comprises an error amplifier, but is not limited thereto. In preferred embodiments, the reference voltage generator provides the reference voltage VREF 1 regardless of manufacturing process variations and/or temperature variations.

The overcurrent protection circuit 12 prevents the LDO regulator 100 from damage caused by overcurrent. The overcurrent protection circuit 12 comprises a constant overcurrent limiting circuit (COLC) 20 and a foldback overcurrent limiting circuit (FOLC) 30 . The COLC 20 detects an output current IOUT flowing through the pass transistor PT and limits the output current IOUT to below a predetermined current. For example, the COLC 20 detects the output current IOUT and pulls a voltage level of the gate terminal of the pass transistor PT high (i.e., increases the voltage level of the control signal VG) when the output current IOUT exceeds the predetermined current, thereby suppressing the increased output current IOUT.

Because the output current IOUT is limited by the COLC 20 , the output voltage VOUT decreases when a short circuit (i.e., a heavy load condition) occurs, such that the voltage across the pass transistor PT overly increases. In this example, the excessive voltage may burn out the pass transistor PT or some component in the LDO regulator 100 , such that the LDO regulator 100 fails to operate. However, the FOLC 30 enables the COLC 20 to further decrease the output current IOUT when the output voltage VOUT is lower than a predetermined voltage because of a short circuit (or a heavy load condition), thereby preventing damage caused by excessive voltage across the pass transistor PT. For example, the FOLC 30 decreases the predetermined current for limiting the output current IOUT when the output voltage VOUT is lower than the predetermined voltage, such that the COLC 20 further decreases the output current IOUT according to the decreased predetermined current. In some examples, the FOLC 30 can compare the output voltage VOUT with a reference voltage to determine whether the output voltage VOUT is higher than the predetermined voltage. Alternatively, the FOLC 30 can compare a division voltage of the output voltage VOUT with a reference voltage to determine whether the output voltage VOUT is higher than the predetermined voltage. The detailed operations of the overcurrent protection circuit 12 will be illustrated hereinafter.

FIG. 2 shows an embodiment of the LDO regulator. As shown, the LDO regulator 100 A is similar to the LDO regulator 100 in FIG. 1 , differing only, in that the COLC 20 A is implemented by a constant current source CS 1 , PMOS transistors MP 1 and MP 2 and NMOS transistors MN 1 and MN 2 , and the FOLC 30 A compares the output voltage VOUT with a reference voltage VREF 2 to determine whether a short circuit (a heavy load) has occurred. Operations of the components which are similar to that in the LDO regulator 100 are omitted for simplification.

The constant current source CS 1 is coupled between the unregulated power supply voltage VIN and a node ND 1 to provide a constant current I 1 . The NMOS transistor MN 1 comprises a drain terminal coupled to the node ND 1 , a source terminal coupled to a ground voltage, and a gate terminal coupled to the NMOS transistor MN 2 . The NMOS transistor MN 2 comprises a drain terminal coupled to a gate terminal thereof, and a source terminal coupled to the ground voltage, in which the size of the NMOS transistor MN 1 is in proportion to that of the NMOS transistor MN 2 . The NMOS transistors MN 1 and MN 2 form a current mirror, and a current I 2 A flowing through the NMOS transistor MN 1 is in proportion to a current I 2 B flowing through the NMOS transistor MN 2 . The current I 2 A can be regarded as a mirror current of the current I 2 B. The PMOS transistor MP 1 comprises a source terminal coupled to the unregulated power supply voltage VIN, a drain terminal coupled to a gate terminal of the PMOS transistor MP 2 , and a gate terminal coupled to the node ND 1 . The PMOS transistor MP 2 comprises a source terminal coupled to the unregulated power supply voltage VIN, a drain terminal coupled to the drain terminal of the NMOS transistor MN 2 , and a gate terminal coupled to the gate terminal of the pass transistor PT.

When the output voltage VOUT is higher than the reference voltage VREF 2 , the FOLC 30 A does not work. For example, the current I 3 can be zero, but is not limited thereto. Since the source terminals of the transistor MP 2 and pass transistor PT are both coupled to the unregulated power supply voltage VIN and the gate terminals are both coupled to the control signal VG from the driving circuit 10 , the current I 2 B through the PMOS transistor MP 2 is in proportion to the output current IOUT, and thus, the PMOS transistor MP 2 can be used to detect the output current IOUT flowing through the pass transistor PT. Because the current I 2 A is also in proportion to the current I 2 B, the current I 2 A is in proportion to the current IOUT. In this embodiment, the currents I 2 A and I 2 B increase as the output current increases, but is not limited thereto. In this case, the node ND 1 can be regarded as a current comparator comparing the current I 1 and the current I 2 A. When the current I 2 A is smaller than the current I 1 , the voltage level on the node ND 1 rises to high (close to the unregulated power supply voltage VIN). On the contrary, when the current I 2 B exceeds the current I 1 , the voltage on the node ND 1 falls (close to ground), such that the transistor MP 1 is turned on to pull high the gate terminal of the pass transistor PT, thereby overcurrent. In a steady condition, the current I 2 A is approximately equal to the current I 1 , and the output current IOUT can be limited below a predetermined current. Namely, the predetermined current is in direct proportion to the current I 1 provided by the constant current source CS 1 , and thus the predetermined current can be adjusted by increasing/decreasing the current I 1 .

In this embodiment, the FOLC 30 A drains out a current I 3 from the current I 1 to enable the COLC 20 A to further decrease the predetermined current, when the output voltage VOUT is lower than a predetermined voltage because of a short circuit (or a heavy load condition), the FOLC 30 A enables the COLC 20 A to further decrease the output current IOUT. For example, the current I 3 drained by the FOLC 30 A can be increased as the output voltage VOUT decreases, but is not limited thereto. At this time, the voltage on the node ND 1 falls when the current I 1 is smaller than the current (I 2 A+I 3 ), and the voltage on the node ND 1 rises when the current I 1 exceeds the current (I 2 A+I 3 ). Hence, the COLC 20 A further decrease the output current IOUT until the sum of the current I 2 A (which is proportion to the output current IOUT) and the current I 3 is approximately equal to the current I 1 provided by the constant current source CS 1 . Namely, it can be regarded as that the COLC 20 A limits the output current IOUT to below the decreased predetermined current. As a result, the output current IOUT decreases as the output voltage VOUT decreases, when a short circuit (or a heavy load condition) occurs. Thus, damage caused by a short circuit or a heavy load condition can be prevented.

FIG. 3 shows another embodiment of the LDO regulator. As shown, the LDO regulator 100 B is similar to the LDO regulator 100 A in FIG. 2 , differing only, in that constant current source CS 1 is replaced by a controllable current source CS 2 , the FOLC 30 A enables the current source CS 2 to decrease the predetermined current when the output voltage VOUT is lower than the predetermined voltage, such that the output current IOUT is further decreased as the output voltage VOUT decreases.

As mentioned in FIG. 2 , the predetermined current is in direct proportion to the current I 1 provided by the constant current source CS 1 , and thus, in this embodiment, the current source CS 2 decreases the current IS to decrease the predetermined current. At this time, the voltage level on the node ND 1 falls when the current I 2 A decreased exceeds the decreased current IS, and the voltage level on the node ND 1 rises when the current I 2 A is smaller than the decreased current IS. Namely, the COLC 20 A further decrease the output current IOUT until the current I 2 A (which is proportion to the output current IOUT) is approximately equal to the current IS deceased by the current source CS 2 . It can be regarded as that the COLC 20 A limits the output current IOUT to below the decreased predetermined current. As a result, the output current IOUT decreases as the output voltage VOUT decreases, when a short circuit (or a heavy load condition) occurs. Thus, damage caused by a short circuit or a heavy load condition can be prevented.

FIG. 4 shows another embodiment of the LDO regulator. As shown, the LDO regulator 100 C is similar to the LDO regulator 100 A in FIG. 2 , differing only, in that the COLC 20 B is implemented by a constant current source CS 3 , NMOS transistors NM 3 ˜MN 6 , PMOS transistors MP 3 ˜MP 7 and resistors R 3 ˜R 4 , and the FOLC 30 B is implemented by a constant current source CS 4 , PMOS transistors MP 9 ˜MP 9 and NMOS transistors MN 7 ˜MN 9 . Operations of the driving circuit 10 , the pass transistor PT and the resistors R 1 and R 2 are similar to that illustrated in FIG. 1 and thus, are omitted for simplification.

The PMOS transistor MP 3 comprises a source terminal coupled to a node ND 3 , a drain terminal coupled to a node NOUT, and a gate terminal coupled to the gate terminal of the pass transistor PT. The resistor R 3 is coupled between the unregulated power supply voltage VIN and the node ND 3 , and the PMOS transistor MP 4 comprises a source terminal coupled to the node ND 3 , a drain terminal coupled to a node ND 4 and a gate terminal coupled to the node ND 4 and a gate terminal of the PMOS transistor MP 5 . The resistor R 4 is coupled between the unregulated power supply voltage VIN and a source terminal of the PMOS transistor MP 5 , and the PMOS transistor MP 5 comprises a source terminal coupled to the resistor R 4 , a drain terminal coupled to a node ND 5 and a gate terminal coupled to the PMOS transistor MP 3 . The constant current source CS 3 is coupled between the unregulated power supply voltage VIN and a node ND 6 , and the NMOS transistor MN 3 comprises a drain terminal coupled to the node ND 6 , a source terminal coupled to the ground voltage, and a gate terminal coupled to the node ND 6 and the NMOS transistor MN 6 .

The NMOS transistor MN 4 comprises a drain terminal coupled to the node ND 4 , a gate coupled to the NMOS transistor MN 3 , and a source terminal coupled to the ground voltage. The NMOS transistor MN 5 comprises a drain terminal coupled to the node ND 5 , a gate coupled to the NMOS transistors MN 3 and MN 4 , and a source terminal coupled to the ground voltage GND. The NMOS transistor MN 6 comprises a drain terminal coupled to a node ND 7 , a source terminal coupled to the ground voltage, and a gate terminal coupled to the node ND 5 . The PMOS transistor MP 6 comprises a source terminal coupled to the unregulated power supply voltage VIN, a drain terminal coupled to the node ND 7 , and a gate terminal coupled to the node ND 7 and the PMOS transistor MP 7 . The PMOS transistor MP 7 comprises a source terminal coupled to the unregulated power supply voltage VIN, a gate terminal coupled to the PMOS transistor MP 6 , and a drain terminal coupled to the gate terminals of the pass transistor PT and the PMOS transistor MP 3 .

The constant current source CS 3 and the PMOS transistors MN 3 ˜MN 5 form a current source. In this embodiment, a current I 5 A flowing through the NMOS transistor MN 3 , is identical to a current I 5 B flowing through the NMOS transistor MN 4 and the PMOS transistor MP 4 , and a current I 5 C flowing through the NMOS MN 5 and the PMOS transistor MP 5 . Because a current I 4 provided by the constant current source CS 3 is equal to a sum of the current I 5 A (or I 5 B or I 5 C) and a current I 6 , the current I 5 A decreases as the current I 6 increases.

Since the gate terminals of the pass transistor PT and the PMOS transistor MP 3 are connected together and the drain terminals are connected to the node NOUT, a current I 7 flowing through the PMOS transistor MP 3 increases as the output current IOUT increases. Because the currents I 5 B and I 5 C flowing through the PMOS transistor MP 4 and MP 5 are limited by the NMOS transistors MN 4 and MN 5 , a current I 6 flowing through the resistor R 3 increases such that a voltage level at the node ND 3 accordingly decreases when the current I 7 increases.

Once the output current IOUT exceeds a predetermined current, the voltage level at the node ND 4 is decreased such that a voltage level at the node ND 5 is increased to turn on the NMOS transistor NM 6 . As the NMOS transistor MN 6 is turned on, a voltage level at the node ND 7 is pulled low, such that the PMOS transistors MP 6 and MP 7 are turned on. As a result, the voltage level at the gate terminals of the pass transistor PT and the PMOS transistor MP 3 is increased to decrease the output current IOUT, such that the output current IOUT can be limited to below the predetermined current. In this embodiment, the voltage level at the node ND 5 can be regarded as being more sensitive to that at the node ND 3 , as the current I 5 A decreases. Namely, the current I 5 A (which is identical to the currents I 5 B and I 5 C) is in direct ratio to the predetermined current. Thus, in this embodiment, the COLC 20 B can limit the output current IOUT to below a smaller predetermined current by decreasing the current I 5 A.

The NMOS transistor MN 7 comprises a drain terminal coupled to the node ND 6 , a gate coupled to the NMOS transistor MN 8 , and a source terminal coupled to the ground voltage. The constant current source CS 4 is coupled between the unregulated power supply voltage VIN and a node ND 8 . The PMOS transistor MN 8 comprises a source terminal coupled to the node ND 8 , a gate terminal coupled to a division voltage (i.e., A.VOUT) of the output voltage VOUT and a drain terminal coupled to the NMOS transistor MN 8 , in which the coefficient A is smaller than 1. The NMOS transistor MN 8 comprises a drain terminal coupled to the PMOS transistor MP 8 , a source terminal coupled to the ground voltage, and a gate terminal coupled to the drain terminal thereof and the gate terminal of the NMOS transistor MN 7 . The PMOS transistor MP 9 comprises a source terminal coupled to the node ND 8 , a gate terminal coupled to the reference voltage VREF 2 , and a drain terminal coupled to the NMOS transistor MN 9 . The NMOS transistor MN 9 comprises a drain terminal coupled to the PMOS transistor MP 9 , a gate terminal coupled to the drain terminal thereof, and a source terminal coupled to the ground voltage.

When the output voltage VOUT is lower than a predetermined voltage because of a short circuit (or a heavy load condition), the FOLC 30 B enables the COLC 20 B to further decrease the output current IOUT. For example, when the division voltage A.VOUT is higher than the reference voltage VREF 2 , the FOLC 30 B determines that the output voltage VOUT is not lower than a predetermined voltage and does not increase the current IX flowing through the NMOS transistor MN 7 . Namely, the FOLC 30 B does not drain out the current IX from the current I 4 to decrease the current I 5 A/I 5 B/I 5 C to further decrease the predetermined current.

On the contrary, once the division voltage A.VOUT is lower than the reference voltage VREF 2 , the FOLC 30 B determines that the output voltage VOUT is lower than the predetermined voltage, and thus, the current IX flowing through the NMOS transistor MN 7 is accordingly increased as the output voltage VOUT decreases. The current I 5 A decreases as the current IX is increased because the current I 4 is equal to the sum of the currents I 5 A and IX. Namely, when the output voltage VOUT is lower than the predetermined voltage, the FOLC 30 B decreases the current I 5 A, such that the predetermined current for limiting the output current OUT is decreased as the output voltage decreases. In this example, the COLC 20 B further decreases the output current IOUT according to the decreased predetermined current, i.e., the COLC 20 B limits the output current IOUT to below the decreased predetermined current. As a result, the output current IOUT decreases as the output voltage VOUT decreases, when a short circuit (or a heavy load condition) occurs. Thus, damage caused by a short circuit or a heavy load condition can be prevented.

FIG. 5 shows another embodiment of the LDO regulator. As shown, the LDO regulator 100 D is similar to the LDO regulator 100 C in FIG. 4 , differing only, in that the FOLC 30 C increases a ratio of the current I 8 to the output current IOUT to further decrease the predetermined current when the output voltage VOUT is smaller than the predetermined voltage, rather than changing the current I 5 A. Operations of the COLC 20 C are similar to that illustrated in FIG. 4 and thus, are omitted for simplification.

The FOLC 30 C comprises a comparator 31 , two switching elements SW 1 ˜SW 2 , and a PMOS transistor MP 10 . The PMOS transistor MP 10 comprises a source terminal coupled to the node ND 3 , a drain terminal coupled to the node NOUT, and a gate coupled to the switching elements SW 1 and SW 2 , in which the size of the PMOS transistor MP 10 is N times that of the PMOS transistor MP 3 . The switching element SW 1 comprises a first terminal coupled to the gate terminal of the PMOS transistor MP 10 and a second terminal coupled to the gate terminals of the pass transistor PT and the PMOS transistor MP 3 , and the switching element SW 2 is coupled between the unregulated power supply voltage VIN and the gate terminal of the PMOS transistor MP 10 . The comparator 31 comprises a first input terminal coupled to the reference voltage VREF 2 , a second input terminal coupled to the division voltage A.VOUT of the output voltage VOUT and an output terminal coupled to the switching elements SW 1 and SW 2 .

For example, when the division voltage A.VOUT is higher than the reference voltage VREF 2 , the FOLC 30 C determines that the output voltage VOUT is not lower than a predetermined voltage. As a result, the comparator 31 outputs a control signal VC to turn the switching element SW 1 and SW 2 off and on respectively, such that the PMOS transistor MP 10 is turned off. The FOLC 30 C detects whether the output current IOUT exceeds the predetermined current by the PMOS transistor MP 3 as illustrated in FIG. 4 to limit the output current IOUT to below the predetermined current. At this time, a current I 8 is equal to the current I 7 flowing through the PMOS transistor MP 3 .

On the contrary, when the division voltage A.VOUT is lower that the reference voltage VREF 2 because of a short circuit (or a heavy load condition), the FOLC 30 C determines that the output voltage VOUT is lower than the predetermined voltage. As a result, the comparator 31 outputs the control signals VC to turn the switching element SW 1 and SW 2 on and off respectively, mad the PMOS transistor MP 10 is turned on to increase the current I 8 . In this embodiment, the currents I 7 and I 9 are both in direct ratio to the output current IOUT. The current I 8 can be equal to a sum of the current I 7 flowing through the PMOS transistor MP 3 and a current I 9 flowing through the PMOS transistor MP 10 . The ratio of the current I 8 to the output current IOUT is increased to (I 7 +I 9 ):IOUT from I 7 :IOUT.

As such, the current I 6 flowing through resistor R 3 is greatly increased, the voltage level of the node ND 3 is accordingly decreased, and the voltage level at the node ND 5 is increased. As a result, the NMOS transistor MN 6 is turned on to pull the node ND 7 lower, such that the PMOS transistors MP 6 and MP 7 are turned on. Hence, the voltage level at the gate terminals of the pass transistor PT and the PMOS transistor MP 3 is increased to further decrease the output current IOUT. Hence, the COLC 20 C can limit the output current IOUT to below the decreased predetermined current.

Because the LDO regulators 100 and 100 A˜ 100 D of the embodiments can further decrease the output current as the output voltage decreases when a short circuit or a heavy load occurs, damage caused by short circuit or a heavy load condition can be prevented.

Certain terms are used throughout the description and claims to refer to particular system components. As one skilled in the art will appreciate, consumer electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function.

Although the invention has been described in terms of preferred embodiment, it is not limited thereto. Those skilled in the art can make various alterations and modifications without departing from the scope and spirit of the invention. Therefore, the scope of the invention shall be defined and protected by the following claims and their equivalents.