Apparatus and method for encoding and decoding channel in a communication system using low-density parity-check codes

This application claims priority under 35 U.S.C. §119(a) to a Korean Patent Application filed in the Korean Intellectual Property Office on Feb. 18, 2008 and assigned Serial No. 10-2008-0014649, a Korean Patent Application filed in the Korean Intellectual Property Office on Feb. 29, 2008 and assigned Serial No. 10-2008-0019373, a Korean Patent Application filed in the Korean Intellectual Property Office on Nov. 25, 2008 and assigned Serial No. 10-2008-0117264, and a Korean Patent Application filed in the Korean Intellectual Property Office on Jan. 30, 2009 and assigned Serial No. 10-2009-0007662, the disclosures of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates generally to a communication system using Low-Density Parity-Check (LDPC) codes, and more particularly, to a channel encoding/decoding apparatus and method for generating LDPC codes of a particular type.

2. Description of the Related Art

In wireless communication systems, link performance significantly decreases due to various noises in channels, a fading phenomenon, and Inter-Symbol Interference (ISI). Therefore, in order to realize high-speed digital communication systems requiring high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable internet, it is necessary to develop a technology for overcoming noises, fading, and ISI. Recently, an intensive study was conducted relating to the use of an error-correcting code in increasing communication reliability by efficiently recovering distorted information.

An LDPC code, which was first introduced by Gallager in the 1960s, has been underutilized due to its complex implementation that could not be resolved by past technology. However, turbo code, which was discovered by Berrou, Glavieux, and Thitimajshima in 1993, shows the performance approximating Shannon's channel limit. Thus, research has been conducted on iterative decoding and graph-based channel encoding along with analyses on performance and characteristic of the turbo code. Due to this research, the LDPC code was restudied in the late 1990s, which proved that LDPC code has performance approximating Shannon's channel limit if it undergoes decoding by applying iterative decoding based on a sum-product algorithm on a Tanner graph (a special case of a factor graph) corresponding to the LDPC code.

The LDPC code is typically represented using a graph representation technique, and many characteristics can be analyzed through the methods based on graph theory, algebra, and probability theory. Generally, a graph model of channel codes is useful for description of codes. By mapping information on encoded bits to vertexes in the graph and mapping relations between the bits to edges in the graph, it is possible to consider a communication network in which the vertexes exchange predetermined messages through the edges. This makes it possible to derive a natural decoding algorithm. For example, a decoding algorithm derived from a trellis, which can be regarded as a kind of graph, can include the well-known Viterbi algorithm and a Bahl, Cocke, Jelinek and Raviv (BCJR) algorithm.

The LDPC code is generally defined as a parity-check matrix, and can be expressed using a bipartite graph, which is referred to as a Tanner graph. In the bipartite graph vertexes constituting the graph are divided into two different types, and the LDPC code is represented by the bipartite graph composed of vertexes, some of which are called variable nodes and the other of which are called check nodes. The variable nodes are mapped one-to-one to the encoded bits.

With reference to FIGS. 1 and 2 , a description will be made of a graph representation method for the LDPC code.

FIG. 1 shows an example of a parity-check matrix H 1 of the LDPC code composed of 4 rows and 8 columns. Referring to FIG. 1 , since the number of columns is 8, an LDPC code generates a length-8 codeword, and the columns are mapped to 8 encoded bits.

FIG. 2 is a diagram illustrating a Tanner graph corresponding to H 1 of FIG. 1 .

Referring to FIG. 2 , the Tanner graph of the LDPC code is composed of 8 variable nodes x 1 ( 202 ), x 2 ( 204 ), x 3 ( 206 ), x 4 ( 208 ), x 5 ( 210 ), x 6 ( 212 ), x 7 ( 214 ) and x 8 ( 216 ), and 4 check nodes 218 , 220 , 222 and 224 . An i th column and a j th row in the parity-check matrix H 1 of the LDPC code are mapped to a variable node x i and a j th check node, respectively. In addition, a value of 1, i.e., a non-zero value, at the point where an i th column and a j th row in the parity-check matrix H 1 of the LDPC code cross each other, indicates that there is an edge between the variable node x i and the j th check node on the Tanner graph as shown in FIG. 2 .

In the Tanner graph of the LDPC code, a degree of the variable node and the check node is defined as the number of edges connected to each respective node, and the degree is equal to the number of non-zero entries in a column or row corresponding to the associated node in the parity-check matrix of the LDPC code. For example, in FIG. 2 , degrees of the variable nodes x 1 ( 202 ), x 2 ( 204 ), x 3 ( 206 ), x 4 ( 208 ), x 5 ( 210 ), x 6 ( 212 ), x 7 ( 214 ) and x 8 ( 216 ) are 4, 3, 3, 3, 2, 2, 2 and 2, respectively, and degrees of check nodes 218 , 220 , 222 and 224 are 6, 5, 5 and 5, respectively. In addition, the numbers of non-zero entries in the columns of the parity-check matrix H 1 of FIG. 1 , which correspond to the variable nodes of FIG. 2 , are equal to their degrees 4, 3, 3, 3, 2, 2, 2 and 2. The numbers of non-zero entries in the rows of the parity-check matrix H 1 of FIG. 1 , which correspond to the check nodes of FIG. 2 , are equal to their degrees 6, 5, 5 and 5.

In order to express degree distribution for the nodes of the LDPC code, a ratio of the number of degree-i variable nodes to the total number of variable nodes is defined as f i , and a ratio of the number of degree-j check nodes to the total number of check nodes is defined as g i . For instance, for the LDPC code corresponding to FIGS. 1 and 2 , f 2 = 4/8, f 3 =⅜, f 4 =⅛, and f i =0 for i≠2, 3, 4; and g 5 =¾, g 6 =¼, and g j =0 for j≠5, 6. When a length of the LDPC code, i.e., the number of columns, is defined as N, and the number of rows is defined as N/2, the density of non-zero entries in the entire parity-check matrix having the above degree distribution is computed as Equation (1).

In Equation (1), as N increases, the density of ‘1’s in the parity-check matrix decreases. Generally, as for the LDPC code, since the code length N is inversely proportional to the density of non-zero entries, the LDPC code with a large N has a very low density of non-zero entries. The wording ‘low-density’ in the name of the LDPC code originates from the above-mentioned relationship.

Next, with reference to FIG. 3 , a description will be made of characteristics of a parity-check matrix of a structured LDPC code to be applied in the present invention. FIG. 3 schematically illustrates an LDPC code adopted as the standard technology in Digital Video Broadcasting-Satellite transmission 2 nd generation (DVB-S2), which is one of the European digital broadcasting standards.

In FIG. 3 , N 1 denotes a length of an LDPC codeword, K 1 provides a length of an information word, and (N 1 −K 1 ) provides a parity length. Further, integers M 1 and q are determined to satisfy q=(N 1 −K 1 )/M 1 . Preferably, K 1 /M 1 should also be an integer.

Referring to FIG. 3 , a structure of a parity part, i.e., K 1 th column through (N 1 −1) th column, in the parity-check matrix, has a dual diagonal shape. Therefore, as for degree distribution over columns corresponding to the parity part, all columns have a degree ‘2’, except for the last column having a degree ‘1’.

In the parity-check matrix, a structure of an information part, i.e., 0 th column through (K 1 −1) th column, is made using the following rules.

Rule 1: A total of K 1 /M 1 column groups are generated by grouping K 1 columns corresponding to the information word in the parity-check matrix into multiple groups each composed of M 1 columns. A method for forming columns belonging to each column group follows Rule 2 below.

Rule 2: Positions of ‘1’s in each 0 th column in i th column groups (where i=1, . . . , K 1 /M 1 ) are first determined. When a degree of a 0 th column in each i th column group is denoted by D i , if positions of rows with 1 are assumed to be R i,0 (1) , R i,0 (2) , . . . , R i,0 (D i ) , positions R i,j (k) (k=1, 2, . . . , D i ) of rows with 1 are defined as Equation (2), in a j th column (where j=1, 2, . . . , M 1 −1) in an i th column group.

R i,j (k) =R i,(j−1) (k) +q mod( N 1 −K 1 ),  (2)

k=1, 2, . . . , D i , i=1, . . . , K 1 /M 1 , j=1, . . . , M 1 −1

According to the above rules, it is can be appreciated that degrees of columns belonging to an i th column group (where i=1, . . . , K 1 /M 1 ) are all equal to D i . For a better understanding of a structure of a DVB-S2 LDPC code that stores information on the parity-check matrix according to the above rules, the following detailed example will be described.

As a detailed example, for N 1 =30, K 1 =15, M 1 =5 and q=3, three sequences for the information on the positions of rows with 1 for 0 th columns in 3 column groups can be expressed as follows. Herein, these sequences are called “weight-1 position sequences” for convenience.

R 1,0 (1) =0 , R 1,0 (2) =1 , R 1,0 (3) =2,

R 2,0 (1) =0 , R 2,0 (2) =11 , R 2,0 (3) =13,

R 3,0 (1) =0 , R 3,0 (2) =10 , R 3,0 (3) =14.

Regarding the weight-1 position sequence for 0 th columns in each column group, only the corresponding position sequences can be expressed as follows for each column group. For example:

0 1 2

0 11 13

0 10 14.

In other words, the i th weight-1 position sequence in the i th line sequentially represents the information on the positions of rows with 1 in the i th column group.

It is possible to generate an LDPC code having the same concept as that of a DVB-S2 LDPC code of FIG. 4 , by forming a parity-check matrix using the information corresponding to the detailed example, and Rule 1 and Rule 2.

It is known that the DVB-S2 LDPC code designed in accordance with Rule 1 and Rule 2 can be efficiently encoded using the structural shape. Respective steps in a process of performing LDPC encoding using the DVB-S2 based parity-check matrix will be described below by way of example.

In the following description, as a detailed example, a DVB-S2 LDPC code with N 1 =16200, K 1 =10800, M 1 =360 and q=15 undergoes an encoding process. For convenience, information bits having a length K 1 are represented as (i 0 , i 1 , . . . , i K i −1 ), and parity bits having a length (N 1 −K 1 ) are expressed as (p 0 , p 1 , . . . , p N i −K i−1 ).

p 0 =p 1 = . . . =p N i K i −1 =0

Step 2: The LDPC encoder reads information on a row where 1 is located in a column group from a 0 th weight-1 position sequence out of the stored sequences indicating the parity-check matrix.

0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622

R 1,0 (1) =0 , R 1,0 (2) =2048 , R 1,0 (3) =1613 , R 1,0 (4) =1548 , R 1,0 (5) =1286,

R 1,0 (6) =1460 , R 1,0 (7) =3196 , R 1,0 (8) =4297 , R 1,0 (9) =2481 , R 1,0 (10) =3369,

R 1,0 (11) =3451 , R 1,0 (12) =4620 , R 1,0 (13) =2622.

The LDPC encoder updates particular parity bits p x in accordance with Equation (3) using the read information and the first information bit i 0 . Herein, x denotes a value of R 1,0 (k) for k=1, 2, . . . , 13.

p 0 =p 0 i 0 , p 2084 =p 2064 i 0 , p 1613 =p 1613 i 0 ,

p 1548 =p 1548 i 0 , p 1286 =p 1286 i 0 , p 1460 =p 1460 i 0 ,

p 3196 =p 3196 i 0 , p 4297 =p 4297 i 0 , p 2481 =p 2481 i 0 ,

p 3369 =p 3369 i 0 , p 3451 =p 3451 i 0 , p 4620 =p 4620 i 0 ,

p 2622 =p 2622 i 0   (3)

In Equation (3), p x =p x i 0 can also be expressed as p x ←p x i 0 , and denotes binary addition.

Step 3: The LDPC encoder first finds out a value of Equation (4) for the next 359 information bits i m (where m=1, 2, . . . , 359) after i 0 .

{ x +( m mod M 1 )× q } mod( N 1 −K 1 ), M 1 =360, m=1, 2, . . . , 359  (4)

In Equation (4), x denotes a value of R 1,0 (k) for k=1, 2, . . . , 13. It should be noted that Equation (4) has the same concept as Equation (2).

Next, the LDPC encoder performs an operation similar to Equation (3) using the value found in Equation (4). That is, the LDPC encoder updates p {x+(m mod M 1 )×q} mod(N 1 −K 1 ) for i m . For example, for m=1, i.e., for i 1 , the LDPC encoder updates parity bits p(x+q)mod(N 1 −K 1 ) as defined in Equation (5).

p 15 =p 15 i 1 , p 2009 =p 2009 i 1 , p 1628 =p 1628 i 1 ,

p 1563 =p 1563 i 1 , p 1301 =p 1301 i 1 , p 1475 =p 1475 i 1 ,

p 3211 =p 3211 i 1 , p 4312 =p 4312 i 1 , p 2496 =p 2496 i 1 ,

p 3384 =p 3384 i 1 , p 3466 =p 3466 i 1 , p 4635 =p 4635 i 1 ,

p 2637 =p 2637 i 0   (5)

It should be noted that q=15 in Equation (5). The LDPC encoder performs the above process for m=1, 2, . . . , 359, in the same manner as shown above.

Step 4: As in Step 2, the LDPC encoder reads information of the 1 st weight-1 position sequence (k=1, 2, . . . , 13) for a 361 st information bit i 360 , and updates a particular p x , where x denotes R 2,0 (k) . The LDPC encoder updates p {x+(m mod M 1 )×q} mod(N 1 −K 1 ) , m=361, 362, . . . , 719 by similarly applying Equation (4) to the next 359 information bits i 361 , i 362 , . . . , i 719 after i 360 .

Step 5: The LDPC encoder repeats Steps 2, 3 and 4 for all groups each having 360 information bits.

p i =p i p i−1 , i= 1, 2, . . . , N 1 −K 1 −1  (6)

The parity bits p i of Equation (6) are parity bits that undervent LDPC encoding.

As described above, in DVB-S2, the LDPC encoder performs LDPC encoding through the process of Step 1 through Step 6.

It is well known that performance of the LDPC code is closely related to cycle characteristics of the Tanner graph. In particular, it is well known by experiments that performance degradation may occur when the number of short-length cycles is great in the Tanner graph. Thus, the cycle characteristics on the Tanner graph should be considered in order to design LDPC codes having high performance.

However, no method has been proposed that designs DVB-S2 LDPC codes having good cycle characteristics. For the DVB-S2 LDPC code, an error floor phenomenon is observed at a high Signal to Noise Ratio (SNR) as optimization on cycle characteristics of the Tanner graph is not considered. For these reasons, there is a need for a method capable of efficiently improving cycle characteristics in designing LDPC codes having the DVB-S2 structure.

The present invention has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the present invention provides a channel encoding/decoding apparatus and method for designing a parity-check matrix of a quasi-cyclic LDPC code designed based on a circulant permutation matrix to design a DVB-S2 LDPC code in a communication system using LDPC codes.

Another aspect of the present invention provides a channel encoding/decoding apparatus and method for designing a parity-check matrix of the same LDPC code as the DVB-S2 LDPC code having a good Tanner graph characteristic in a communication system using LDPC codes.

According to one aspect of the present invention, a method is provided for generating a parity-check matrix of a Low-Density Parity-Check (LDPC) code. Parameters for designing the LDPC code are determined. A first parity-check matrix of a quasi-cyclic LDPC code is formed according to the determined parameters. A second parity-check matrix is created through the elimination of a predetermined portion of a parity part in the first parity-check matrix. A third parity-check matrix is created by rearranging the second parity-check matrix.

According to another aspect of the present invention, a method is provided for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. A stored parity-check matrix is read. A received signal is LDPC-encoded using the stored parity-check matrix. The parity-check matrix is divided into an information word and a parity. When a code rate is ⅗ and a length of a codeword is 16200, the parity-check matrix is formed as defined in the following table;

According to a further embodiment of the present invention, a method is provided for decoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. A parity-check matrix of the LDPC code is extracted. LDPC decoding is performed using the extracted parity-check matrix. The extracted parity-check matrix is divided into a parity and an information word. When a code rate is ⅗ and a length of a codeword is 16200, the parity-check matrix is formed as defined in the following table;

According to an additional aspect of the present invention, an apparatus is provided for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. An LDPC code parity-check matrix extractor reads a stored parity-check matrix. An LDPC encoder LDPC-encodes a received signal using the stored parity-check matrix. The parity-check matrix is divided into a parity and an information word. When a code rate is ⅗ and a length of a codeword is 16200, the parity-check matrix is formed as defined in the following table;

According to another further aspect of the present invention, an apparatus is provided for decoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. An LDPC code parity-check matrix extractor reads a stored parity-check matrix. An LDPC decoder performs LDPC decoding using the read parity-check matrix. The read parity-check matrix is divided into a parity and an information word. When a code rate is ⅗ and a length of a codeword is 16200, the read parity-check matrix is formed as defined in the following table;

The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

FIG. 1 is a diagram illustrating a parity-check matrix of a length-8 LDPC code;

FIG. 2 is a diagram illustrating a Tanner graph of a parity-check matrix of a length-8 LDPC code;

FIG. 3 is a diagram illustrating a schematic structure of a DVB-S2 LDPC code;

FIG. 4 is a diagram illustrating a parity-check matrix of a DVB-S2 LDPC code;

FIG. 5 is a diagram illustrating a parity-check matrix generated by rearranging columns and rows in the parity-check matrix of the DVB-S2 LDPC code of FIG. 4 according to predetermined rules, according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a parity-check matrix of a quasi-cyclic LDPC code necessary for designing a DVB-S2 LDPC code, according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating the result obtained by transforming the parity-check matrix of the quasi-cyclic LDPC code necessary for design of a DVB-S2 LDPC code, according to an embodiment of the present invention;

FIG. 8 is a flowchart illustrating a process of designing a DVB-S2 LDPC code, according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a computer simulation result on the DVB-S2 LDPC code, according to an embodiment of the present invention;

FIG. 10 is a block diagram illustrating a structure of a transceiver in a communication system using the redesigned DVB-S2 LDPC code, according to an embodiment of the present invention;

FIG. 11 is a block diagram illustrating a structure of a transmission apparatus using an LDPC code, according to an embodiment of the present invention;

FIG. 12 is a block diagram illustrating a structure of a reception apparatus using an LDPC code, according to an embodiment of the present invention; and

FIG. 13 is a flowchart illustrating a reception operation in a reception apparatus using an LDPC code, according to an embodiment of the present invention.

Preferred embodiments of the present invention are described in detail with reference to the annexed drawings. The same or similar components are designated by the same or similar reference numerals although they are illustrated in different drawings. Detailed descriptions of constructions or processes known in the art may be omitted to avoid obscuring the subject matter of the present invention.

The present invention provides a method for designing a DVB-S2 LDPC code having a good Tanner graph characteristic. In addition, the present invention provides a method for generating an LDPC codeword using a parity-check matrix of the above-designed LDPC code and an apparatus thereof.

Structural characteristics of a DVB-S2 LDPC code are described below using a parity-check matrix of a DVB-S2 LDPC code shown in FIG. 4 . For the parity-check matrix shown in FIG. 4 , N 1 =30, K 1 =15, M 1 =5 and q=3, and weight-1 position sequences of rows for 0 th columns in three column groups are as follows:

0 1 2

0 11 13

0 10 14

Here, an i th weight-1 position sequence in the i th line sequentially represents the information on the positions of rows with 1 in the i th column group.

The parity-check matrix of FIG. 4 is reconstructed in accordance with the following rules. FIG. 4 is a diagram illustrating a parity-check matrix of a DVB-S2 LDPC code.

Rule 3: 0 th row through (N 1 −K 1 −1) th row are rearranged so that a (q·i+j) th row is located in an (M 1 ·j+i) th row, where 0≦i≦M 1 and 0≦j<q.

Rule 4: With 0 th column through (K 1 −1) th column being kept intact, K 1 th column through (N 1 −1) th column are rearranged so that a (K 1 +q·i+j) th column is located in a (K 1 +M 1 ·j+i) th column.

A parity-check matrix with a shape shown in FIG. 5 is obtained by reconstructing the parity-check matrix of FIG. 4 in accordance with Rule 3 and Rule 4. FIG. 5 illustrates a parity-check matrix generated by rearranging columns and rows in the parity-check matrix of the DVB-S2 LDPC code of FIG. 4 according to predetermined rules, according to an embodiment of the present invention.

If it is assumed in FIG. 5 that ‘1’ exists in an (N 1 −1) th column at a 0 th row, it can be appreciated that the parity-check matrix in FIG. 5 corresponds to a kind of a quasi-cyclic LDPC code consisting of a circulant permutation matrix with a size of M 1 ×M 1 , i.e. 5×5. The ‘circulant permutation matrix’ is defined as a kind of a permutation matrix created by circular-shifting rows in identity matrixes rightward one by one. In addition, the ‘quasi-cyclic LDPC code’ is defined as a sort of an LDPC code created by dividing a parity-check matrix into several blocks with the same size and mapping circulant permutation matrixes or zero matrixes to the blocks.

In summary, it can be understood that a parity-check matrix similar to the quasi-cyclic LDPC code can be obtained by reconstructing a parity-check matrix of the DVB-S2 LDPC code through Rule 3 and Rule 4. Also, it is expected that the DVB-S2 LDPC code can be generated from the quasi-cyclic LDPC code through the reverse process of Rule 3 and Rule 4.

While there is no known research result on the DVB-S2 LDPC code, there are many known design methods for the quasi-cyclic LDPC code. The design methods for the quasi-cyclic LDPC code include well-known methods for optimizing cycle characteristics on the Tanner graph.

An embodiment of the present invention proposes a method for designing a DVB-S2 LDPC code using the well-known method for improving cycle characteristics on the Tanner graph of the quasi-cyclic LDPC code. However, since the method for improving cycle characteristics of the quasi-cyclic LDPC code is only indirectly related to the present invention, a detailed description thereof will be omitted for simplicity.

A description of a method for designing a DVB-S2 LDPC code using a quasi-cyclic LDPC code is provided below. The DVB-S2 LDPC code has a codeword length NJ, an information length K 1 , and a parity length (N 1 −K 1 ), and q=(N 1 −K 1 )/M 1 .

A parity-check matrix of a quasi-cyclic LDPC code is shown in FIG. 6 . FIG. 6 is a diagram illustrating a parity-check matrix of a quasi-cyclic LDPC code necessary for designing a DVB-S2 LDPC code, according to an embodiment of the present invention. The parity-check matrix shown in FIG. 6 has (N 1 −K 1 ) rows and N 1 columns, and is divided into M 1 ×M 1 partial blocks. For convenience, if t—K 1 /M 1 , an information part and a parity part in the parity-check matrix of FIG. 6 consist of t column blocks and q column blocks, respectively, and have a total of q row blocks. Here, N 1 /M 1 =t+q.

The respective partial blocks constituting the parity-check matrix of FIG. 6 correspond to circulant permutation matrixes or zero matrixes. Here, the circulant permutation matrix has a size of M 1 ×M 1 , and is created based on a circulant permutation matrix P, which is defined as:

P

=

[

0

1

0

…

0

0

0

1

…

0

0

0

0

…

0

⋮

⋮

⋮

⋱

1

1

0

0

…

0

]

In FIG. 6 , a ij has an integer of 0 through M 1 −1 or a value of ∞, P 0 is defined as an identity matrix I, and P ∞ denotes an M 1 ×M 1 zero matrix. Also, numerals ‘0’ in the parity part denote M 1 ×M 1 zero matrixes.

The parity-check matrix of FIG. 6 is characterized in that column blocks corresponding to the parity have identity matrixes I and a circulant permutation matrix P M 1 −1 as shown in the drawing. In other words, the column blocks corresponding to the parity are fixed to the structure shown in FIG. 6 . The circulant permutation matrix P M 1 −1 is defined as:

The quasi-cyclic LDPC code shown in FIG. 6 is the part that remains unchanged in the process of optimizing cycles of the quasi-cyclic LDPC code as the structures of column blocks corresponding to its parity part are fixed. In other words, since the column blocks corresponding to the parity part are fixed in the parity-check matrix of FIG. 6 , the connections between variable nodes corresponding to the parity are determined on the Tanner graph, so it only needs to optimize the connections between variable nodes corresponding to the information part in order to optimize cycles of the Tanner graph.

As described above, there are many known methods for optimizing cycle characteristics on the Tanner graph of the quasi-cyclic LDPC code. Since the design method for the quasi-cyclic LDPC code with a Tanner graph having the optimized cycle characteristics is only indirectly related to the present invention, a detailed description thereof is omitted herein.

It is assumed that degree distribution is determined to show excellent performance in the state where the structure of the parity part is fixed in the quasi-cyclic parity-check matrix of FIG. 6 through the design method for the quasi-cyclic LDPC code. Positions of the circulant permutation matrix and the zero matrixes are determined in the column blocks corresponding to the information part according to the degree distribution. Cycle characteristics of the Tanner graph are optimized.

The form shown in FIG. 7 , for example, can be made by eliminating ‘1’ in the last column at the first row in the circulant permutation matrix P M 1 −1 corresponding to the last (N 1 /M 1 ) th or (t+q) th column block at the first row block in the parity-check matrix of FIG. 6 . FIG. 7 is a diagram illustrating the result obtained by transforming the parity-check matrix of the quasi-cyclic LDPC code necessary for design of a DVB-S2 LDPC code, according to an embodiment of the present invention.

It should be noted that the circulant permutation matrix P M 1 −1 is changed to the following matrix Q in FIG. 7 .

Q

=

[

0

0

…

0

0

1

0

…

0

0

0

1

…

0

0

⋮

⋮

⋱

⋮

0

0

0

…

1

0

]

The following Rule 5 and Rule 6 are defined to apply the reverse process of Rule 3 and Rule 4.

Rule 5: With 0 th column through (K 1 −1) th column being kept intact, K 1 th column through (N 1 −1) th column are rearranged so that a (K 1 +M 1 ·j+i) th column is located in a (K 1 +q·i+j) th column, where 0≦i<M 1 and 0≦j<q.

Rule 6: 0 th row through (N 1 −K 1 −1) th row are rearranged so that an (M 1 ·j+i) th row is located in a (q·i+j) th row.

The parity-check matrix of the LDPC code generated from the quasi-cyclic LDPC code of FIG. 6 through the above-described process by applying Rule 5 and Rule 6 becomes the parity-check matrix having the form of the DVB-S2 LDPC code shown in FIG. 3 , for example. The above-described method for designing a DVB-S2 parity-check matrix, in which its codeword, information and parity lengths are N 1 , K 1 and (N 1 −K 1 ), respectively, and q=(N 1 −K 1 )/M 1 , can be summarized into the following process.

DVB-S2 LDPC Code Design Process

FIG. 8 is a flowchart illustrating a process of designing a DVB-S2 LDPC code according to an embodiment of the present invention.

Referring to FIG. 8 , parameters necessary for designing a desired DVB-S2 LDPC code are determined in step 801 . It is assumed herein that the parameters such as a codeword length and an information length as well as the good degree distribution are previously determined to design the DVB-S2 LDPC code.

Next, in step 803 , a parity-check matrix of a quasi-cyclic LDPC code consisting of M 1 ×M 1 circulant permutation matrixes and zero matrixes as shown in FIG. 6 is formed according to the parameters determined in step 801 . In FIG. 6 , column blocks corresponding to a parity part are always fixed to a particular form.

In step 805 , circulant permutation matrixes of column blocks corresponding to an information part in FIG. 6 are determined by applying an algorithm for improving cycle characteristics of a Tanner graph of the quasi-cyclic LDPC code. Any known algorithm for improving cycle characteristics can be used herein.

In step 807 , a parity-check matrix shown in FIG. 7 , for example, is obtained by eliminating ‘1’ in the last column at the first row in the parity-check matrix of FIG. 6 , which has been settled in step 805 .

In step 809 , columns and rows in the parity-check matrix of FIG. 7 are rearranged by applying Rule 5 and Rule 6 to the parity-check matrix of FIG. 7 . The finally obtained parity-check matrix can be the DVB-S2 LDPC code shown in FIG. 3 , for example.

A codeword can be generated by applying the above-described DVB-S2 LDPC encoding process to the LDPC code designed through the above steps.

To analyze performance of the DVB-S2 LDPC code, a DVB-S2 LDPC code having the following parameters was designed. For example,

N 1 =648000 , K 1 =38880 , M 1 =360 , q= 72

To design rate-⅗ DVB-S2 LDPC codes having the above parameters, parity-check matrixes shown in Table 1 and Table 2, for example, can be obtained from a quasi-cyclic LDPC code having a total of N/M 1 =180 column blocks and q=(N 1 −K 1 )/M 1 =72 row blocks by applying the DVB-S2 LDPC code design process. An i th weight-1 position sequence in an i th column sequentially represents the information on the positions of rows with 1 in an i th column group.

In addition, a DVB-S2 LDPC code having the following parameters was designed. For example,

N 1 =16200 , K 1 =9720 , M 1 =360 , q= 18

To design rate-⅗ DVB-S2 LDPC codes having the above parameters, parity-check matrixes shown in Table 3 through and Table 6, for example, can be obtained from a quasi-cyclic LDPC code having a total of N 1 /M 1 =45 column blocks and q=(N 1 −K 1 )/M 1 =18 row blocks by applying the DVB-S2 LDPC code design process. It is noted that an i th weight-1 position sequence in an i th column sequentially represents the information on the positions of rows with 1 in an i th column group.

A performance comparison between the newly designed DVB-S2 LDPC code and the existing DVB-S2 LDPC code is shown in FIG. 9 . FIG. 9 is a diagram illustrating a computer simulation result on the DVB-S2 LDPC code according to an embodiment of the present invention.

It can be appreciated that when an Additive White Gaussian Noise (AWGN) channel uses a Binary Phases Shift Key (BPSK) modulation scheme, performance improvement of approximately 0.15 dB is made at BER=10 −4 . The performance improvement of a rate-⅗ DVB-S2 LDPC code can be achieved by simply changing information about the parity-check matrix as shown in Table 1 through Table 6.

The DVB-S2 LDPC code design process described with reference to FIG. 8 can be used not only for the code rate of ⅗ but also for other code rates. A DVB-S2 LDPC code having the following parameters was designed as an example for designing a DVB S2 LDPC code having another code rate.

N 1 =64800 , K 1 =43200 , M 1 =360 , q= 60

To design rate-⅔ DVB-S2 LDPC codes having the above parameters, parity-check matrixes shown in Table 7 through and Table 10, for example, can be obtained from a quasi-cyclic LDPC code having a total of N 1 /M 1 =180 column blocks and q=60 row blocks by applying the DVB-S2 LDPC code design process of FIG. 8 .

FIG. 10 is a block diagram illustrating a structure of a transceiver in a communication system using the redesigned DVB-S2 LDPC code, according to an embodiment of the present invention.

Referring to FIG. 10 , a message u is input to an LDPC encoder 1011 in a transmitter 1010 before being transmitted to a receiver 1030 . Then the LDPC encoder 1011 encodes the input message u and provides the encode signal c to a modulator 1013 . The modulator 1013 modulates the encoded signal and transmits the modulated signal s to the receiver 1030 through a wireless channel 1020 . Then a demodulator 1031 in the receiver 1030 demodulates the signal r transmitted by the transmitter 1010 , and outputs the demodulated signal x to an LDPC decoder 1033 . Then the LDPC decoder 1033 calculates an estimation value u of the message from the data received through the wireless channel.

A detailed structure of a transmission apparatus in the communication system using the redesigned DVB-S2 LDPC code is shown in FIG. 11 . FIG. 11 is a block diagram illustrating a structure of a transmission apparatus using the redesigned LDPC code according to an embodiment of the present invention.

The transmission apparatus includes a controller 1130 , an LDPC code parity-check matrix extractor 1110 and an LDPC encoder 1150 .

The LDPC code parity-check matrix extractor 1110 extracts an LDPC code parity-check matrix according to the requirements of the system. The LDPC code parity-check matrix can be extracted from the sequence information shown in Table 1 through Table 10, can be extracted using a memory in which the parity-check matrix is stored, can be given in the transmission apparatus, or can be generated in the transmission apparatus.

The controller 1130 is adapted to determine a necessary parity-check matrix according to a code rate, a codeword length, or an information length to meet the requirements of the system.

The LDPC encoder 1150 performs encoding based on the LDPC code parity-check matrix information read by the controller 1130 and the LDPC code parity-check matrix extractor 1110 .

FIG. 12 is a block diagram illustrating a structure of a reception apparatus according to an embodiment of the present invention.

FIG. 12 illustrates a reception apparatus for receiving the signal transmitted from the communication system using the redesigned DVB-S2 LDPC code and recovering user-desired data from the received signal.

The reception apparatus includes a controller 1250 , a parity-check matrix decider 1230 , an LDPC code parity-check matrix extractor 1270 , a demodulator 1210 and an LDPC decoder 1290 .

The demodulator 1210 demodulates a received LDPC code, and provides the demodulated signal to the parity-check matrix decider 1230 and the LDPC decoder 1290 .

The parity-check matrix decider 1230 , under the control of the controller 1250 , decides the parity-check matrix of the LDPC code used in the system based on the demodulated signal.

The controller 1250 provides the decision result from the parity-check matrix decider 1230 to the LDPC code parity-check matrix extractor 1270 and the LDPC decoder 1290 .

The LDPC code parity-check matrix extractor 1270 , under the control of the controller 1250 , extracts the parity-check matrix of the LDPC code required by the system, and provides the extracted parity-check matrix to the LDPC decoder 1290 . As stated above, the parity-check matrix of the LDPC code can be extracted from the sequence information shown in Table 1 through Table 10, can be extracted using a memory in which the parity-check matrix is stored, can be given in the transmission apparatus, or can be generated in the transmission apparatus.

The LDPC decoder 1290 , under the control of the controller 1250 , performs decoding based on the received signal provided from the demodulator 1210 and the information on the LDPC code's parity-check matrix provided from the LDPC code parity-check matrix extractor 1270 .

An operation flowchart of the reception apparatus in FIG. 12 is shown in FIG. 13 .

In step 1301 , the demodulator 1210 receives a signal transmitted from the communication system using the redesigned DVB-S2 LDPC code and demodulates the received signal. Thereafter, in step 1303 , the parity-check matrix decider 1230 makes a decision on a parity-check matrix of the LDPC code used in the system based on the demodulated signal.

The decision result from the parity-check matrix decider 1230 is provided to the LDPC code parity-check matrix extractor 1270 in step 1305 . The LDPC code parity-check matrix extractor 1270 extracts a parity-check matrix of the LDPC code required by the system, and provides it to the LDPC decoder 1290 in step 1307 .

As mentioned above, the parity-check matrix of the LDPC code can be extracted from the sequence information shown in Table 1 through Table 10, can be extracted using a memory in which the parity-check matrix is stored, can be given in the transmission apparatus, or can be generated in the transmission apparatus.

Thereafter, in step 1309 , the LDPC decoder 1290 performs decoding based on the information about the LDPC code's parity-check matrix provided from the LDPC code parity-check matrix extractor 1270 .

As is apparent from the foregoing description, the present invention optimizes characteristics of the Tanner graph in designing the DVB-S2 LDPC code, thereby optimizing performance of the communication system using the LDPC code.

While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.