Quick response width modulation for a voltage regulator

The present invention is related generally to voltage regulators and, more particularly, to a circuit and method for improving the load transient response of voltage regulators.

In modern voltage regulator systems for microprocessor core voltage controlling, multi-phase control has been a popular control method for adapting high power density and high current slew rate requirements. However, conventional multi-phase control method is still insufficient to meet these ultra high load transient requirements in recent generations' voltage regulator (VR) specifications defined by Intel, especially during load application transient. Accordingly, an open-loop control mechanism called quick response was developed to overcome the undershoot problem. During load application transient, the quick response mechanism will instantaneously turn on all phases' upper gate (UG) to fully supply heavy load current demand, and the output voltage droop can therefore be controlled into correct load line specification. Even so, the quick response function still has some defects. For example, inaccurate turn-on or turn-off of quick response may result in unexpected ring back or second undershoot of output voltage.

FIG. 1 is a block diagram of an interleaving pulse width modulation (PWM) voltage regulator system with conventional quick response control scheme, which includes N phases, phase 1 , phase 2 , . . . , phase N, where N is a natural number, parallel connected between a power input V IN and a power output V OUT . Each phase has a power stage 10 connected to the power input V IN and power output V OUT , and a PWM comparator 12 to decide a pulse width modulation signal PWM j , j=1, 2, . . . , or N, for the power stage 10 of this phase. In order to generate the per-phase pulse width modulation signals PWM 1 , PWM 2 , . . . , PWM N , voltage divider resistors R 1 and R 2 divide the output voltage V OUT to generate a feedback signal V FB , an error amplifier 14 compensates the error between the feedback signal V FB and a reference signal V REF and provides an amplified error signal V COMP into the positive inputs of each PWM comparator 12 , and each PWM comparator 12 compares the error signal V COMP with a ramp signal V RAMP to decide the pulse width modulation signal PWM j of the corresponding phase. Each of the power stages 10 is controlled by the pulse width modulation signal PWM j of the corresponding phase to switch one or more power switches thereof, so as to generate the phase currents IL 1 , IL 2 , . . . , ILN, whose combination is the load current I LOAD supplying for the load 16 . The function of quick response is implemented by a quick response generation circuit 18 and per-phase combiners 20 . The quick response generation circuit 18 monitors the error signal V COMP to decide a quick response signal QR which triggers a quick response pulse when a load transient occurs. Each combiner 20 inserts the quick response pulse into the pulse width modulation signal PWM j of the corresponding phase. Alternatively, the quick response generation circuit 18 monitors the output voltage V OUT or the feedback signal V FB instead, in order to trigger the quick response pulse.

FIG. 2 is a simplified block diagram of a per-phase feedback control circuit extracted from FIG. 1 for detailed description about the conventional quick response control scheme. In order for particular distinction, the reference signals for the error amplifier 14 and the quick response comparator 22 are denoted by V REF1 and V REF2 respectively. The positive and negative inputs of a quick response comparator 22 receive the reference signal V REF2 and feedback signal V FB respectively, to decide the quick response signal QR. The input voltages of the quick response comparator 22 , V REF2 and V FB , are so designed to meet the circumstance that under steady state operation, V REF2 will always be lower than V FB and hence the output of the quick response comparator 22 will always be zero. Therefore, the pulse width modulation signal PWM will always be determined only by the output of the PWM comparator 12 in steady state. Moreover, V REF2 is so designed to meet the circumstance that V REF2 will approach V FB , either V REF2 rising or V FB falling, during load application. When V REF2 is higher than V FB , the output QR of the quick response comparator 22 goes high and the output of the combiner 20 goes high according to the quick response pulse. Hence, during load application, the pulse width modulation signal PWM is determined not only by the output of the PWM comparator 12 but also by the output of the quick response comparator 22 . In other words, the quick response pulse will be inserted into the normal pulse width modulation signal PWM and dominates the PWM pulse width during instant load application.

FIG. 3 is a timing diagram illustrating an operation mode of the conventional quick response control scheme in a four phase voltage regulator. At time t 1 , the load current I LOAD transits from I MIN to I MAX , and the output voltage V OUT of the voltage regulator drops accordingly. At the moment the output voltage V OUT drops, the quick response comparator 22 will assert the quick response signal QR to instantaneously turn on all the pulse width modulation signals PWM 1 -PWM 4 of the interleaved phases to supply this high load current demand. At time t 2 , the quick response period ends and the per-phase inductor currents are raised to a higher level, but the delay of gate signal transmission and per-phase inductor current imbalance cause the output voltage V OUT to exhibit a period of ringback phenomenon 24 . After time t 2 , the pulse width modulation signal PWM 3 restarts its original PWM pulse and the subsequent PWM pulses will automatically adjust their pulse widths to regulate the output voltage V OUT to the desired level. However, the system will suffer a long period of current imbalance until the end of time t 3 . The time length of current imbalance depends on the quick response trigger point, quick response duration, inductor current level, restart point of the pulse width modulation signal PWM, . . . etc. This current imbalance phenomenon may cause unexpected ringback or short-term ringing of output voltage V OUT and hence increases the amount of output bulk or decoupling capacitors.

In order to resolve these defects of conventional quick response, a circuit and method of per-phase current balancing and pulse width adjustment of quick response is proposed. Altogether, the proposed new algorithm of quick response can achieve perfect adaptive voltage positioning (AVP) function without unnecessary undershoot or ringback of output voltage during load transient.

An object of the present invention is to provide a circuit with accurately controlled quick response signal.

Another object of the present invention is to provide a method with accurately controlled on-trigger edge, off-trigger edge and the width of a quick response signal.

Yet another object of the present invention is to provide a quick response multi-phase voltage regulator.

Still another object of the present invention is to provide a quick response method for a multi-phase voltage regulator.

According to the present invention, a quick response generation circuit for a voltage regulator includes two quick response comparators to compare a feedback signal related to the output voltage of the voltage regulator with two reference signals respectively, to determine a set signal and a reset signal. In response to the set signal and reset signal, a per-phase quick response signal determines a quick response pulse to be inserted into the pulse width modulation signal of the corresponding phase. The quick response pulse will force the upper power switch of the corresponding phase on, to connect the power input to the power output of the voltage regulator.

According to the present invention, a method for generating a quick response signal for a voltage regulator includes comparing a feedback signal related to the output voltage of the voltage regulator with two reference signals respectively, to determine a set signal and a reset signal which decide the on-trigger edge, off-trigger edge and the pulse width of the quick response signal.

According to the present invention, a multi-phase voltage regulator includes a power input, a power output to provide an output voltage, an error amplifier to generate an error signal from the difference between a feedback signal related to the output voltage and a reference signal, two PWM comparators to generate two pulse width modulation signals according to the error signal and two ramp signals to control two power stages to generate two phase currents respectively. Each of the power stages has a power switch connected between the power input and power output. Two quick response generation circuits provide two quick response signals to insert two quick response pulses into the two pulse width modulation signals to turn on the two power switches respectively. The two quick response pulses have different widths.

According to the present invention, a quick response method for a multi-phase voltage regulator includes generating two quick response signals to insert two quick response pulses into two pulse width modulation signals to turn on two upper power switches in two power stages of the multi-phase voltage regulator respectively. The two quick response pulses have different widths.

These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of an interleaving PWM voltage regulator system with conventional quick response control scheme;

FIG. 2 is a simplified block diagram of a per-phase feedback control circuit extracted from FIG. 1 for detailed description about the conventional quick response control scheme;

FIG. 3 is a timing diagram illustrating an operation mode of the conventional quick response control scheme in a four phase voltage regulator;

FIG. 4 is a block diagram of an interleaving PWM voltage regulator system with proposed quick response width modulation control scheme;

FIG. 5 is a timing diagram illustrating an operation mode of proposed quick response width modulation control scheme;

FIG. 6 is a simplified block diagram of per-phase feedback control circuit extracted from FIG. 4 to illustrate the proposed quick response width modulation control scheme;

FIG. 7 is a modification of the quick response generation circuit shown in FIG. 6 ;

FIG. 8 is an embodiment equivalent to the quick response generation circuit of FIG. 7 ;

FIG. 9 is an embodiment to insert a quick response signal into the positive input of the PWM comparator; and

FIG. 10 is an embodiment to insert a quick response signal into the negative input of the PWM comparator.

A system according to the present invention contains two control loops, the first is the original PWM loop which contains an error amplifier and a PWM comparator to generate the original PWM signal, and the second is quick response loop which generates quick response signals. The quick response signals can be modulated according to some signals and therefore, they are separate from each other in a multi-phase voltage regulator.

FIG. 4 is a block diagram of an interleaving PWM voltage regulator system with proposed quick response width modulation (QRWM) control scheme, which includes N phases parallel connected between a power input V IN and a power output V OUT . Each phase has a power stage 10 connected to the power input V IN and power output V OUT , a PWM comparator 12 to decide a pulse width modulation signal PWM j , j=1, 2, . . . , or N, for the power stage 10 of this phase, a quick response generation circuit 26 to generate a quick response signal QR j , j=1, 2, . . . , or N, which triggers a quick response pulse during load transient, and a combiner 20 to insert the quick response pulse into the pulse width modulation signal PWM j of this phase. The power stages 10 provide phase currents IL 1 , IL 2 , . . . , ILN respectively that are combined to be a load current I LOAD supplying for a load 16 . Divider resistors R 1 and R 2 divide the output voltage V OUT of the voltage regulator to generate a feedback signal V FB , an error amplifier 14 compensates the error between the feedback signal V FB and a reference signal V REF and provides an amplified error signal V COMP to the positive input of each PWM comparator 12 , and each PWM comparator 12 compares the error signal V COMP with a ramp signal V RAMP to decide the pulse width modulation signal PWM j of the corresponding phase. In addition to be controlled by the corresponding pulse width modulation signal PWM j , each power stage 10 further provides its phase current signal I PHASE(j) , j=1, 2, . . . , or N, to a summation circuit 28 and the quick response generation circuit 26 of its phase. All the phase current signals I PHASE(1) -I PHASE(N) are summed up by the summation circuit 28 and then divided by the phase number N by a division circuit 30 , to generate an average current signal I AVG provided to each quick response generation circuit 26 . Each quick response generation circuit 26 generates the quick response signal QR j , j=1, 2, . . . , or N, according to the average current signal I AVG , phase current signal I PHASE(j) of its corresponding phase, and error signal V COMP . In each phase, the quick response signal QR j and the output of the PWM comparator 12 are combined by a combiner 20 to be the pulse width modulation signal PWM j . In other embodiments, the quick response generation circuit 26 may monitor the output voltage V OUT or the feedback signal V FB , instead of the error signal V COMP , in order to decide the quick response signal QR j . Since the quick response signals QR 1 -QR N are generated per phase by the respective quick response generation circuit 26 , the on-trigger edge, off-trigger edge and pulse width of each quick response signal QR j can be decided phase by phase. Namely, the quick response signals QR 1 -QR N of this voltage regulator system may not be the same.

FIG. 5 is a timing diagram illustrating an operation mode of proposed quick response width modulation control scheme. At time t 1 , the load current I LOAD transits from I MIN to I MAX , and the output voltage V OUT drops accordingly. The set signal of the quick response is unique in this embodiment, which means each interleaved phase the same set signal and per-phase PWM will turn on at the same time when the quick response is triggered. As shown in FIG. 5 , at the moment V OUT dropping, all the quick response generation circuits 26 triggers their own quick response signal QR j simultaneously. However, the reset signal of the quick response is different among the interleaved phases and will be determined by each phase's own quick response generation circuit 26 . Therefore, the turn-off edge of each quick response signal QR 1 -QR N will be different and is related to their own phase current, that is, the phase which has the largest phase current during the load application will have the shortest quick response pulse width. The larger the phase current is, the earlier the quick response of the corresponding phase terminates. As a result, the quick response widths of the interleaved phases may not be the same. This mechanism forces each phase's inductor current to be balanced during load application transient. As shown in FIG. 5 , the quick response signal QR 3 is turned off first, then take turns to QR 2 , QR 1 , till time t 2 the quick response signal QR 4 is turned off in the end. Therefore, the time points of the phase currents IL 1 -IL 4 beginning to fall down are different and the current imbalance after the load transient is reduced or even eliminated. This current-adjusting scheme for quick response width modulation can reduce the ringback 24 and improve the settling of the output voltage V OUT .

In further detail, FIG. 6 is a simplified block diagram of per-phase feedback control circuit extracted from FIG. 4 to illustrate the proposed quick response width modulation control scheme. In this embodiment, the quick response generation circuit 26 includes quick response comparators 32 , 34 and a SR flip-flop 36 . The quick response comparator 32 compares the feedback signal V FB with a reference signal V REF2 to decide the setting input of the SR flip-flop 36 , and the quick response comparator 34 compares the feedback signal V FB with a reference signal V REF3 to decide the resetting input of the SR flip-flop 36 . Under steady state operation, the output of the quick response comparator 32 will always stay low, the output of the SR flip-flop 36 will always be zero, and the pulse width modulation signal PWM decided by the PWM comparator 12 alone. During load application transient, the on-trigger edge of the quick response signal QR will be determined by the quick response comparator 32 and the off-trigger edge of the quick response signal QR will be determined by the quick response comparator 34 . Hence the turn-on edge position, turn-off edge position and pulse width of the quick response signal QR can be adjusted according to the designed values of V REF2 and V REF3 . If all the quick response generation circuits 26 of FIG. 4 are designed as having a same value of V REF2 but having different values of V REF3 , the quick response signals QR 1 -QR N will be triggered at a same time but terminated at different times. The right side of FIG. 6 shows a part circuit of the power stage 10 , which receives the pulse width modulation signal PWM to switch the upper power switch SW thereof. During load application transient, the quick response pulse of the quick response signal QR is inserted into the output of the PWM comparator 12 through the combiner 20 , and forces the upper power switch SW to be on so as to increase the ability of providing the phase current. In this embodiment, the circuit of generating the quick response signal QR is implemented by the SR flip-flop 36 ; in other embodiments, the SR flip-flop 36 may be replaced by other element or circuit able to assert the quick response signal QR.

FIG. 7 is a modification of the quick response generation circuit 26 shown in FIG. 6 . A combiner 38 subtracts a bias voltage V DC1 from the reference signal V REF to generate the reference signal V REF2 (=V REF −V DC1 ) as the positive input of the quick response comparator 32 , and a combiner 40 adds a bias voltage V DC2 to the reference signal V REF to generate the reference signal V REF3 (=V REF +V DC2 ) as the negative input of the quick response comparator 34 . To generate the bias voltage V DC2 , the difference between the per-phase current signal I PHASE and average current signal I AVG is obtained by a combiner 42 , and then transformed into the bias voltage V DC2 by a transducer 44 having a transform function f 1 . The set signal of quick response is determined by the quick response comparator 32 . When load application transient occurs, if the feedback signal V FB drops below V REF2 (=V REF −V DC1 ), then the quick response comparator 32 sends out a set signal S to initiate quick response. The reset signal of quick response is determined by the quick response comparator 34 . If V FB rises above V REF3 (=V REF +V DC2 ), then the quick response comparator 34 will send out a reset signal R to terminate quick response. In this embodiment, the values of V DC1 and V DC2 will determine the turn-on threshold and turn-off threshold of quick response scheme in which V DC1 and V DC2 can be different between the interleaved phases, e.g., V DC2 is a function f 1 dependent of per-phase error current signal such that V DC2 =f 1 ×(I PHASE −I AVG ), which means per-phase reset signals R of quick response will be different depending on their sensed phase currents I PHASE . The transform function f 1 will transform per-phase current signal I PHASE into suited bias voltage V DC2 and f 1 can be any kind of arithmetic transformation.

A person who is skilled in this art-should understand that a signal enters into the positive input of a comparator is equivalent to a negative of the signal enters into the negative input of the comparator. FIG. 8 shows an embodiment equivalent to the quick response generation circuit 26 of FIG. 7 . The combiner 38 adds the bias voltage V DC1 to the feedback signal V FB as the negative input (V FB +V DC1 ) of the quick response comparator 32 , and the combiner 40 subtracts the bias voltage V DC2 from the feedback signal V FB as the positive input (V FB −V DC2 ) of the quick response comparator 34 . The bias voltage V DC2 is generated by the same way as that shown in FIG. 7 . V DC1 is a constant voltage designed for DC level shifting applications and V DC2 is a function f 1 dependent of per-phase current I PHASE such that V DC2 =f 1 ×(I PHASE −I AVG ). The transducer 44 will transform per-phase error current signal into suited voltage signal V DC2 and the function f 1 can be any kind of arithmetic transformation. Therefore, each interleaved phase's quick response signal QR is different and the pulse width of each phase's quick response signal QR will be dependent on their sensed current signals. More equivalent circuits to insert the bias voltages V DC1 and V DC2 into the quick response comparators 32 and 34 may be designed based on the same principle.

A person who is skilled in this art should understand that a signal can be inserted everywhere into a PWM loop for a same purpose. FIG. 9 provides an embodiment which inserts the quick response signal QR into the positive input of the PWM comparator 12 . The quick response comparators 32 and 34 and the SR flip-flop 36 are configured as that shown in FIG. 6 . The set signal S is determined by the quick response comparator 32 which compares V FB with V REF2 . The reset signal R is determined by the quick response comparator 34 which compares V FB with V REF3 . The output of the SR flip-flop 36 , the modulated quick response signal QR, is transformed by a transducer 46 into a suited voltage signal to modulate the original error signal V COMP by the combiner 20 . The transform function f 2 of the transducer 46 can be any kind of arithmetic transformation. The purpose of inserting the quick response signal QR into the positive input of the PWM comparator 12 is also to modulate each phase's PWM signal, in order to instantaneously turn on the upper switches of each power stage 10 to supply load application transient, and to achieve the same function as the embodiment of FIG. 6 .

Alternatively, the embodiment shown in FIG. 10 inserts the quick response signal QR into the negative input of the PWM comparator 12 . In this case, the output of the SR flip-flop 36 , i.e. the modulated quick response signal QR, is transformed by a transducer 48 whose transform function f 3 can be any kind of arithmetic transformation, into a suited voltage signal to modulate the original ramp signal V RAMP by the combiner 20 . The purpose and function of this embodiment are the same as that of FIG. 6 .

A person who is skilled in this art should understand that in other embodiments implementing the quick response pulse modulation scheme of FIG. 6 , the inputs (at positive input or negative input) of the quick response comparators 32 and 34 could be the output voltage of the voltage regulator, the output of the error amplifier 14 , the reference signal at the input of the error amplifier 14 , a sensed signal representative of the phase current, or any, other possible arithmetic combinations of these signals.

Although the quick response mechanism may have been developed and used for many years in VR applications, the key improvement of the proposed quick response width modulation scheme is that the system will not produce only single quick response signal shared by each interleaved phase, but will accurately control the trigger, terminate and pulse width of the quick response signal per-phase in a multi-phase voltage regulator, and further, modulate the pulse width of each phase's individual quick response signal according to per-phase current thereof. The modulated quick response signal can be inserted into anywhere of a normal control loop in each interleaved phase, such as the positive input of PWM comparator, the negative input of PWM comparator, the output of PWM comparator, the input of error amplifier, or the output of error amplifier. In conclusion, the quick response signal of each interleaved phase can be different, and thus the pulse width and starting-ending-position of quick response pulses of each interleaved phase can also be different. Separated quick response signal of each interleaved phase will result in better performance of VR systems, especially in load application transient for core voltage regulation.

While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.