Voltage regulator having a plurality of capacitors configured to obtain a feedback voltage from a division voltage

1. Field of the Invention

The invention relates to voltage regulators, and in particular to voltage regulators using switching elements and capacitors to serve as a feedback resistor.

2. Description of the Related Art

Power management control systems including voltage regulators are incorporated within portable electronic devices, such as laptop computers, hand-held electronic devices, and cellular phones, to generate a stable output voltage from a varying input voltage supply. The purpose of the voltage regulator is to regulate the external power supplied to the internal circuitry for efficient current usage or quiescent power. The useable operating voltage is called the “drop-out” voltage, which is the difference between the input and output voltages of regulator regulation. The smaller the difference, the more efficient the system. Additionally, batteries can supply only a finite amount of charge, so, the more quiescent current the regulator uses, the less operating lifespan the battery will have and therefore the system will be less efficient.

Embodiments of an electronic circuit are provided, in which a voltage regulation unit converts an input voltage to an output voltage by comparing a reference voltage and a feedback voltage. Additionally, a switching-capacitor circuit is coupled between the output voltage and the voltage regulation unit and comprises a plurality of switching elements and at least first and second capacitors. The first and second capacitor extracts a division voltage from the output voltage by charge sharing between the first and second capacitors to obtain the feedback voltage.

The invention provides an embodiment of an electronic circuit, in which a voltage regulation unit converts an input voltage to an output voltage by comparing a reference voltage and a feedback voltage, a first capacitor comprises a first terminal coupled to the output voltage, a first switching element comprises a first terminal coupled to the first terminal of the first capacitor and a second terminal coupled to a second terminal of the first capacitor, and a second switching element comprises a first terminal coupled to the second terminal of the first capacitor and the second terminal of the first switching element, and a second terminal coupled to the voltage regulation unit. A third switching element comprises a first terminal coupled to the second terminal of the second switching element, a second capacitor comprises a first terminal coupled to a second terminal of the third switching element, and a second terminal coupled to a ground voltage, and a fourth switching element comprises a first terminal coupled to a first terminal of the second capacitor and the second terminal of the third switching element and a second terminal coupled to the ground voltage.

The invention provides an embodiment of an electronic circuit, in which a voltage regulation unit converts an input voltage to an output voltage by comparing a reference voltage and a feedback voltage, a first switching element comprises a first terminal coupled to the output voltage, a first capacitor comprising a first terminal coupled to a second terminal of the first switching element and a second terminal coupled to a ground voltage, and a second switching element comprises a first terminal coupled to the first terminal of the first capacitor and the second terminal of the first switching element. A second capacitor comprises a first terminal coupled to a second terminal of the second switching element and a second terminal coupled to the ground voltage, a third switching element comprises a first terminal coupled to the second terminal of the second switching element and the first terminal of the second capacitor and a second terminal coupled to the ground voltage, and a fourth switching element comprises a first terminal coupled to the first terminal of the first capacitor and the second terminal of the first switching element and a second terminal coupled to the voltage regulation unit.

The invention provides an embodiment of a voltage regulator, in which an error amplifier comprises a first input terminal coupled to a reference voltage, a second input terminal coupled to a feedback voltage, and a transistor comprises a first terminal coupled to an input voltage, a control terminal coupled to an output terminal of the error amplifier and a second terminal outputting an output voltage. A switching-capacitor circuit is coupled between the output voltage and the error amplifier and comprises a plurality of switching elements and at least first and second capacitors. The switching elements are switched by non-overlapping clocks such that the second capacitor is discharged to a ground voltage during a first period, and the first and second capacitors are connected together during a second period thereby extracting a division voltage of the output voltage to serve as the feedback voltage.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows an embodiment of a voltage regulator;

FIG. 2 shows a diagram of a voltage regulator;

FIG. 3 shows another embodiment of a voltage regulator;

FIG. 4 shows a control timing chart of the switching elements in the switching-capacitor circuit shown in FIG. 3 ;

FIG. 5 shows another embodiment of the voltage regulator;

FIG. 6 shows a control timing chart of the switching elements in the switching-capacitor circuit shown in FIG. 5 ;

FIG. 7 shows another embodiment of a voltage regulator;

FIG. 8 shows another embodiment of a voltage regulator; and

FIG. 9 shows a control timing chart of the switching elements in the switching-capacitor circuit shown in FIG. 8 .

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 shows an embodiment of a voltage regulator. As shown, the voltage regulator 100 can be a low drop-out (LDO) voltage regulator or a low quiescent current regulator and comprises an error amplifier EA 0 , a PMOS pass transistor M 0 and a feedback resistor series 10 having a resistor series (i.e., resistors R 1 and R 2 ). When the output voltage Vout is designed to be larger than a predetermined voltage level and the current through the resistors R 1 and R 2 are limited, resistances of the resistor series (R 1 and R 2 ) are required to be very large such that the layout area thereof is accordingly increased. For example, when the output voltage Vout is designed to be 2.8V and the current through the resistors R 1 and R 2 are limited at 0.5 μA, the total resistance of the resistors R 1 and R 2 is required to be 5.6MΩ. Generally, a power management IC comprises more than 10 LDO voltage regulators, and thus, the feedback resistor series in all LDO voltage regulators would occupy an overwhelming majority of layout area when considering required low current.

In order to reduce layout are of such LDO voltage regulators in the power management IC, embodiments of the invention utilize a switching-capacitor (SC) circuit to be implemented as the feedback resistor.

FIG. 2 shows a diagram of a voltage regulator. As shown, voltage regulator 200 comprises a voltage regulator unit 20 and a switching-capacitor (SC) circuit 30 . For example, the voltage regulator 20 can be a low quiescent current regulator, a charge-pump circuit, a switching-mode power supply or a low drop-out (LDO) voltage regulator, but is not limited thereto. The voltage regulator unit 20 converts an input voltage Vdd to an output voltage Vout by comparing a reference voltage Vref and a feedback voltage Vbk. The switching-capacitor circuit 30 is coupled between the output voltage Vout and the voltage regulation unit 20 and comprises a plurality of switching elements and at least two capacitors (shown in following figures). The switching elements in the switching-capacitor circuit 30 are switched by non-overlapping clocks such that one capacitor is discharged to a bias voltage during a first period, and the two capacitors are connected together during a second period thereby obtaining a division voltage of the output voltage Vout and serving as the feedback voltage Vbk. Namely, the switching-capacitor circuit 30 performs a voltage-division to the output voltage Vout by charge sharing between the two capacitors to obtain the feedback voltage Vbk.

For example, the switching elements in the switching-capacitor circuit 30 are switched such that two terminals of one of the two capacitors are coupled to the output voltage Vout during a first period and the two capacitors are connected in series during a second period to obtain the division voltage of the output voltage Vout and serve as the feedback voltage Vbk. Alternatively, the switching elements in the switching-capacitor circuit are switched such that one of the two capacitors is charged by the output voltage Vout during a first period, and the two capacitors are connected in parallel to obtain the division voltage of the output voltage Vout and serve as the feedback voltage Vbk during the second period.

FIG. 3 shows another embodiment of a voltage regulator. As shown, a voltage regulator 300 comprises a voltage regulation unit 20 ″ converting the input voltage Vdd to the output voltage Vout and a switching-capacitor circuit 30 A providing the feedback voltage Vbk to the voltage regulation unit 20 ″ according to the output voltage Vout. The voltage regulation unit 20 ″ comprises an error amplifier EA 1 and a PMOS pass transistor M 1 . The error amplifier EA 1 comprises a first input terminal coupled to the reference voltage Vref, a second input terminal coupled to the feedback voltage Vbk, and an output terminal coupled to the transistor M 1 . The transistor M 1 comprises a first terminal coupled to the input voltage Vdd, a control terminal coupled to the output terminal of the error amplifier EA 1 and a second terminal outputting the output voltage Vout.

The voltage regulator unit 20 ″ converts the input voltage Vdd to the output voltage Vout by comparing the reference voltage Vref and the feedback voltage Vbk from the switching-capacitor circuit 30 A. For example, when the feedback voltage Vbk is higher than the reference voltage Vref, the error amplifier EA 1 lowers the voltage on the control terminal of the transistor M 1 such that the output voltage Vout is increased. On the contrary, when the feedback voltage Vbk is lower than the reference voltage Vref, the error amplifier EA 1 increases the voltage on the control terminal of the transistor M 1 such that the output voltage Vout is lowered. Thus, the voltage regulator unit 20 ″ can maintain the output voltage Vout at a desired voltage level according to the reference voltage Vref and the feedback voltage Vbk.

The switching-capacitor circuit 30 A comprises capacitors C 1 and C 2 and switching elements SW 1 ˜SW 4 . The capacitor C 1 has a first terminal coupled to the output voltage Vout and a second terminal coupled to the switching element SW 2 . The switching element SW 1 has a first terminal coupled to the first terminal of the capacitor C 1 , and a second terminal coupled to the second terminal of the capacitor C 1 . The switching element SW 2 has a first terminal coupled to the second terminal of the capacitor C 1 and a second terminal coupled a node ND 1 , in which the voltage at the node ND 1 serves as the feedback voltage Vbk. The switching element SW 3 has a first terminal coupled to the node ND 1 and a second terminal coupled to the capacitor C 2 and the switching element SW 4 . The capacitor C 2 has a first terminal coupled to the second terminal of the switching element SW 3 and a second terminal coupled to a bias voltage (here a ground voltage Gnd is served as the bias voltage). The switching element SW 4 has a first terminal coupled to the first terminal of the capacitor C 2 and a second terminal coupled to the ground voltage Gnd.

FIG. 4 shows a control timing chart of the switching elements in the switching-capacitor circuit shown in FIG. 3 . Operations of the switching-capacitor circuit 30 A are described with reference to FIGS. 3 and 4 . As shown, during a time period t 0 ˜t 1 , the switching elements SW 1 and SW 4 are tuned off and the switching elements SW 2 and SW 3 are turned on, the capacitors C 1 and C 2 extracts a division voltage from the output voltage Vout to serve as the feedback voltage Vbk (i.e., the voltage on the node ND 1 ). For example, the capacitors C 1 and C 2 extract the division voltage from the output voltage Vout by charge sharing therebetween to serve as the feedback voltage Vbk. During a time period t 1 ˜t 2 , all switching elements SW 1 ˜SW 4 are turned off. Because the switching elements SW 2 and SW 3 are turned off, the voltage at the node ND 1 (i.e., the feedback voltage Vbk) is maintained (i.e., the same as the last time period t 0 ˜t 1 ). Then, during a time period t 2 ˜t 3 , the switching elements SW 1 and SW 4 are turned on and the switching elements SW 2 and SW 3 are turned off, such that two terminals of the capacitor C 1 are both coupled to the output voltage Vout, and two terminals of the capacitor C 2 are both coupled to the ground voltage Gnd.

Next, during a time period t 3 ˜t 4 , all switching elements SW 1 ˜SW 4 are turned off again. During a time period t 4 ˜t 5 , the switching elements SW 1 and SW 4 are tuned off and the switching elements SW 2 and SW 3 are turned on, the capacitors C 1 and C 2 extracts a division voltage from the output voltage Vout again. Then, during a time period t 5 ˜t 6 , the switching elements SW 1 ˜SW 4 are turned off. Because the switching elements SW 2 and SW 3 are turned off, the voltage at the node ND 1 (i.e., the feedback voltage Vbk) is maintained (i.e., the same as the last time period t 4 ˜t 5 ).

During a time period t 6 ˜t 7 , the switching elements SW 1 and SW 4 are turned on and the switching elements SW 2 and SW 3 are turned off, such that two terminals of the capacitor C 1 are both coupled to the output voltage Vout, and two terminals of the capacitor C 2 are both coupled to the ground voltage Gnd both, and so on.

In this embodiment, the capacitor C 1 and the switching elements SW 1 and SW 2 can be regarded as a first resistor and the capacitor C 2 and the switching elements SW 3 and SW 4 can be regarded as a second resistor. Equivalent resistance of the first and second resistors can be considered as T 1 /C 11 and T 2 /C 22 respectively, in which C 11 represents the capacitance of the capacitor C 1 , C 22 represents the capacitance of the capacitor C 2 , T 1 represents the duty period of the switching element SW 1 and T 2 represents the duty period of the switching element SW 4 . For example, the resistance of 1MΩ can be obtained when the capacitor C 1 is 1 pF and the switching element SW 1 is operated at 1 MHz (i.e., duty period is 10 −6 sec). Namely, the resistance of the first and second resistors can be modified by different capacitances and different duty period of switching elements SW 1 ˜SW 4 .

FIG. 5 shows another embodiment of the voltage regulator. As shown, the voltage regulator 400 is similar to the voltage regulator 300 shown in FIG. 3 , except that a switching element SW 5 is coupled between the node ND 1 and the second input terminal of the error amplifier EA 1 . FIG. 6 shows a control timing chart of the switching elements in the switching-capacitor circuit shown in FIG. 5 . Operations of the switching-capacitor circuit in the voltage regulator 400 are described with reference to FIGS. 5 and 6 .

As shown, during a time period t 0 ˜t 1 , the switching elements SW 1 and SW 4 are tuned off and the switching elements SW 2 , SW 3 and SW 5 are turned on, the capacitors C 1 and C 2 extracts a division voltage from the output voltage Vout to serve the feedback voltage Vbk (i.e., the voltage on the node ND 1 ). At time t 1 , the switching elements SW 1 and SW 4 remain off and the switching elements SW 2 and SW 3 remain on, and the switching element SW 5 is turned off. Hence, the voltage at the second input terminal of the error amplifier EA 1 (i.e., the feedback voltage Vbk) is maintained (i.e., the same as the last time period t 0 ˜t 1 ).

At time period t 2 , the switching elements SW 1 , SW 4 and SW 5 remain off and the switching elements SW 2 and SW 3 are turned off. During a time period t 2 ˜t 3 , all switching elements SW 1 ˜SW 5 remain off. Then, during a time period t 3 ˜t 4 , the switching elements SW 2 , SW 3 and SW 5 remain off and the switching elements SW 1 and SW 4 are turned on such that two terminals of the capacitor C 1 are both coupled to the output voltage Vout, and two terminals of the capacitor C 2 are both coupled to the ground voltage Gnd both. Next, at time t 4 , the SW 2 , SW 3 and SW 5 remain off and the switching elements SW 1 and SW 4 are turned off. Then, during a time period t 4 ˜t 5 , all switching elements SW 1 ˜SW 5 remain off. The operations during time period t 5 ˜t 9 is similar to that during the time period t 0 ˜t 5 , and so on.

FIG. 7 shows another embodiment of a voltage regulator. As shown, a voltage regulator 500 is similar to the voltage regulator 300 shown in FIG. 3 , except that the capacitor C 2 is replaced by a variable capacitor C 3 . The variable capacitor C 3 comprises capacitors C 3 _ 0 ˜C 3 — n and switching elements SWC_ 1 ˜SWC_n. The capacitor C 3 _ 0 is coupled between a node ND 2 and the ground voltage Gnd, the capacitor C 3 _ 1 and the switching element SWC_ 1 are connected in series between the node ND 2 and the ground voltage Gnd, the capacitor C 3 _ 2 and the switching element SWC_ 2 are connected in series between the node ND 2 and the ground voltage Gnd, and so on. When the switching element SWC_ 1 is turned on, the capacitors C 3 _ 0 and C 3 _ 1 are connected in parallel and the capacitance of the variable capacitor C 3 is increased. When the switching elements SWC_ 1 ˜SWC_ 2 are both turned on, the capacitors C 3 _ 0 ˜C 3 _ 2 are connected in parallel and the capacitance of the variable capacitor C 3 is further increased, and so on. Namely, the more of the switching elements SWC_ 1 ˜SWC_n are turned on, the larger the capacitance of the variable capacitor C 3 . Operations of the voltage regulator 500 are similar to that of the voltage regulator 300 shown in FIG. 3 and thus, are omitted for brevity. The voltage regulator 500 can adjust voltage level of the output voltage Vout by tuning the capacitance of the variable capacitor C 3 .

FIG. 8 shows another embodiment of a voltage regulator. As shown, a voltage regulator 600 is similar to the voltage regulator 300 shown in FIG. 3 , except that the switching-capacitor circuit 30 A is replaced with a switching-capacitor circuit 30 B. The switching-capacitor circuit 30 B comprises switching elements SW 6 ˜SW 9 and capacitors C 4 ˜C 5 . The switching element SW 6 has a first terminal coupled to the output voltage Vout and a second terminal coupled to a node ND 3 . The capacitor C 4 has a first terminal coupled to the node ND 3 and a second terminal coupled to the ground voltage Gnd. The switching element SW 7 has a first terminal coupled to the node ND 3 and a second terminal coupled to a node ND 3 ″. The capacitor C 5 has a first terminal coupled to the node ND 3 ″ and a second terminal coupled to the ground voltage Gnd. The switching element SW 8 has a first terminal coupled to the node ND 3 ″ and a second terminal coupled to the ground voltage Gnd. The switching element SW 9 has a first terminal coupled to the node ND 3 and a second terminal coupled to the second terminal input terminal of the error amplifier EA 1 .

FIG. 9 shows a control timing chart of the switching elements in the switching-capacitor circuit shown in FIG. 8 . Operations of the switching-capacitor circuit 30 B are described with reference to FIGS. 8 and 9 .

As shown, during a time period t 0 ˜t 1 , the switching elements SW 6 and SW 8 are tuned off and the switching elements SW 7 and SW 9 are turned on, the capacitors C 1 and C 2 perform a voltage-division to the output voltage Vout to serve the feedback voltage Vbk. For example, the output voltage Vout stored in the capacitor C 4 charges the capacitor C 5 , i.e., charge sharing between capacitors C 4 and C 5 are executed, to extracts the division voltage of the output voltage Vout to serve as the feedback voltage Vbk.

At time t 1 , the switching elements SW 6 and SW 8 remain off and the switching elements SW 7 remains on, and the switching element SW 9 is turned off. Hence, the voltage at the second input terminal of the error amplifier EA 1 (i.e., the feedback voltage Vbk) is maintained (i.e., the same as the last time period t 0 ˜t 1 ). At time period t 2 , the switching elements SW 6 , SW 8 and SW 9 remain off and the switching element SW 7 is turned off. During a time period t 2 ˜t 3 , all switching elements SW 1 ˜SW 5 remain off.

Then, during a time period t 3 ˜t 4 , the switching elements SW 7 and SW 9 remain off and the switching elements SW 6 and SW 8 are turned on such that the capacitor C 4 is charged by the output voltage Vout and two terminals of the capacitor C 5 are both coupled to the ground voltage Gnd. Next, at time t 4 , the SW 7 and SW 9 remain off and the switching elements SW 6 and SW 8 are turned off. Then, during a time period t 4 ˜t 5 , all switching elements SW 6 ˜SW 9 remain off. The operations during time period t 5 ˜t 9 are repeated.

In some embodiments, the capacitor C 4 or the capacitor C 5 can be replaced with the variable capacitor C 3 shown in FIG. 7 for adjusting the output voltage Vout to a wanted voltage level. Because capacitance per unit is increased more and more in advanced semiconductor processes, it is more efficient to replace the feedback resistor with capacitors and switching elements and thus the layout area of the voltage regulator can be reduced. In some embodiment, the capacitors C 1 ˜C 5 or C 3 _ 0 ˜C 3 — n can also be implemented on the active devices during forming of metal-insulator-metal devices or metal-on-metal devices, and thus, the capacitors C 1 ˜C 5 or C 3 _ 0 ˜C 3 — n do not increase a chip's layout area.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.