Level shifter circuits and methods for maintaining duty cycle

This application claims the benefit of priority from U.S. Provisional Patent Application No. 61/020,437, filed Jan. 11, 2008, entitled “Low Power, High Speed, Duty Cycle Keeping, CMOS Level Shifter” the entire disclosure of which is hereby incorporated herein by reference.

The present invention relates to level shifting, and in particular, to level shifter circuits and methods for maintaining duty cycle in level shift circuits.

Modern electronic systems comprise a wide variety of digital devices for processing, transmitting and/or storing digital data. Processing, transmitting and storing digital data often depends on the timing of a clock and/or other signals. The quality of the clock source limits the performance possible for a digital electronic system. For example, the reliability of the timing of electronic gates and clocks within the system affect the time a system must wait (e.g. set up and hold times) to latch the data at an input terminal or to perform other functions with that data. The more unreliable the transition timing of the clock signal, the longer the setup and hold times required by the system, and the poorer the system performance.

Often, different portions of an electronic system use different digital rail voltage values. For example, it is known in the art to have digital integrated circuits that use one set of rail voltage values internally (e.g., 0 and 1.8 volts for the digital zero and one values), and another set of rail voltage values to drive output pins (e.g. 0 and 5 volts for the digital zero and one values). Similarly, is known to have a system which uses lower voltage rails for one group of circuits, but uses higher voltage rails to drive a set of cables, or to use lower voltage rail values for reading data from memory cells, while using higher voltage rail values to drive circuitry external to those memory cells (see U.S. Pat. No. 4,903,327, issued to Rao). See also U.S. Pat. No. Re. 34,808, issued to Hsieh, which discusses circuitry for converting signals using TTL voltage levels to different voltage levels.

FIG. 1 illustrates a prior art CMOS level shifter circuit 100 . Level shifter circuit 100 includes an inverter 101 coupled to a control terminal of a transistor 102 . Level shifter circuit 100 utilizes a voltage range from ground to V D0 at an input terminal 104 and a voltage range from ground to V D1 at an output terminal 105 . Voltage V D1 is greater than voltage V D0 . Unfortunately, there is a mismatch between the timing characteristics of input signal CLK in and output signal CLK out . This is because when transistor 102 turns off, the rise time of signal CLK out is slowed by the output impedance of circuit 100 (depending primarily upon the effect of resistor R and the capacitance (not shown) on output terminal 105 . In contrast, when signal CLK out falls, the output impedance is dominated by the on-resistance of transistor 102 (much lower than resistor R) and the above-mentioned capacitance. This mismatch of impedance skews transitions of output signal CLK out such that the duty cycle for output signal CLK out does not match the duty cycle of input signal CLK in .

FIG. 2 illustrates a prior art CMOS level shifter circuit 200 . Level shifter circuit 200 includes transistors 201 - 204 . Differential input signals CLK in+ and CLK in− drive the control input terminals of transistor 203 and 204 , respectively. Transistors 201 and 202 are in a cross coupled configuration. When transistor 203 is switched on, the current passing through transistor 203 must overcome the current passing through transistor 201 in order to switch the level shifter output (CLK out− ) to a low level. This delays and changes the timing of the rising and falling transitions of the output signals CLK out+ and CLK out− and skews the duty cycle.

The current passing through transistor 203 must overcome the current passing through the transistor 201 in order to switch the level shifter output (CLKout−) to a low level. A weaker drive for transistor 201 will improve the fall time of signal and degrade the rise time performance at the same time. Changes in supply voltage (Vdd2) may change the drive of transistor 201 (/ 202 ) which may change the output rising(/falling) edges. Inconsistent rising (/falling) edges may degrade duty cycle performance.

Thus, there is a need for improved level shifting. A level shifter circuit in accordance with one embodiment of the present invention solves these and other problems by providing level shifter circuits and methods for maintaining duty cycle.

A circuit according to one embodiment the present invention includes a first buffer, a second buffer, and an output buffer. The first buffer receives an input signal and provides a first buffer output signal on a first output lead. The second buffer receives the input signal and provides a second buffer output signal on a second output lead. The output buffer has a first input lead coupled to the first output lead and AC coupled to the second output lead. The AC coupling communicates timing information from the second buffer to the output buffer. The first buffer applies sufficient voltage to control the first input lead of the output buffer under DC conditions.

Typically, the first buffer has a higher output impedance than the second buffer so that changes in state of the second buffer output signal are communicated to the first input lead of the output buffer.

The output buffer typically comprises a first switch having a control lead coupled to the first input lead of the output buffer and a second switch having a control lead coupled to a second input lead of the output buffer. The first and second switches are coupled in series across a voltage supply. The output buffer has an output lead coupled to a node between the switches.

In one embodiment, the second input lead of the output buffer is coupled to the second output lead. In an alternative embodiment, the circuit comprises a third buffer that receives the input signal and provides a third output signal on a third output lead. The third output lead is coupled to the second input lead of the output buffer.

Typically, the input signal has a set of input voltage rail values. The output buffer provides an output signal having a set of output voltage rail values having a greater voltage swing than the voltage swing of the input voltage rail values. The first buffer ensures that the signal on the input lead of the output buffer achieves a sufficient voltage under DC conditions to properly operate the output buffer. The second buffer ensures the input lead of the output buffer achieves a sufficient voltage under AC conditions to properly operate the output buffer.

A circuit in accordance with another embodiment comprises first, second, and third buffers. The first buffer receives an input signal and provides a first buffer output signal having first voltage rail values. The second buffer receives the input signal and provides a second buffer output signal having second voltage rail values. The third buffer is coupled to receive the first output signal on a first input terminal and coupled to receive the second buffer output signal on a second input terminal and provides a third buffer output signal having third voltage rail values. The third buffer voltage rails have a range greater than both a range of the first voltage rail values and a range of the second voltage rail values. The second buffer output signal provides signal transitions at the first and second input terminals of the third buffer such that the third buffer maintains transition timing relationships of the input signal.

In another embodiment, the transition timing relationship includes a duty cycle of the input signal.

The circuit typically further comprises a capacitor coupled between the first input terminal of the third buffer and the second input terminal of the third buffer. The capacitor AC couples the second buffer output signal to the first input terminal of the third buffer.

In one embodiment, the range of the first voltage rails allows the second voltage rail values of the second buffer output signal to contribute to a change of state of the third buffer output signal according to the transition timing relationship.

In one embodiment, the second buffer has a lower output impedance than the first buffer. Thus, the second output signal changes a state of the first input terminal of the third buffer. The first buffer maintains the state of the signal on the third buffer input terminal when the AC coupling of the second output signal decays.

In another embodiment, the circuit further comprises a fourth buffer. The fourth buffer receives an input signal and provides a fourth buffer output signal having fourth voltage rail values. The third buffer voltage rails have a range greater than a range of the fourth voltage rail values. The output lead of the fourth buffer is coupled to the second input terminal of the output buffer. The output lead of the second buffer is AC coupled to the second input terminal of the output buffer.

The circuit typically further comprises first and second capacitors. The first capacitor AC couples the first input terminal of the third buffer to the output terminal of the second buffer. The second capacitor AC couples second input terminal of the third buffer and the output terminal of the second buffer.

The range of the first voltage rail values typically allows the second voltage rail values of the second buffer output signal to contribute to a change of state of the third buffer output signal according to the transition timing relationship. The range of the fourth voltage rail values typically allows the second voltage rail values of the second buffer output signal to contribute to a change of state of the third buffer output signal according to the transition timing relationship.

The output impedance of the second buffer is typically lower than the output impedance of the first and fourth buffers. This enables the second buffer to change a state of the third buffer output signal due to AC coupling of the second buffer to the output buffer. The first and fourth buffers maintain the state of the third buffer output signal when the AC coupled signal delays.

The third buffer typically includes a high side switch and a low side switch. The high side switch has a first terminal coupled to a first reference voltage, a second terminal coupled to an output terminal, and a control terminal coupled to the first input terminal of the third buffer. The low side switch has a first terminal coupled to the output terminal, a second terminal coupled to a second reference voltage, and a control terminal coupled to the second input terminal of the third buffer. The first and second reference voltages provide the third voltage rail values.

In one embodiment, an integrated circuit or other electrical system comprises the circuit in accordance with the invention. A first portion of the integrated circuit (or other electrical system) uses one set of voltage rail values to communicate a signal, and the circuit in accordance with the invention drives another portion of the integrated circuit (or system) with a signal having second voltage rail values. Alternatively, the circuit in accordance with the invention drives output terminals, pins or cables with the second voltage rail values. The circuit in accordance with the invention may be used in any systems with multiple supply voltages like hard disk drives (HDD), digital video disk players (DVD), high definition televisions (HDTV), and microelectomechanical systems (MEMS).

A method in accordance with another embodiment of the invention comprises receiving an input signal and generating in response thereto first and second buffered output signals. The second buffered output signal communicates timing information from the second buffer output signal to a first input lead of the output buffer via AC coupling. The first buffer output signal is provided to and has sufficient voltage to control the first input lead of the output buffer under DC conditions.

Typically, the first buffer output signal does not interfere with changes in a state of the second output buffer signal that are communicated to the first input lead of the output buffer.

In one embodiment, the method further comprises switching a first switch according to a signal on the first input lead of the output buffer and switching a second switch according to the second output signal. The first switch couples a first reference voltage to an output terminal of the output buffer when the output buffer is in one state. The second switch couples a second reference voltage to the output terminal of the output buffer when the output buffer is in another state.

In another embodiment, the method further comprises buffering the input signal to generate and couple a third output signal to a second input lead of the output buffer. The first switch is switched according to a first signal on the input lead of the output buffer. The second switch is switched according to a second signal on the second input lead of the output buffer. The first switch comprises a first reference voltage to an output terminal of the output buffer. The second switch couples a second reference voltage to the output terminal of the output buffer.

In another embodiment, the input signal has a set of input voltage rail values. The output buffer provides an output signal having a set of output voltage rail values having a greater voltage swing than the voltage swing of the input voltage rail values. The first buffer output signal has a sufficient voltage under DC conditions to properly operate the output buffer. The second buffer output signal has a sufficient voltage under AC conditions to properly operate the output buffer.

FIG. 1 illustrates a first prior art CMOS level shifter circuit.

FIG. 2 illustrates a second prior art CMOS level shifter circuit.

FIG. 3A illustrates a level shifter circuit according to one embodiment of the invention.

FIG. 3B illustrates waveforms associated with the level shifter circuit of FIG. 3A .

FIG. 4A illustrates in detail an example of a level shifter circuit according to the embodiment of FIG. 3A .

FIG. 4B illustrates a current source for use in the embodiment of FIG. 4A .

FIG. 5A illustrates a level shifter circuit according to one embodiment of the invention.

FIG. 5B illustrates waveforms associated with the level shifter circuit of FIG. 5A .

FIG. 6 illustrates in detail an example of a level shifter circuit according to the embodiment of FIG. 3A .

Described herein are level shifter circuits and methods for maintaining duty cycles. In the following description, for purposes of explanation, examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications of the features and concepts described herein.

FIG. 3A illustrates a level shifter circuit 300 according to one embodiment of the invention. Level shifter circuit 300 shifts a high rail V D0 of an input signal D in to a higher rail V D1 of a buffer output signal D out such that the buffer output signal D out maintains transition timing relationships of input signal D in . A transition timing relationship includes timing periods between different rising and falling transitions of a signal. For example, a period of a signal, a pulse width of a signal, and a duty cycle of a signal may all be part of a transition timing relationship.

Level shifter circuit 300 includes buffers 302 - 304 , and a capacitor 306 . Buffers 302 and 303 receive a digital input signal D in at an input terminal 301 . Input signal D in has voltage rails 307 (i.e. V D0 and V E0 ). Buffer 302 provides a buffer output signal B 1 having voltage rails 308 (i.e. V D1 and V E1 ). Buffer 303 provides a buffer output signal B 2 having voltage rails 309 (i.e. V D0 and V E0 ). Buffer 304 receives buffer output signal B 1 on an input terminal T 1 and receives buffer output signal B 2 on an input terminal T 2 . Buffer 304 provides buffer output signal D out on output terminal 305 . Signal D out has voltage rails 310 (i.e. V D1 and V E0 ). Voltage rails 310 typically have a range greater than both a range of voltage rails 308 (i.e. (V D1 −V E0 )>(V D1 −V E1 )) and a range of voltage rails 309 (i.e. (V D1 −V E0 )>(V D0 −V E0 )) such that input signal D in having voltage rails 307 is level shifted to output signal D out having voltage rails 310 . In one exemplary embodiment, V D0 =2.0V, V E0 =0V, V D1 =5V, V E1 =3.0V, and V thresholdT1 (i.e. the threshold voltage of a transistor within buffer 304 coupled to terminal T 1 , not shown in FIG. 3A but shown in FIG. 4 )=4.0V. V E1 is 1V below threshold V thresholdT1 . V thresholdT2 (the threshold voltage of a transistor within buffer 304 coupled to terminal T 2 , not shown in FIG. 3A but shown in FIG. 4 ) is between V E0 and V D0 (e.g. 1.0 V, for example).

In a 0.18 um process, the threshold voltage for a low voltage transistor (1.8V) is approximately 0.5V and the threshold voltage for the high voltage transistor (3.3V) is approximately 0.6V. In different processes the threshold voltage will be different. For example, in a 0.35 um process, the threshold voltage is normally about 0.7 for the high voltage transistor (5V). In one example design, V D0 =1.8V, V E0 =0V, V D1 =3.3V, and V E1 =1.5V.

When input signal D in is at high voltage V D0 (in this example, 2.0V), buffer output signal B 1 is at low voltage V E1 (3V), buffer output signal B 2 is at low voltage V E0 (0V), and buffer output signal D out is at high voltage V D1 (5V). When input signal D in changes state to low voltage V E0 (i.e. 0V), buffer output signal B 2 goes to high voltage V D0 (2.0V) at approximately the same rate as the transition of input signal D in . The output lead of buffer 303 is AC coupled to terminal T 1 via capacitor 306 . Since the output impedance of buffer 302 under these circumstances exceeds the output impedance of buffer 303 , the transition on lead B 2 caused by buffer 303 changes the voltage at terminal T 1 from 3V to 5V and therefore the voltage at terminal T 1 passes threshold V thresholdT1 of 4V. Buffer output signal B 2 at terminal T 2 and the AC coupled buffer output signal B 2 at terminal T 1 therefore change the state of buffer output signal D out . The transition timing relationships of further transitions of states of buffer output signal D out match the transition timing relationships of the corresponding input signal D in . (As used in this patent, “matching” does not necessarily require an exact matching). AC coupled buffer output signal B 2 provides transitions of states such that buffer output signal D out maintains transition timing relationships of input signal D in .

The transition timing relationships include the duty cycle of input signal D in and the duty cycle of buffer output signal D out . Also, the relationship of rising transitions and falling transitions of buffer output signal D out matches a relationship of corresponding rising and falling transitions of input signal D in .

AC coupled buffer output signal B 2 drives an output impedance of buffer 302 . Buffer 302 preferably has an output impedance that does not significantly alter the timing transition relationships of the rising AC coupled buffer output signal B 2 . If the output impedance of buffer 302 excessively loads AC coupled buffer rising output signal B 2 , the signal at input terminal T 1 may be delayed and the transfer of transition timing may be degraded.

Because output signal B 2 is AC coupled to terminal T 1 , it cannot hold the voltage level on terminal T 1 high indefinitely. In order to maintain the state of buffer output signal D out , output signal B 1 preferably rises quickly enough to maintain the signal at input terminal T 1 above threshold V thresholdT1 after the effect of the transition of signal B 2 on lead T 1 recedes.

FIG. 3B illustrates waveforms associated with the input signal D in and buffer output signal D out . As seen in FIG. 3B , input signal D in has high rail voltage V D0 and a low rail voltage V E0 . Rising transition to rising transition of input signal D in defines a period P 1 . Input signal D in includes a pulse width PW 1 . Range R 1 is the voltage difference traveled by input signal D in .

There is a delay D 1 between the input signal D in and buffer output signal D out due to propagation delays associated with the circuitry of level shifter circuit 300 . Buffer output signal D out has high rail voltage V D1 and low rail voltage V E0 . Rising transition to rising transition of buffer output signal D out defines a period P 2 . Buffer output signal D out includes a pulse width PW 2 . Range R 2 is the voltage difference traveled by buffer output signal D out .

Rail voltage V D0 of input signal D in is level shifted to rail voltage V D1 of buffer output signal V out . Period P 1 and pulse width PW 1 of input signal D in match period P 2 and pulse width PW 2 of buffer output signal D out . The duty cycle of input signal D in , therefore matches the duty cycle of buffer output signal D out . FIG. 3B shows that transition timing relationships of buffer output signal D out matches the transition timing relationships of input signal D in . (As mentioned above, matching as used herein is not necessarily an exact matching.)

FIG. 4A illustrates in detail an example of an embodiment in accordance with FIG. 3A . Buffer 302 of FIG. 4 drives buffer output signal B 1 . Buffer 302 of FIG. 4 includes a resistor 411 , a current source 412 , and a transistor 413 . One terminal of resistor 411 is coupled to reference voltage V D1 and the other terminal of resistor 411 is coupled to input terminal T 1 . Input terminal T 1 is also coupled to one terminal of capacitor 306 and one terminal of current source 412 . The other terminal of current source 412 is coupled to one terminal of transistor 412 . The other terminal of transistor 412 is coupled to reference voltage V E0 . A control terminal of transistor 413 is coupled to input terminal 301 .

Voltage rails 308 of buffer output signal B 1 cooperate with AC coupled buffer output signal B 2 to allow AC coupled signal B 2 to cross the threshold of transistor 414 to turn transistor 414 on and off. In one example, V D0 =V E1 =3.0V, V E0 =0V, V D1 =5V, and V thresholdT1 =4.0V. V thresholdT1 is the threshold voltage of transistor 414 . V E1 suffices to keep transistor 414 on but also allows a rising transition of AC coupled buffer output signal B 2 to turn off transistor 414 in response to a falling transition of signal D in . In one example of this embodiment,

V D1 −V E1 =( I 1 *R 1 )= V D0 −V E0 =2.0V

V D1 =5.0V

V E1 =V D1 −2=5.0V

V D1 −V E1 =5V−3V=2V.

As can be seen from the foregoing, current I 1 and resistance R 1 are selected to establish voltage V E1 at a desired value (in this example, 3.0 V). Assuming the signal D in is running at 50 MHz and capacitor 306 is represented as C 306 , the following equation follows.

R 1 * C 306 = 1 2 ⁢ π ⁢ ⁢ f = 1 2 * 3.14 * 50 ⁢ MHz = 3 ⁢ ns

The capacitor C 306 may occupy less area, and a value of 0.6 pF may be chosen for this case. From the equation shown above, minimum R 1 follows as shown below.

R 1 ⁡ ( min ) = 3 ⁢ ns 0.6 ⁢ pF = 5 ⁢ kohms

To achieve a safe margin, R 1 may be chosen as follows.

R 1 =10 *R min=506 kohm

Therefore, I 1 =(V D1 −V E1 )/R 1 =40 uA. For a higher frequency signal D in , smaller values of capacitance C 306 may be used.

FIG. 4B illustrates a current source for use in the embodiment of FIG. 4A . Current source 302 includes a reference current source 412 a and an NMOS current mirror comprising transistors 412 b - 412 d. Reference current source 412 a is coupled to transistor 412 b which is coupled as a diode. Reference current source 412 a is also coupled to a control terminal of transistor 412 d such that transistor 412 d delivers current I 1 to resistor R 1 ( 412 ) when transistor 413 is turned on. The current I 1 generates a voltage as described above at terminal T 1 .

Transistor 412 c is coupled to bias transistor 412 b. A control terminal of transistor 412 c receives voltage V D0 . When input signal Din turns on transistor 413 by providing voltage V D0 to a control terminal of transistor 413 , the current mirror provides current I 1 . In this embodiment transistor 412 b matches transistor 412 d and transistor 412 c matches transistor 413 . In this case I 1 =Iref. However changing the ratio of the dimensions of the transistors by one skilled in the art will result in currents that are a fraction or a multiple of reference current Iref. A PMOS current mirror may be implemented in a similar manner to generate I 2 in FIG. 6 .

FIG. 5A illustrates a level shifter circuit 500 according to another embodiment of the invention for shifting both the high voltage rail V D0 and the low voltage rail V E0 to voltages V D3 and V E3 , respectively. Level shifter circuit 500 includes buffers 501 - 504 and capacitors 507 - 508 . Level shifter circuit 500 is similar to level shifter circuit 300 of FIG. 3 . Buffers 501 - 503 receive input signal D in . Buffer 502 provides a buffer output signal B 2 . Capacitor 507 AC couples signal B 2 to input terminal T 1 of buffer 504 . Capacitor 508 AC couples signal B 2 to input terminal T 2 of buffer 504 . The first and second AC coupled signals contribute to the transitioning of buffer output signal D out . Buffer 502 provides a buffer output signal B 1 to maintain the state of transistor 514 when the effect to AC coupled signal B 2 decays at input terminal T 1 . In a similar manner, buffer 503 provides a buffer output signal B 3 to maintain the state of transistor 515 when the effect of AC coupled buffer output signal B 2 decays at input terminal T 2 . Maintaining the state of transistors 514 and 515 maintains the state of buffer output signal D out .

Level shifter circuit 500 shifts high rail voltage V D0 of input signal D in to a higher rail voltage V D3 of a buffer output signal D out and shifts low rail voltage V E0 of input signal D in to a lower rail voltage V E3 of buffer output signal D out . The shifting of the high rail voltage V D0 and low rail voltage V E0 is accomplished while buffer output signal D out maintains transitioning timing relationships of input signal D in .

FIG. 5B illustrates exemplary waveforms of input signal D in and output signal D out . Signals D in and D out are illustrated as square waves, but in other embodiments they can have any duty cycle. Also these signals do not need to be repetitive waveforms. For example, the waveforms may be a stream of digital data.

Input signal D in and output signal D out include matching transition timing relationships. Input signal D in includes a low level V E0 , a high level V D0 , a period P 3 , a pulse width PW 3 , and a voltage range R 3 . Buffer output D out includes a low level V E3 , a high level voltage V D3 , a period P 4 , a pulse width PW 4 , and a voltage range R 4 . Period P 3 and pulse width PW 3 match period P 4 and pulse width P 4 , respectively. Also, the duty cycle of signal D in matches the duty cycle of signal D out .

Although buffer output signal D out is delayed relative to input signal D in , the transition timing relationships of signal D out match the transition timing relationships signal D in . For example, period P 4 matches period P 3 and pulse width PW 4 matches pulse width PW 3 . Input signal D in has been level shifted to voltage range R 4 from voltage range R 3 . Voltage level V E3 is less than voltage level V E0 , voltage V D3 is greater than voltage V D0 and range R 4 exceeds range R 3 .

FIG. 6 illustrates in detail an embodiment in accordance with FIG. 5A , discussed above. As can be seen, buffer 501 comprises the same components, and operates in a manner similar to, buffer 302 of FIG. 4 . Buffer 502 comprises the same components, and operates in a manner similar to buffer 303 . Buffer 503 is similar to buffer 501 , except that it includes a P channel transistor 619 instead of an N channel transistor 616 . Also, resistor 621 is coupled to low reference voltage V E3 instead of high voltage lead V D3 . Below are example values for level shifter circuit 500 of FIG. 6 . Signal Din has a frequency of 50 MHz for this example.

R 1 =R 2 =50 Kohm, C 507 =C 508 =0.6 pf, I 1 =I 2 =40 uA.

V D0 =2V, V E0 =0V, V D3 =3V, V E3 =−3V

The level shifter circuits described above and other equivalent embodiments may be implemented using CMOS technology or other IC technology suitable for implementing embodiments of the present invention. For example, a high speed process such as processes utilizing a GaAs process can be used to implement embodiments of this invention as well. Alternatively, other semiconductor materials such as Si can be used. The level shifter circuits and methods may be integrated into a system fabricated as an IC. In addition, other components may be added to the circuit without departing from the invention.

Although the buffers discussed above perform inverting functions, in other embodiments, the buffers can perform logic functions (e.g. AND, NAND, NOR, OR) and non-inverting buffering as well. Signals D in and D out can be clock, data, instructions or other types of signals.

In one embodiment, instead of just shifting high voltage V D0 to V D1 as shown in FIG. 3 , in another embodiment, only low voltage V E0 is shifted to voltage V E1 (e.g. using circuitry similar to buffer 503 ). Also, in one embodiment, buffers 303 and 502 need not operate off of voltages V E0 and V D0 . Further, buffer 304 can use a voltage other than voltage V E0 . For example, buffer 304 can use a voltage slightly higher than voltage V E0 . Accordingly, all such modifications come within the invention.