Buffer circuit of semiconductor integrated apparatus

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2008-0023028, filed on Mar. 12, 2008, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

1. Technical Field

The embodiments described herein relate to a semiconductor integrated apparatus, and more particularly, to a buffer circuit of a semiconductor integrated apparatus.

2. Related Art

In general, a buffer circuit of a semiconductor integrated apparatus is provided to supply a stabilized voltage to an internal circuit. Here, the buffer circuit is configured to receive a reference voltage and generate an internal voltage having the same level as the reference voltage.

FIG. 1 is a schematic circuit diagram of a conventional buffer circuit of a semiconductor integrated apparatus. In FIG. 1 , a buffer circuit 10 has a current mirror structure receiving an input voltage V_in from an exterior of the buffer circuit 10 and generating a stable output voltage V_out. The buffer circuit 10 includes first to tenth transistors P 1 to P 5 and N 1 through N 5 . The first and second transistors P 1 and P 2 receive a first bias voltage BIAS 1 through gate terminals and a supply voltage ‘VDD’ through source terminals, and output a constant voltage through drain terminals. The third and fourth transistors N 1 and N 2 have gate terminals connected to a common node, and are connected to the drains of the first and second transistors P 1 and P 2 , and receive the constant voltage. Here, the gate and drain terminals of the third transistor N 1 are connected with each other, and therefore, the gate and drain terminals of the third transistor N 1 and the gate terminal of the fourth transistor N 2 receive the same potential level.

The fifth and sixth transistors P 3 and P 4 have source terminals to which the source terminals of the third and fourth transistors N 1 and N 2 are connected, and gate terminals connected to a common node. Here, the gate and drain terminals of the fifth transistor P 3 are connected with each other. The seventh and eighth transistors N 3 and N 4 receive a second bias voltage BIAS 2 through gate terminals, and have drain terminals connected to the drain terminals of the fifth and sixth transistors P 3 and P 4 and source terminal connected to a ground voltage ‘VSS’.

The input voltage V_in is supplied to a node to which the third transistor N 1 and the fifth transistor P 3 are connected, and an output node A, from which the output voltage V_out is output, is connected to a node to which the fourth transistor N 2 and the sixth transistor P 4 are connected. In addition, a pull-up signal ‘pu’ is output from a node to which the second transistor P 2 and the fourth transistor N 2 are connected, and a pull-down signal ‘pd’ is output from a node to which the sixth transistor P 4 and the eighth transistor N 4 are connected.

The ninth transistor P 5 has a gate terminal through which the pull-up signal ‘pu’ is input and a source terminal to which the supply voltage ‘VDD’ is supplied. The tenth transistor N 5 has a gate terminal through which the pull-down signal ‘pd’ is input, a drain terminal to which the drain terminal of the ninth transistor P 5 is connected, and a source terminal which is connected to the ground voltage ‘VSS’. At this time, the output node A is connected to a node to which the ninth transistor P 5 and the tenth transistor N 5 are connected.

In the buffer circuit 10 , if the level of the input voltage V_in increases, then the potential level of the pull-up signal ‘pu’ decreases, and the turn-ON of the ninth transistor P 5 quickly occurs. Accordingly, the level of the output voltage V_out increases. Conversely, if the level of the input voltage V_in decreases, then the potential level of the pull-down signal ‘pd’ increases, and the turn-ON of the tenth transistor N 5 quickly occurs. Accordingly, the level of the output voltage V_out decreases.

However, buffer circuit 10 suffers from defects in that, since it is composed of the transistors, as described above, it is influenced by process variations.

A normal buffer circuit must generate the output voltage V_out having the same level as the input voltage V_in. Accordingly, by measuring the level of the output voltage V_out in response to the input voltage V_in, as can be readily seen from FIG. 2 , the level of the input voltage V_in and the level of the output voltage V_out do not correspond to each other. This non-correspondence in the levels of the input and output voltages V_in and V_out results from changes in the sizes of the ninth and tenth transistors P 5 and N 5 that function to actually perform pull-up and pull-down operations in the buffer circuit 10 . Here, the sizes of transistors are determined by photolithographic processes. Accordingly, as semiconductor integrated apparatuses trend toward fine formation, errors are likely to occur while conducting the photolithographic processes. Thus, the sizes of transistors may deviate from a predetermined range.

For example, if the tenth transistor N 5 is formed large relative to the other transistors due to the process variations, as can be readily seen from the graph of FIG. 2 , the level of the output voltage V_out decreases compared to the level of the input voltage V_in. On the contrary, if the ninth transistor P 5 is formed large relative to the other transistors, then the level of the output voltage V_out increases compared to the level of the input voltage V_in.

Thus, in the buffer circuit 10 , it is difficult to generate precisely an internal voltage.

A buffer circuit of a semiconductor integrated apparatus capable of generating an output voltage having the same level as an input voltage without being influenced by a process variation is described herein.

In one aspect, a buffer circuit of a semiconductor integrated apparatus includes a control block configured to output a result of comparing an input voltage level and an output voltage level as a control signal, and a buffering bock configured to generate an output voltage having substantially the same level as an input voltage in response to the control signal.

In another aspect, a buffer circuit of a semiconductor integrated apparatus includes a pull-up unit configured to perform a pull-up operation depending upon a potential level of a pull-up signal and increase a level of an output voltage, a pull-down unit configured to perform a pull-down operation depending upon a potential level of a pull-down signal and decrease the level of the output voltage, and a control block configured to generate a control signal for selectively driving the pull-up unit and the pull-down unit.

In another aspect, a semiconductor integrated circuit includes a buffer circuit configured to compare an input voltage level and an output voltage level and output a control signal based upon the comparison, and to generate an output voltage having substantially the same level as an input voltage in response to the control signal.

These and other features, aspects, and embodiments are described below in the section “Detailed Description.”

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a schematic circuit diagram of a conventional buffer circuit of a semiconductor integrated apparatus;

FIG. 2 are graphs representing input signal levels and output signal levels of the buffer circuit of FIG. 1 ;

FIG. 3 is a schematic block diagram of an exemplary buffer circuit of a semiconductor integrated apparatus according to one embodiment;

FIG. 4 is a schematic circuit diagram of an exemplary buffering block capable of being implemented in the apparatus of FIG. 3 according to one embodiment;

FIG. 5 is a schematic circuit diagram of an exemplary control block capable of being implemented in the block of FIG. 3 according to one embodiment; and

FIG. 6 are graphs representing exemplary input signal levels and output signal levels of the buffer circuit of FIG. 3 according to one embodiment.

FIG. 3 is a schematic block diagram of an exemplary buffer circuit of a semiconductor integrated apparatus according to one embodiment. In FIG. 3 , a buffer circuit 500 can include a buffering block 100 and a control block 200 .

The buffering block 100 can be configured to output an output voltage V_out having substantially the same level as an input voltage V_in in response to a control signal ‘ctrl’ transmitted from the control block 200 .

The control block 200 can compare the levels of the input voltage V_in and the output voltage V_out, and can output the control signal ‘ctrl’ indicating a comparison result.

FIG. 4 is a schematic circuit diagram of an exemplary buffering block capable of being implemented in the apparatus of FIG. 3 according to one embodiment. In FIG. 4 , the buffering block 100 can include a signal generation section 110 and a voltage output section 120 as shown in FIG. 4 .

The signal generation section 110 can be configured to generate a pull-up signal ‘pu’ and a pull-down signal ‘pd’ depending upon the level of the input voltage V_in. For example, the signal generation section 110 can include first to eighth transistors N 11 to N 14 and P 11 to P 14 . The first transistor N 11 can receive the input voltage V_in through a source terminal, and gate and drain terminals of the first transistor N 11 can be connected with each other. The second transistor N 12 can have a gate terminal to which the gate terminal of the first transistor N 11 can be connected and a source terminal receiving the output voltage V_out.

The third transistor P 11 can have a gate terminal receiving a first bias voltage BIAS 1 , a source terminal receiving a supply voltage VDD, and a drain terminal to which the drain terminal of the first transistor N 11 can be connected. The fourth transistor P 12 can have a gate terminal receiving the first bias voltage BIAS 1 , a source terminal receiving the supply voltage VDD, and a drain terminal to which the drain terminal of the second transistor N 12 can be connected.

The fifth transistor P 13 can have a gate terminal and a drain terminal which are connected with each other and a source terminal to which the source terminal of the first transistor N 11 can be connected. The sixth transistor P 14 can have a gate terminal to which the gate terminal of the fifth transistor P 13 can be connected, and a source terminal to which the source terminal of the second transistor N 12 can be connected.

The seventh transistor N 13 can have a gate terminal receiving a second bias voltage BIAS 2 , a drain terminal to which the drain terminal of the fifth transistor P 13 can be connected, and a source terminal to which the terminal of a ground voltage VSS can be connected. The eighth transistor N 14 can have a gate terminal receiving the second bias voltage BIAS 2 , a drain terminal to which the drain terminal of the sixth transistor P 14 can be connected, and a source terminal to which the terminal of the ground voltage VSS can be connected.

Accordingly, the pull-up signal ‘pu’ can be output from a node to which the second transistor N 12 and the fourth transistor P 12 are connected, and the pull-down signal ‘pd’ can be output from a node to which the sixth transistor P 14 and the eighth transistor N 14 are connected.

In addition, the pull-up signal ‘pu’ and the pull-down signal ‘pd’ can be generated by comparing the levels of the input voltage V_in and the output voltage V_out in the signal generation section 110 . Here, setting can be made such that, when the level of the input voltage V_in is higher than the level of the output voltage V_out, the potential level of the pull-up signal ‘pd’ can decrease. Conversely, when the level of the input voltage V_in is lower than the level of the output voltage V_out, the potential level of the pull-down signal ‘pd’ can increase.

In FIG. 3 , the voltage output section 120 can perform pull-up and pull-down operations depending upon the levels of the pull-up signal ‘pu’ and the pull-down signal ‘pd’, and can adjust the level of the output voltage V_out. Here, the pull-up operation and the pull-down operation can be controlled depending upon whether the control signal ‘ctrl’ is enabled.

In FIG. 3 , the voltage output section 120 can include a pull-up unit 121 and a pull-down unit 122 . The pull-up unit 121 can be configured such that, when the control signal ‘ctrl’ is enabled, the pull-up unit 121 can perform the pull-up operation depending upon the potential level of the pull-up signal ‘pu’ and increases the level of the output voltage V_out. For example, the pull-up unit 121 can include a pull-up driver 121 - 1 and a first switching part 121 - 2 .

The pull-up driver 121 - 1 can switch the supply voltage VDD depending upon the potential level of the pull-up signal ‘pu’. For example, the pull-up driver 121 - 1 can include a ninth transistor P 15 having a gate terminal receiving the pull-up signal ‘pu’ and a source terminal receiving the supply voltage VDD.

When the control signal ‘ctrl’ is enabled to a low level, the first switching part 121 - 2 can provide the output of the pull-up driver 121 - 1 as the output voltage V_out. For example, the first switching part 121 - 2 can include a tenth transistor P 16 having a gate terminal receiving the control signal ‘ctrl’, a drain terminal receiving the output of the pull-up driver 121 - 1 , and a source terminal to which the terminal of the output voltage V_out can be connected.

The pull-down unit 122 can include a second switching part 122 - 1 and a pull-down driver 122 - 2 . The second switching part 122 - 1 can be configured to transmit the output voltage V_out to the pull-down driver 122 - 2 when the control signal ‘ctrl’ is disabled to a high level. For example, the second switching part 122 - 1 can include an eleventh transistor N 15 having a gate terminal receiving the control signal ‘ctrl’, a source terminal receiving the output voltage V_out, and a drain terminal to which the pull-down driver 122 - 2 can be connected.

The pull-down driver 122 - 2 can guide the output of the second switching part 122 - 1 to the terminal of the ground voltage VSS in response to the potential level of the pull-down signal ‘pd’. For example, the pull-down driver 122 - 2 can include a twelfth transistor N 16 having a gate terminal receiving the pull-down signal ‘pd’, a drain terminal to which the output of the second switching part 122 - 1 can be supplied, and a source terminal to which the terminal of the ground voltage VSS can be connected.

FIG. 5 is a schematic circuit diagram of an exemplary control block capable of being implemented in the block of FIG. 3 according to one embodiment. In FIG. 5 , the control block 200 can be configured to compare the levels of the input voltage V_in and the output voltage V_out and to generate the control signal ‘ctrl’. For example, the control block 200 can be configured in the shape of a current mirror-type comparator.

The control block 200 having the shape of a current mirror-type comparator can include thirteenth to seventeenth transistors N 21 to N 23 , P 21 , and P 22 . The thirteenth transistor N 21 can have a gate terminal receiving the output voltage V_out, and the fourteenth transistor N 22 can have a gate terminal receiving the input voltage V_in. In addition, the fifteenth transistor N 23 can have a gate terminal receiving the supply voltage VDD, a drain terminal to which a node having the thirteenth transistor N 21 and the fourteenth transistor N 22 connected thereto can be connected, and a source terminal to which the terminal of the ground voltage VSS can be connected. The sixteenth transistor P 21 can have a gate terminal and a drain terminal to which the drain of the thirteenth transistor N 21 can be connected, and a source terminal receiving the supply voltage VDD. The seventeenth transistor P 22 can have a gate terminal to which the gate terminal of the sixteenth transistor P 21 can be connected, a source terminal receiving the supply voltage VDD, and a drain terminal to which the drain of the fourteenth transistor N 22 can be connected.

In FIG. 5 , the control block 200 can further include a driver 210 that can buffer a signal output from a node to which the fourteenth transistor N 22 and the seventeenth transistor P 22 are connected. For example, the driver 210 can include first and second inverters IV 21 and IV 22 connected in series.

An exemplary operation of the buffer circuit of a semiconductor integrated apparatus will be described with reference to FIGS. 3-5 .

When the level of the input voltage V_in is higher than the level of the output voltage V_out, the control block 200 can output the control signal ‘ctrl’ having a low level. Then, the control signal ‘ctrl’ having the low level can be input to the buffering block 100 . Since the first switching part 121 - 1 of the pull-up unit 121 is turned ON, the pull-up unit 121 can output a pulled-up voltage as the output voltage V_out. Here, since the second switching part 122 - 1 of the pull-down unit 122 is turned OFF, the pull-down unit 122 does not perform the pull-down operation.

In addition, when the level of the output voltage V_out is higher than the level of the input voltage V_in, the control block 200 can output the control signal ‘ctrl’ having a high level. Accordingly, the control signal ‘ctrl’ having the high level can be input to the buffering block 100 . Since the second switching part 122 - 1 of the pull-down unit 122 is turned ON, the pull-down unit 122 can pull down the output voltage V_out. Here, since the first switching part 121 - 1 of the pull-up unit 121 is turned OFF, the pull-up unit 121 does not perform the pull-up operation.

If the pull-up driver for performing the pull-up operation or the pull-down driver for performing the pull-down operation has a size different from that originally designed, then the level of the output voltage V_out changes. However, since the pull-up operation and the pull-down operation are selectively performed in response to the control signal ‘ctrl’ that is generated by comparing the levels of the input voltage V_in and the output voltage V_out, the level of the output voltage V_out is not substantially influenced by the sizes of the pull-up driver 121 - 1 and the pull-down driver 122 - 2 .

FIG. 6 are graphs representing exemplary input signal levels and output signal levels of the buffer circuit of FIG. 3 according to one embodiment. In FIG. 6 , the levels of the input voltage V_in and the output voltage V_out are buffered, wherein even when the sizes of the pull-up driver 121 - 1 and the pull-down driver 122 - 2 change, the levels of the input voltage V_in and the output voltage V_out are substantially the same.

Accordingly, the buffer circuit of a semiconductor integrated apparatus can control pull-up and pull-down operations, and can generate an output voltage having substantially the same level as an input voltage irrespective of process variations, whereby voltage stabilization of a semiconductor memory apparatus can be accomplished. In addition, power consumption can be reduced.

While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the device and methods described herein should not be limited based on the described embodiments. Rather, the device and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.