Semiconductor integrated circuit

The present application claims the benefit under 35 U.S.C. 119(a) to Korean Application No. 10-2008-0089555, filed on Sep. 11, 2008, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if set forth in full.

1. Technical Field

The embodiments described herein relate to a semiconductor integrated circuit (IC), and more particularly, to a clock control apparatus of a semiconductor IC.

2. Related Art

In general, a semiconductor IC includes a clock generating circuit, such as a Delay Locked Loop (DLL) circuit and a Phase Locked Loop (PLL) circuit, to generate an internal clock signal having a phase faster than an external clock signal by a predetermined time. Accordingly, the internal clock signal generated in this way is used to synchronize timing for buffering data during data input/output operations.

Since a frequency of the internal clock signal determines an operational speed of a semiconductor IC, a clock generating circuit is provided to generate an internal clock signal having a higher frequency in order to improve the operational speed. Accordingly, semiconductor ICs include a method for oscillating a clock signal having a relatively high frequency by using the PLL circuit. In addition, the semiconductor ICs include a method of dividing a clock signal into a plurality of individual frequencies by using a mufti-phase DLL circuit.

Currently, semiconductor ICs use a PLL circuit for oscillating a PLL clock signal by using a reference clock signal input through a clock signal input buffer, and then transmitting the buffered clock signal input to a data input/output circuit along a relatively long conductive transmission line to generate an internal clock signal by using a DLL circuit. Here, the DLL circuit is implemented as a multi-phase DLL circuit, and the internal clock signal is implemented as a set of clock signals each having multiple phases. However, using both a PLL circuit and a DLL circuit in one semiconductor IC degrades internal area efficiency of a semiconductor IC, thereby preventing high integration of the semiconductor IC. In addition, since both the PLL and DLL circuits are provided together, consumption power greatly increases. Thus, the semiconductor IC fails to maintain a low power consumption, thereby reducing power efficiency of the semiconductor IC.

A semiconductor IC capable of improving area efficiency and power efficiency is described herein.

In one aspect, a semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.

In another aspect, a semiconductor integrated circuit comprises a Phase Locked Loop (PLL) circuit configured to generate a PLL clock signal in response to a frequency of a reference clock signal, a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and a transmission line configured to transmit the PLL clock signal from the PLL circuit to the voltage controlled oscillator, the transmission line comprising a length that is larger than a sum of a pathway of the reference clock signal from the clock input buffer to the PLL circuit and a transmission length of the output clock signal from the voltage controlled oscillator to the plurality of data input/output buffers.

In another aspect, a semiconductor integrated circuit comprises a clock input buffer configured to buffer an external clock signal and to generate a reference clock signal, a clock generating circuit configured to generate an internal clock signal in response to a frequency of the reference clock signal, a voltage controlled oscillator configured to oscillate and output a plurality of output clock signals having multiple phases in response to the internal clock signal, and a plurality of data input/output buffers configured to receive the plurality of output clock signals to perform buffering operations on input/output data.

These and other features, aspects, and embodiments are described in detailed below in the section “Detailed Description.”

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a schematic block diagram of an exemplary semiconductor IC according to one embodiment;

FIG. 2 is a schematic circuit diagram of an exemplary voltage controlled oscillator capable of being implemented in the semiconductor IC of FIG. 1 according to one embodiment; and

FIG. 3 is a schematic circuit diagram of an exemplary 4-input delay cell capable of being implemented in the oscillator of FIG. 2 according to one embodiment.

FIG. 1 is a schematic block diagram of an exemplary semiconductor IC 1 according to one embodiment. In FIG. 1 , the semiconductor IC 1 can be configured to include a clock input buffer 10 , a PLL circuit 20 , a transmission line 30 , a voltage controlled oscillator 40 , and a plurality of data input/output buffers 50 . Although not specifically shown, the semiconductor IC 1 can be implemented on a substrate as individual components or integrated as a single circuit configuration on and/or in a substrate.

The clock input buffer 10 can buffer an external clock signal ‘clk_ext’ to generate a reference clock signal ‘clk_ref’. The PLL circuit 20 can generate a PLL clock signal ‘clk_pll’ in response to a frequency of the reference clock signal ‘clk_ref’. The transmission line 30 can transmit the PLL clock signal ‘clk_pll’. The voltage controlled oscillator 40 can oscillate an output clock signal ‘clk_out’ in response to the PLL clock signal ‘clk_pll’ transmitted along the transmission line 30 . The plurality of data input/output buffers 50 can receive the output clock signal ‘clk_out’ and perform buffering operations on input/output data.

For example, the PLL circuit 20 can generate a control voltage Vctrl in response to a frequency of the reference clock signal ‘clk_ref’. In addition, the PLL circuit 20 can generate the PLL clock signal ‘clk_pll’ having a frequency that corresponds to a level of the control voltage Vctrl. In addition, the control voltage Vctrl can be provided to the voltage controlled oscillator 40 , and the voltage controlled oscillator 40 can match a frequency of the output clock signal ‘clk_out’ with the level of the control voltage Vctrl. Accordingly, both the output clock signal ‘clk_out’ and the PLL clock signal ‘clk_pll’ can have substantially the same frequency.

In FIG. 1 , the output clock signal ‘clk_out’ can be implemented as a plurality of clock signals, each having different multiple phases. For example, the output clock signal ‘clk_out’ can be a combination of a plurality of clock signals generated by dividing a phase of the PLL clock signal ‘clk_pll’. Accordingly, the plurality of clock signals can be respectively transmitted to the data input/output buffers 50 , which can be allocated in advance.

In FIG. 1 , although not drawn to specific scale, a length of the transmission line 30 can be larger than a sum of the transmission length of the reference clock signal ‘clk_ref’ from the clock input buffer 10 to the PLL circuit 20 . Moreover, a length of the transmission line 30 can be larger than a pathway of the output clock signal ‘clk_out’ from the voltage controlled oscillator 40 to the data input/output buffers 50 . For example, the PLL circuit 20 is located near the clock input buffer 10 , which receives the external clock signal ‘clk_ext’, and the voltage controlled oscillator 40 , which is located near the data input/output buffers 50 . The voltage controlled oscillator 40 can be used, e.g., instead of a DLL circuit as in conventional circuits, to overcome any adverse noise effects by a semiconductor IC due to the clock signals, which have multiple phases, being transmitted along a relatively long transmission line 30 . Here, the voltage controlled oscillator 40 functions in response to the PLL clock signal ‘clk_pll’ to generate the output clock signals ‘clk_out’, each having multiple phases, which can have substantially the same frequency with the PLL clock signal ‘clk_pll’. Accordingly, the voltage controlled oscillator 40 can contribute to reducing occupational area of the semiconductor IC and reduce consumption current.

FIG. 2 is a schematic circuit diagram of an exemplary voltage controlled oscillator 40 capable of being implemented in the semiconductor IC 1 of FIG. 1 according to one embodiment. In FIG. 2 , the voltage controlled oscillator 40 can receive the PLL clock signal ‘clk_pll’, as clock signal pairs, and can produce the output clock signals ‘clk_out’, as clock pairs having four phases, for example. Alternatively, the output clock signals ‘clk_out’ can be clock pairs having more or less than four phases.

For example, as shown in FIG. 2 , the voltage controlled oscillator 40 can include an oscillation unit 410 and a buffering unit 420 . The oscillation unit 410 can generate oscillation clock signal pair ‘clk_osc<1:4>’ and ‘/clk_osc<1:4>’ in response to the PLL clock signal pair ‘clk_pll’ and ‘/clk_pll’ and the control voltage Vctrl. For example, the oscillation unit 410 can include a 4-input delay cell 4 DC and first to third 2-input delay cells 2 DC 1 to 2 DC 3 . Alternatively, the oscillation unit 410 can include more or less than a 4-input delay cell and more or less than 2-input delay cells.

The 4-input delay cell 4 DC can buffer the PLL clock signal pair ‘clk_pll’ and ‘/clk_pll’ and a fourth oscillation clock signal pair ‘clk_osc 4 ’ and ‘/clk_osc 4 ’ in response to the control voltage Vctrl to generate a first oscillation clock signal pair ‘clk_osc 1 ’ and ‘/clk_osc 1 ’. In addition, the first 2-input delay cell 2 DC 1 can buffer the first oscillation clock signal pair ‘clk_osc 1 ’ and ‘/clk_osc 1 ’ to generate a second oscillation clock signal pair ‘clk_osc 2 ’ and ‘/clk_osc 2 ’. Similarly, the second 2-input delay cell 2 DC 2 can buffer the second oscillation clock signal pair ‘clk_osc 2 ’ and ‘/clk_osc 2 ’ to generate a third oscillation clock signal pair ‘clk_osc 3 ’ and ‘/clk_osc 3 ’. Likewise, the third 2-input delay cell 2 DC 3 can buffer the third oscillation clock signal pair ‘clk_osc 3 ’ and ‘/clk_osc 3 ’ to generate a fourth oscillation clock signal pair ‘clk_osc 4 ’ and ‘/clk_osc 4 ’. Accordingly, if n-input delay cells are used, wherein “n” can be greater than one, then corresponding oscillation clock signal pairs can be buffered to generate corresponding ones of oscillation clock signal pairs.

In FIG. 2 , the buffering unit 420 can buffer the four oscillation clock signal pairs ‘clk_osc<1:4>’ and ‘/clk_osc<1:4>’ to output the output clock signal pairs ‘clk_out’ and ‘/clk_out’ having four phases, respectively. For example, the buffering unit 420 can include first to fourth clock buffers BUF 1 to BUF 4 . Alternatively, the buffering unit 420 can include more or less than four clock buffers.

The first clock buffer BUF 1 can buffer the first oscillation clock signal pair ‘clk_osc 1 ’ and ‘/clk_osc 1 ’ to output a first output clock signal pair ‘clk_out 1 ’ and ‘/clk_out 1 ’. Similarly, the second clock buffer BUF 2 can buffer the second oscillation clock signal pair ‘clk_osc 2 ’ and ‘/clk_osc 2 ’ to output a second output clock signal pair ‘clk_out 2 ’ and ‘/clk_out 2 ’. The third clock buffer BUF 3 can buffer the third oscillation clock signal pair ‘clk_osc 3 ’ and ‘/clk_osc 3 ’ to output a third output clock signal pair ‘clk_out 3 ’ and ‘/clk_out 3 ’. The fourth clock buffer BUF 4 can buffer the fourth oscillation clock signal pair ‘clk_osc 4 ’ and ‘/clk_osc 4 ’ to output a fourth output clock signal pair ‘clk_out 4 ’ and ‘/clk_out 4 ’.

In FIG. 2 , the voltage controlled oscillator 40 can generate the output clock signal pairs ‘clk_out<1:4>’ and ‘/clk_out<1:4>’ having phases that correspond to the PLL clock signal pair ‘clk_pll’ and ‘/clk_pll’. For example, the 4-input delay cell 4 DC of the oscillation unit 410 can receive the control voltage Vctrl as an input to generate the first oscillation clock signal pair ‘clk_osc 1 ’ and ‘/clk_osc 1 ’ having a frequency that corresponds to its voltage level. Accordingly, the output clock signal pairs ‘clk_out<1:4>’ and ‘/clk_out<1:4>’ can be configured to have substantially the same frequency with the PLL clock signal pair ‘clk_pll’ and ‘/clk_pll’. In addition, both the first to third 2-input delay cells 2 DC 1 to 2 DC 3 of the oscillation unit 410 and the first to fourth clock buffers BUF 1 to BUF 4 of the buffering unit 420 can have oscillator structures.

FIG. 3 is a schematic circuit diagram of an exemplary 4-input delay cell 4 DC capable of being implemented in the oscillator 40 of FIG. 2 according to one embodiment. In FIG. 3 , the 4-input delay cell 4 DC can receive the control voltage Vctrl as a positive control voltage Vctrl and a negative control voltage /Vctrl.

For example, the 4-input delay cell 4 DC can be configured to include a positive output node (Nout), a negative output node (/Nout), a pull-up unit 4 DC- 1 , and a pull-down unit 4 DC- 2 . The positive output node (Nout) can output the first positive oscillation clock signal ‘clk_osc 1 ’, and the negative output node (/Nout) can output the first negative oscillation clock signal ‘/clk_osc 1 ’. In addition, the pull-up unit 4 DC- 1 can pull-up the output node pair (Nout) and (/Nout) in response to the negative control voltage /Vctrl. For example, the pull-up unit 4 DC- 1 can include first to fourth transistors TR 1 to TR 4 .

In FIG. 3 , the first transistor TR 1 can have a gate terminal and a drain terminal commonly connected to the negative output node (/Nout), and a source terminal to which an external supply voltage VDD can be supplied. The second transistor TR 2 can have a gate terminal to which the negative control voltage/Vctrl can be supplied, a source terminal to which the external supply voltage VDD can be supplied, and a drain terminal connected to the negative output node (/Nout). The third transistor TR 3 can have a gate terminal to which the negative control voltage/Vctrl can be supplied, a source terminal to which the external supply voltage VDD can be supplied, and a drain terminal connected to the positive output node (Nout). The fourth transistor TR 4 can have a gate terminal and a drain terminal commonly connected to the positive output node (Nout), and a source terminal to which the external supply voltage VDD can be supplied.

The pull-down unit 4 DC- 2 can pull-down the output node pair (Nout) and (/Nout) in response to the PLL clock signal pair ‘clk_pll’ and ‘clk_pll’, the fourth oscillation clock signal pair ‘clk_osc 4 ’ and ‘/clk_osc 4 ’, and the positive control voltage Vctrl. For example, the pull-down unit 4 DC- 2 includes fifth to ninth transistors TR 5 to TR 9 .

The fifth transistor TR 5 can have a gate terminal to which the fourth positive oscillation clock signal ‘clk_osc 4 ’ can be input, a drain terminal connected to the negative output node (/Nout), and a source terminal connected to a first node (N 1 ). The sixth transistor TR 6 can have a gate terminal to which the positive PLL clock signal ‘clk_pll’ can be input, a drain terminal connected to the negative output node (/Nout), and a source terminal connected to the first node (N 1 ). The seventh transistor TR 7 can have a gate terminal to which the negative PLL clock signal ‘/clk_pll’ can be input, a drain terminal connected to the positive output node (Nout), and a source terminal connected to the first node (N 1 ). The eighth transistor TR 8 can have a gate terminal to which the fourth negative oscillation clock signal ‘/clk_osc 4 ’ can be input, a drain terminal connected to the positive output node (Nout), and a source terminal connected to the first node (N 1 ). The ninth transistor TR 9 can have a gate terminal to which the positive control voltage Vctrl can be input, a drain terminal connected to the first node (N 1 ), and a source terminal connected to a ground VSS.

Accordingly, the 4-input delay cell 4 DC can generate the first oscillation clock signal pair ‘clk_osc 1 ’ and ‘/clk_osc 1 ’ having a frequency that corresponds to levels of the positive control voltage Vctrl and the negative control voltage/Vctrl. For example, a level of the positive control voltage Vctrl can be higher than a level of the negative control voltage/Vctrl. Moreover, the larger a level difference between the positive control voltage Vctrl and the negative control voltage /Vctrl is, the higher the frequency of the first oscillation clock signal pair ‘clk_osc 1 ’ and ‘/clk_osc 1 ’ can be. In addition, the pull-down unit 4 DC- 2 can function such that the sixth transistor TR 6 and the seventh transistor TR 7 can have stronger driving powers than the fifth transistor TR 5 and the eighth transistor TR 8 . Thus, phases of the first oscillation clock signal pair ‘clk_osc 1 ’ and ‘/clk_osc 1 ’ can be relatively close to the phases of the PLL clock signal pair ‘clk_pll’ and ‘/clk_pll’.

As described above, a semiconductor IC can include a voltage controlled oscillator for providing output clock signals having multiple phases, which can be located near the plurality of data input/output buffers. In addition, the voltage controlled oscillator can control a frequency of output clock signals having multiple phases, which can be output from the voltage controlled oscillator, by using control voltage generated in a PLL circuit. Accordingly, the voltage controlled oscillator can provide clock signals having the same frequency with a PLL clock to the plurality of data input/output buffers. Thus, by using the voltage controlled oscillator instead of a DLL circuit, which is substantially smaller than a DLL circuit, area efficiency of a semiconductor IC can be improved. Moreover, since the voltage controlled oscillator consumes less power than a DLL circuit, power efficiency of a semiconductor IC can also be improved.

While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the device and methods described herein should not be limited based on the described embodiments. Rather, the device and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.