CMOS linear voltage/current dual-mode imager

This application is the National Stage of International Application No. PCT/US2007/011925 filed May 18, 2007, which claims the benefit of U.S. Provisional Application No. 60/802,011, filed May 19, 2006, the disclosure of which is incorporated herein by reference in its entirety.

The invention relates to an imaging device and, more particularly, to a linear voltage/current dual-mode imager that allows for mode switching and increased linearity.

CMOS active pixel sensors (APS) incorporate either voltage- or current-mode readout. Voltage-mode readout has been in use since the first 3-transistor (3T) CMOS APS imager disclosed by Fossum, “CMOS image sensors: electronic camera-on-a-chip,” IEEE Trans. Electron. Devices , Vol. 44, No. 10, pp. 1689-1698, 1997, and is still the dominant choice of CMOS imagers in the market today (see, El Gamal, et al. “CMOS image sensors,” IEEE Circuits Devices Mag ., Vol. 21, No. 3, pp. 6-20, 2005). Current-mode readout is used mostly to facilitate focal-plane image processing, because many analog computations can be easily done in the current domain as described, for example, by Gruev, et al., “Implementation of steerable spatiotemporal image filters on the focal plane,” IEEE Trans. Circuits Syst. II , Vol. 49, No. 4, pp. 233-244, 2002. Despite this advantage, most current-mode imagers suffer from higher noise level, or poorer image quality. An imager is desired that provides improved image quality while also facilitating focal-plane image processing. The present invention is provided to meet this need.

The invention relates to a dual-mode imager that is capable of both voltage-mode and current-mode readout. The entire pixel array can be set up in either mode by switches outside the array. Having a unified layout and access scheme, pixels may be mixed with readout transistors that are the same or optimized for each mode together in the same array, to establish a fair comparison of their performance in the two operating modes. One correlated double sampling (CDS) unit is included for each mode and shared by all the pixels to reduce fixed pattern noise (FPN).

In an exemplary embodiment, a voltage/current dual-mode imager receives output from an addressed pixel in a pixel array and provides the pixel output to a voltage-mode readout circuit and/or a current-mode readout circuit under control of a mode switch that is selectively controlled to provide the output of the pixel to either the voltage-mode readout circuit or the current-mode readout circuit. The current mode readout circuit operates in a linear region current mode under first bias conditions to a linear region of the readout transistor and operates in a velocity saturation current mode under second bias conditions to a saturation region of the readout transistor. The size of the respective readout transistors is optimized based on the mode of operation and the desired sensitivity, linearity, and noise performance. Alternatively, a single readout transistor may be used for both voltage and current mode readouts. Mode switches may be controlled to select between the voltage and current modes for a time multiplexed readout. This allows the simultaneous readout of both voltage mode and current mode outputs.

For efficient noise suppression, linear readout of the accumulated photo charge is required. Linear voltage readout is performed by a source follower in each pixel that drives the output line. On the other hand, linear current readout makes use of a transconductor, conventionally implemented by a transistor with fixed VDS operating in the linear region (see, Gruev, et al., “Linear current mode imager with low fix pattern noise,” Proc. IEEE ISCAS ' 04, Vol. 4, 2004, pp. 860-863). Another technique of linear current readout in accordance with the invention uses a velocity-saturated short-channel transistor.

The foregoing summary, as well as the following detailed description of the embodiments of the present invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. As should be understood, however, the invention is not limited to the precise arrangements and instrumentalities shown. In the drawings:

FIG. 1 illustrates one pixel in the imaging array with its readout circuitry.

FIG. 2 illustrates a mode selection switch and x and y switches for individual pixel addressing.

FIG. 3 illustrates an exemplary voltage-mode readout circuit.

FIG. 4 illustrates an exemplary current-mode readout circuit.

FIG. 5 illustrates graphs comparing the I-V curves of two current-mode readout transistors.

FIG. 6 illustrates the improved linearity of the velocity saturation current mode relative to the linear region current mode.

FIG. 7 illustrates the linearity of the 3 optimized readout transistors.

FIG. 8 illustrates a simulated example of the 3 readout modes at different light intensities.

FIG. 9 illustrates sample images for the voltage mode, the linear region current mode, and the velocity saturation current mode.

A detailed description of illustrative embodiments of the present invention will now be described with reference to FIGS. 1-9 . Although this description provides a detailed example of possible implementations of the present invention, it should be noted that these details are intended to be exemplary and in no way delimit the scope of the invention.

Dual-Mode Readout Architecture

FIG. 1 illustrates one pixel 10 in the imaging array with its readout circuitry 12 . The pixel 10 is based on the classical 3T APS design. Pixel 10 includes a photodiode 14 , a readout transistor M 1 , a reset switch M 2 and a column selection switch M 3 . An additional transistor, M 4 , is used to be able to reset the pixels individually. Transistor M 4 implements an AND function such that the reset pulse, which is common to a row, only triggers the reset in the selected column. Likewise, a row selection switch 16 exists at the end of every row of pixels. The row switches, together with the column switches in the pixels, enable the random access of any pixel in a pixel array.

In voltage-mode readout, the mode selection switches 18 are set to position 1 . This connects the drain on every readout transistor to VDD. The source, on the other hand, is connected to a constant current bias I 1 , for the selected pixel. Accumulated photocharge is detected using the readout transistor M 1 as a source follower, in order to drive the readout line associated with a large capacitance. The output circuitry includes a voltage-mode CDS 20 for fixed pattern noise (FPN) suppression, and an output buffer 22 . The timing signals for the voltage-mode readout are illustrated in the upper right-hand corner of FIG. 1 .

Current-mode operation corresponds to position 2 on the mode selection switches 18 . In this mode, the common terminals of the readout transistors M 1 are connected to ground, while the readout line connects to a current conveyor 24 which masks its large capacitance. Under specific bias conditions, the readout transistor M 1 in the selected pixel operates as a transconductor that converts the photocharge linearly to its drain current, which is then copied by the current conveyor 24 and processed by the current mode correlated double sampling (CDS) circuit 26 . The drain and source of M 1 have exchanged roles in this mode, and readout current now flows into the pixel array. The current source I 1 merely adds a constant offset current to meet the input range of the CDS circuit 26 . FIG. 2 illustrates the mode selection switch 18 and x and y switches 16 for individual pixel addressing.

Noise Suppression Circuits

As illustrated in FIGS. 1 and 2 , the imager of the invention has one voltage-mode and one current-mode CDS unit. They are shared by all the pixels, thus avoiding mismatch errors introduced with other row- or column-based CDS approaches.

Voltage-Mode CDS

The voltage-mode readout circuit 20 is shown in FIG. 3 . The CDS function is performed by a simple switched capacitor voltage memory 28 . During the first half of the read operation, the switch s is closed. Assuming an ideal current sink I 1 , the output of the source follower may be approximated as:

V pixel =V photo −V t   (1)

where V photo is the gate voltage of M 1 at the end of charge accumulation and Vt is the threshold of M 1 . In this phase, the voltage drop across the capacitor is:

V cap =V photo −V t −V 1   (2)

where V 1 is a constant voltage used to adjust the output range of the CDS. Next, the switch s is open, and the gate of M 1 is reset to V reset ( FIG. 1 ). Since the capacitor maintains the same voltage drop V cap , the output of the voltage memory must be (V reset −V t )−V cap , or:

V out =V reset −V photo +V 1   (3)

As V t is cancelled out in the equation, the FPN caused by V t variation among pixels will be corrected. The output of the voltage-mode readout circuit 30 is provided to a display (not shown) via output buffer 22 .

Current-Mode CDS

FIG. 4 shows the current-mode readout circuit 40 . The two current memory cells 42 , 44 (first and second stages) implement the CDS function, while the current conveyor 24 has two purposes: it clamps the voltage on the readout line to V d — ref , and it passes a copy of the input current (I pixel +I 1 ) to the CDS 42 , 44 . Since the readout line connects to the drain of a readout transistor M 1 , whose source is grounded, a small V d — ref may be chosen to bias the device in the linear region. In this case, the pixel current is:

This current goes to the two-stage current memory 42 , 44 , which is based on the S 3 I design in Hughes, et al., “S 3 I: The seamless S 2 I switched-current cell,” Proc. IEEE ISCAS ' 97, Vol. 1, 1997, pp. 113-116. During the p 1 a phase, the first memory cell 42 is active. The negative-feedback opamp 48 sets the gate voltage on M 5 , such that the I DS of M 5 is equal to I pixel +I 1 . Then, the p 1 a switches are open. At this instance, the gate voltage of M 5 is lowered due to negative-charge injection (since N-channel switches are used). M 5 now sinks I pixel +I 1 −I e1 . I e1 , representing the error of the first stage 42 , and will be memorized by the second stage 44 during the p 1 b phase. The second stage 44 is virtually identical to the first stage 42 except that opamp 48 is replaced by opamp 50 and M 5 is replaced by M 6 . At the end of the p 1 b phase, the second stage again introduces its error I e2 , which becomes the total error of the CDS 26 . However, I e2 is only dependent on I e1 ; it is not directly related to the original value of I pixel . Therefore it can be regarded as a relatively constant offset error, with only a small variance compared to I e1 and I pixel .

When the pixel is reset, the expression of pixel current (Equation (4)) would have its V photo replaced by V reset . The final output in phase p 2 is then the difference of the two pixel currents, plus the error I e2 , i.e.

I out =β[( V reset −V photo )] V d-ref +I e2   (5)

Again, V t is cancelled out, achieving FPN suppression.

The opamps 48 , 50 in the memory cells bring an additional benefit, as they fix the drain voltage of M 5 and M 6 to V o — ref during memorization. This eliminates the channel length modulation caused by V D variation. Both M 5 and M 6 can be replaced by cascode devices, making them less sensitive to V D during the output phase (p 2 ). Also, the two opamps 48 , 50 can be combined into a single one, shared by both cells.

Linear Current Readout Technique

The conventional linear current readout method, as described in the preceding section, suffers from two sources of nonlinearity. The first is due to mobility dependence on the gate voltage of the readout transistor M 1 , also known as mobility degradation. In other words, the β in Equation (4) becomes a function of V photo . The second is due to voltage drop across the access switches 16 . Although the current conveyor 24 clamps the voltage on the readout line, the VDS across the row and column switches 16 are still function of I photo . This effect is more severe at the in-pixel switch, whose size cannot be very large. As a result, the V D of the readout transistor M 1 can no longer be represented by the constant V d — ref in Equation (4).

The readout technique of the invention is immune to the above two causes of nonlinearity since a short-channel device working in the velocity-saturated region is used as the readout transistor M 1 . Velocity saturation occurs when the electric field along the channel increases beyond a critical value, so that a constant mobility μ n cannot be sustained. This critical value E sat is about 1.5×10 4 V/cm for p-type silicon. The carrier velocity ν n , normally expressed as

- μ n ⁢ ⅆ V ⅆ x ,

now reaches a constant ν sat . Any further increase in the E-field can only decrease the mobility, but will not increase the velocity. The channel current expression under this condition is, as a first approximation:

I DS −ν sat C ox W ( V GS −V DSAT −V t )  (6)

where V DSAT is the drain-source voltage at which velocity saturation comes into play.

V DSAT is a function of V GS , which determines the degree of velocity saturation. However, when V GS is large (but not so large as to enter linear region), one can regard V DSAT as a constant equal to E SAT L. With this approximation, a linear relationship is found between I DS and V GS . Also, inconsistent with the saturation of a long-channel device, I DS does not depend on V DS as the channel is pinched off.

FIG. 5 compares the I-V curves of two current-mode readout transistors. One can identify the effect of mobility degradation in both of them, as the curves bend downwards for large VGS. However, velocity saturation is observed for the short-channel transistor, identified by the dashed box on the second plot. Despite being linear, this region also has a very high voltage-to-current conversion gain. FIG. 6 illustrates the improved linearity of the velocity saturation current mode relative to the linear region current mode.

The same voltage-mode CDS circuit 20 described above with respect to FIG. 3 can be used with this readout mode. The voltage reference V d — ref of the current conveyor 24 needs to be large enough to ensure saturation, while a small or zero I 1 is desired because of the already-large pixel current. The final output current is:

I out =ν sat C ox W ( V reset −V photo )+ I e2   (8)

Compared with Equation (5), the technique of the invention not only is insensitive to the signal-dependency of μ n and V D , but also corrects for the length mismatches of the readout transistors.

Transistor Sizing in Pixels

In an exemplary embodiment, the pixels 10 have readout transistors M 1 that are of the same size and hence not optimized for the voltage mode or the current mode. However, in an alternate embodiment, the readout transistors may be optimized by the mode of operation and one or more such readout transistors provided for each pixel. In such case, it may be assumed, for example, that each pixel 10 has a pitch of 12 μm×12 μm and a fill factor of 31.25%. The reset and access switches all have minimum length. M 3 has the largest width, in order to minimize its on-resistance in current-mode readout. M 2 has a smaller width in order to reduce the parasitic capacitance at the integrating node, and to limit the charge injection when it switches off from the reset phase. The size of M 2 and M 4 are chosen to ensure that the pixel 10 can be reset in about 100 ns in all modes, according to a 30 fps output rate. The layout of photodiode and NMOS switches is identical in all pixels 10 .

An exemplary embodiment contains 3 different sizes of in-pixel readout transistor M 1 , each optimized for a specific mode of operation. In the embodiment where a single readout transistor is used for either voltage mode or current mode readouts via mode switches, the size of the readout transistor should be chosen with the consideration of the application's performance criteria.

Voltage-Mode Readout Transistors

The linearity of the voltage-mode signal path is affected by 3 factors: the readout transistor M 1 's channel length modulation, body effect, and the current sink I 1 's output impedance. When the first two factors are considered, the output voltage V S of the source follower can be written as:

V s =V G −V t −V ON   (9)

where:

The two equations describe the body effect and the channel length modulation, respectively. They are both function of the source follower output V S , which in turn depends on the input voltage V G . The body effect cannot be eliminated with such a single well process; however, the channel length modulation effect may be reduced by making β large, i.e., using a large

W L ,

where W is the width and L is the length of the well. This would make V ON close to zero (which has been assumed in Equation (1)) and less dependent on V S variation.

The nonlinearity caused by a non-ideal current sink I 1 can be seen by writing out the small-signal voltage gain function of the source follower:

V out V in = ?? ⁢ ⁢ m ⁢ ⁢ 1 ?? ⁢ ⁢ m ⁢ ⁢ 1 + ?? ⁢ ⁢ mbs ⁢ ⁢ 1 + G L = 1 1 + ?? ⁢ ⁢ mbs ⁢ ⁢ 1 ?? ⁢ ⁢ m ⁢ ⁢ 1 + G L ?? ⁢ ⁢ m ⁢ ⁢ 1 ( 12 )

where G L is the total conductance after combining Gds 1 with the impedance of the load and I 1 ; Gm 1 and Gmbs 1 are the transconductance and the body transconductance of transistor M 1 , respectively. Since the current sink I 1 has a finite output impedance, its output current I 1 will be a function of V S . This means that the Gm 1 term in Equation (12) will vary according to the operating point set by V S , yielding a non-constant gain. To reduce this nonlinearity, Gm 1 must be made large, by choosing a large

W L .

This also serves to attenuate the body effect, which shows up as Gmbs 1 in the equation.

Thus, in voltage-mode, M 1 is required to have a large W and a small L.

Current-Mode Readout Transistors in Linear Region

The sources of nonlinearity in the current readout mode have already been discussed above. Mobility degradation is a short-channel effect and can be reduced by choosing a large L. It is also desirable to have a large V DS on M 1 , which makes the voltage drop across access switches less significant. This implies a small

W L

for M 1 . In short, this mode requires M 1 to have a small W and a large L.

Current-Mode Readout Transistors in Velocity Saturation

The onset of velocity saturation requires the E-field along the channel to be greater than E sat . The more this field exceeds E sat , the more it makes V DSAT constant in Equation (6). Therefore, it is desirable to have a small L. One may also want to choose a small W to limit the pixel current, in order to match the input range of the current-mode CDS unit, which is also used in the linear-region readout mode. However, making W too small is subject to greater transistor mismatches that will not be corrected by CDS.

Simulation Results

Linearity of the 3 optimized readout transistors were simulated in HSpice. The results are shown in FIG. 7 . A DC sweep was performed while the gate voltage of the transistors ramps down by 0.5V, to emulate the accumulation of photocharge. The output levels are normalized to a linear scale between 0 and 1. Linearity is calculated based on the maximum deviation from a best-fit straight line. It is seen that the voltage mode readout transistor yields the best linearity. Velocity-saturated current mode comes a close second, and has a significant improvement over the conventional linear-region current mode.

FIG. 8 shows a simulated example of the 3 readout modes at different light intensity. The outputs exhibit linear steps, in accordance with the voltage on the photodiode at the end of an integration cycle. FIG. 9 illustrates sample images for the voltage mode, the linear region current mode, and the velocity saturation current mode. As illustrated, the voltage mode provides the best image; however, the velocity saturation mode provides a significantly better image than the linear region current mode.

The dual-mode imager of the invention thus actual supports 3 modes, each mode requiring a different sized readout transistor as follows:

voltage mode: large W, small L;

linear region current mode: small W, large L; and

velocity saturation current mode: small W, small L.

The resulting dual mode imager allows one to extract information in the current mode, as for a comparison study, and to optimally display the image in the voltage mode. Each mode is optimized by transistor size. It will be appreciated that the transistors in the velocity saturation mode are smallest and thus saturate more rapidly and are more sensitive. The modes may be time-multiplexed for readout. For example, the voltage mode may be used for odd frames while the current mode is used for even frames.

It should be understood that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims. All such aspects of the invention are intended to be covered by the appended claims.