DC-DC converter, DC-DC converter control method, and electronic device

This application claims the benefit of priority from Japanese Patent Application No. 2007-333553 filed on Dec. 26, 2007, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

This application relates to a DC-DC converter.

2. Description of Related Art

A DC-DC converter converts an input voltage from a battery coupled thereto and supplies a variety of circuits with a stabilized output voltage. The circuits to which the DC-DC converter supplies a power supply voltage include circuits that are incorporated in electronic devices such as personal computers, mobile phones, gaming devices, and digital cameras.

Techniques related to the DC-DC converter are disclosed in Japanese Laid-open Patent Publication No. 2005-192312, Japanese Laid-open Patent Publication No. 2005-192323, and Japanese Laid-open Patent Publication No. H9-223837.

According to one aspect of an embodiment, a DC-DC converter is provided. The DC-DC converter includes a control unit that controls a current stored in an inductance and an output voltage output from an output terminal electrically couplable to the inductance. The control unit assigns a first period and a second period to a given period when the output voltage is lower than a given value in response to a load electrically couplable to the output terminal. The first period is where a current is stored in the inductance in response to an input voltage and a reference voltage, and the second period is where the current stored in the inductance is supplied to the output terminal in response to the input voltage and the output voltage.

Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention.

FIG. 1 illustrates a first embodiment;

FIG. 2 illustrates a state ( 3 ) time control circuit;

FIG. 3 illustrates a state of a DC-DC converter;

FIG. 4 illustrates another state of the DC-DC converter;

FIG. 5 illustrates yet another state of the DC-DC converter;

FIG. 6 illustrates a waveform diagram of inductor current;

FIG. 7 illustrates a waveform diagram of the DC-DC converter in a steady state;

FIG. 8 illustrates a waveform diagram of state ( 3 ) time control circuit;

FIG. 9 illustrates a waveform diagram of the DC-DC converter in a transient response;

FIG. 10 illustrates a second embodiment;

FIG. 11 illustrates a state ( 3 ) time control circuit;

FIG. 12 illustrates a waveform diagram of a DC-DC converter in a steady state;

FIG. 13 illustrates a waveform diagram of the DC-DC converter in a transient response;

FIG. 14 illustrates a correlation between an output signal Eout and a current Id.

FIG. 15 illustrates a third embodiment;

FIG. 16 illustrates a waveform diagram of a DC-DC converter in a steady state; and

FIG. 17 illustrates a waveform diagram of the DC-DC converter in a transient response.

FIG. 1 illustrates a first embodiment. When a load suddenly increases, a speed of a transient response is set to high in a step up/step down DC-DC converter 1 according to the first embodiment. The DC-DC converter 1 is a H-bridge-type switching regulator. The DC-DC converter 1 includes a choke coil L 1 , transistors FET 1 , FET 2 , FET 3 , and FET 4 , an output capacitor C 1 , and a control circuit 11 . An input terminal Tin is coupled to a drain terminal of the transistor FET 1 . A battery 6 is coupled to the input terminal Tin into which an input voltage Vin is input. The battery 6 may be, for example, a battery used in mobile devices such as mobile phones. The battery may include a DC battery, a lithium battery or the like. The battery 6 may be a power supply obtained by DC-converting and transforming an AC power supply or other power supply except for a converter used in a notebook-type personal computer. A source terminal of the transistor FET 1 is coupled to a terminal Tx of the choke coil L 1 and a drain terminal of the transistor FET 2 . A source terminal of the transistor FET 2 is coupled to a reference electric potential. Gate terminals of the transistors FET 1 and FET 2 are coupled to output terminals DH 1 and DL 1 of the control circuit 11 , respectively.

A drain of the transistor FET 4 is coupled to an output terminal Tout. The stepped-up/stepped-down input voltage Vin is output as an output voltage Vout from the output terminal Tout. The output capacitor C 1 is coupled between the output terminal Tout and the reference electric potential so as to store electric power supplied via the choke coil L 1 . The output terminal Tout is coupled to an input terminal FB of the control circuit 11 . A load 5 is coupled to the output terminal Tout. The load 5 may be, for example, an internal circuit of a mobile device, such as a personal computer, a mobile phone, a gaming device, a digital camera, and other electronic devices, or a rechargeable battery, such as a lithium battery or the like that is incorporated in a note-type personal computer or the like. A source terminal of the transistor FET 4 is coupled to a terminal Ty of the choke coil L 1 and a drain terminal of the transistor FET 3 . A source terminal of the transistors FET 3 is coupled to the reference electric potential. Gate terminals of the transistors FET 3 and FET 4 are respectively coupled to the output terminals DH 2 and DL 2 of the control circuit 11 .

The control circuit 11 includes an error amplifier ERA, a PWM control circuit PC, a status control circuit SC, an oscillator OSC, a state ( 3 ) time control circuit TC 3 , a logic unit LC, and resistor elements R 1 and R 2 . The logic unit LC includes AND circuits AD 1 and AD 2 and inverters INV 1 and INV 2 . The logic unit LC masks state signals ST 2 and ST 3 in a period where a state signal ST 1 is a high level. The logic unit LC masks the state signal ST 3 in a period where the state signal ST 1 is a low level and the state signal ST 2 is the high level. The input terminal FB is coupled to one end of the resistor element R 1 that is coupled, via the resistor element R 2 , to the reference electric potential. A coupling node between the resistor elements R 1 and R 2 is coupled to an inverting input terminal of the error amplifier ERA. A reference voltage Vref is applied to a non-inverting input terminal of the error amplifier ERA. The error amplifier ERA outputs an output signal Eout. The oscillator OSC outputs a clock signal CLK. The PWM control circuit PC receives the output signal Eout and the clock signal CLK and outputs the state signal ST 1 . The state signal ST 1 is input to both the status control circuit SC and, via the inverter INV 1 , to the AND circuits AD 1 and AD 2 . The state ( 3 ) time control signal TC 3 receives the clock signal CLK and outputs a control signal CT 3 . The control signal CT 3 is input to both the AND circuit AD 2 and, via the inverter INV 2 , to the AND circuit AD 1 . The state signal ST 2 output from the AND circuit AD 1 is input to the status control circuit SC. The state signal ST 3 output from the AND circuit AD 2 is input to the status control circuit SC.

Output terminals Q 1 and Q 2 of the status control circuit SC are coupled to the output terminals DH 1 and DH 2 . On the other hand, output terminals *Q 1 and *Q 2 of the status control circuit SC are coupled to the output terminals DL 1 and DL 2 . The output terminals Q 1 , *Q 1 , Q 2 , and *Q 2 output control signals VQ 1 , *VQ 1 , VQ 2 , and *VQ 2 , respectively. The status control circuit SC controls the control signals VQ 1 , *VQ 1 , VQ 2 , and *VQ 2 based upon the state signals ST 1 and ST 3 .

FIG. 2 illustrates the state ( 3 ) time control circuit TC 3 . The input voltage Vin is input to an inverting input terminal of an amplifier AMP and the output voltage Vout is input to a non-inverting input terminal of the amplifier AMP. A power supply voltage Vcc is input to a D terminal of a flip-flop FF. The clock signal CLK is input via an inverter INV 3 to a CK terminal of the flip-flop FF. An output signal from a Q terminal of the flip-flop FF is output as the control signal CT 3 to an outside of the state ( 3 ) time control circuit TC 3 via an inverter INV 4 and also input to a gate terminal of a transistor M 1 . A source terminal of the transistor M 1 is grounded and a drain terminal of the transistor M 1 is coupled to a node ND 2 . One end of a capacitor C is grounded and the other end is coupled to the node ND 2 . A constant current source CC and an inverting input terminal of a comparator COMP are coupled to the node ND 2 . An output voltage V 1 output from the amplifier AMP is input to a non-inverting input terminal of the comparator COMP and a voltage V 2 of the node ND 2 is input to the inverting input terminal thereof. An output terminal of the comparator COMP is coupled to an R terminal of the flip-flop FF.

FIGS. 3 , 4 , and 5 illustrate states of the DC-DC converter 1 . Transition to three different states takes place in the DC-DC converter 1 in response to combinations of ON/OFF states of the transistors FET 1 , FET 2 , FET 3 , and FET 4 .

If the control signals VQ 1 and VQ 2 are a high level and the control signals *VQ 1 and *VQ 2 are a low level, the transistors FET 1 and FET 3 turn ON and the transistors FET 2 and FET 4 turn OFF. As illustrated in FIG. 3 , the terminal Tx of the choke coil L 1 is coupled to the input terminal Tin and the terminal Ty thereof is coupled to the reference electric potential, so that a transition to a state ( 1 ) is performed. In the state ( 1 ), energy from an input terminal Tin side is stored in the choke coil L 1 , and an inductor current IL increases at a steep and uniform gradient with time.

If the control signals *VQ 1 and *VQ 2 are a high level and the control signals VQ 1 and VQ 2 are a low level, the transistors FET 1 and FET 3 turn OFF and the transistors FET 2 and FET 4 turn ON. As illustrated in FIG. 4 , the terminal Tx of the choke coil L 1 is coupled to the reference electric potential and the terminal Ty of the choke coil L 1 is coupled to the output terminal Tout, so that a transition to a state ( 2 ) is performed. In the state ( 2 ), the energy is discharged from the choke coil L 1 toward an output terminal Tout side and the inductor current IL decreases at a steep and uniform gradient with time.

If the control signals VQ 1 and *VQ 2 are a high level and the control signals *VQ 1 and VQ 2 are a low level, the transistors FET 1 and FET 4 turn ON and the transistors FET 2 and FET 3 turn OFF. As illustrated in FIG. 5 , the terminal Tx of the choke coil L 1 is coupled to the input terminal Tin and the terminal Ty of the choke coil L 1 is coupled to the output terminal Tout, so that a transition to the state ( 3 ) is performed. In the state ( 3 ), if the input voltage Vin is higher than the output voltage Vout, the energy from the input terminal Tin side is stored in the choke coil L 1 and is contemporaneously supplied to the output terminal Tout side, and the inductor current IL increases at a constant gradient with time. If the input voltage Vin is lower than the output voltage Vout, the energy is discharged from the choke coil L 1 toward the output terminal Tout side, and the inductor current IL decreases at a constant gradient with time.

FIGS. 6A to 6C illustrate waveform diagrams of the inductor current IL. Since a state of a load (not illustrated) coupled to the output terminal Tout is kept constant, the output voltage Vout becomes a steady state. FIG. 6A is the waveform diagram where a step down operation of “input voltage Vin>output voltage Vout” is performed. FIG. 6B is the waveform diagram where a step up/step down operation of “input voltage Vin=output voltage Vout” is performed. FIG. 6C is the waveform diagram where a step up operation of “input voltage Vin<output voltage Vout.” is performed. A single operation cycle T includes the state ( 1 ) to the state ( 3 ) in any of the cases illustrated in FIGS. 6A to 6C , during the steady state. The transition takes place in the order from the state ( 1 ) through the state ( 2 ) to the state ( 3 ) in the operation cycle T.

In FIG. 6A , a time period of the state ( 1 ) is fixed at a minimum time period t 1 _min and PWM control is performed in a time period t 2 of the state ( 2 ) and a time period t 3 of the state ( 3 ). The minimum time period t 1 _min is a minimum PWM period in the PWM control circuit PC. The minimum PWM period is determined based upon delay times or the like of a variety of circuits, such as a comparator, a flip-flop, and so on, which are incorporated inside the PWM control circuit PC.

As illustrated in FIGS. 6A and 6B , the increasing gradient of the inductor current IL in the state ( 1 ) is determined based upon (Vin/L), where L represents an inductance value of the choke coil L 1 . The decreasing gradient of the inductor current IL in the state ( 2 ) is determined based upon −(Vout/L). The increasing gradient of the inductor current IL ( FIG. 6A ) or the decreasing gradient of the inductor current IL ( FIG. 6C ) in the state ( 3 ) is less than the increasing gradient in the state ( 1 ) or the decreasing gradient in the state ( 2 ). If the input voltage Vin is close to the output voltage Vout, the gradient of the inductor current IL in the state ( 3 ) is zero or close to zero ( FIG. 6B ).

In order to improve efficiency of the DC-DC converter 1 in the steady state, it is necessary that storing wasted energy in the choke coil L 1 and discharging the wasted energy from the choke coil L 1 be reduced. Making the time period of the state ( 1 ) equal to the minimum time period t 1 _min allows the energy stored in the choke coil L 1 to be minimized. A circuit that achieves the effective and ideal waveforms illustrated in FIGS. 6A to 6C is necessary.

The time period t 2 and the time period t 3 necessary to achieve the waveforms illustrated in FIGS. 6A to 6C will be determined. If the output voltage Vout of the DC-DC converter 1 is the steady state, it is necessary that, in any of the cases illustrated in FIGS. 6A to 6C , an increased amount of the inductor current IL increased with the minimum time period t 1 _min of the state ( 1 ) be decreased with the time period t 2 of the state ( 2 ) and the time period t 3 of the state ( 3 ), so that the output voltage Vout may be stabilized. To achieve this, it is necessary that the increased amount of the inductor current IL increased with the minimum time period t 1 _min be equal to the decreased amount of the inductor current IL decreased with during the time period t 2 and the time period t 3 . The above relationship is represented by the following equation.

( V in/ L )* t 1_min−( V out/ L )* t 2+{( V in− V out)/ L}*t 3=0   (1)

T=t 1_min+ t 2+ t 3   (2)

The time period t 2 and the time period t 3 are obtained by Equation (1) and Equation (2) to achieve the waveforms illustrated in FIGS. 6A to 6C . The time period t 3 that makes the time period of the state ( 1 ) equal to the minimum time period t 1 _min is obtained by the following equation (3).

t 3=( V in/ V out)*( T−t 1_min)− t 1_min   Equation (3)

The time period t 2 that makes the time period of the state ( 1 ) equal to the minimum time period t 1 _min may be obtained by the following equation (4).

t 2= T−t 1_min− t 3   Equation (4)

The time period t 2 and the time period t 3 necessary for achieving the waveforms illustrated in FIGS. 6A to 6C may be obtained when determining values of the input voltage Vin, the output voltage Vout, and the minimum time period t 1 _min.

In order to control the DC-DC converter ( 1 ) based upon the minimum time period t 1 _min, the time period t 2 , and the time period t 3 obtained from the above equations, any one of the state time periods among the state ( 1 ) to the state (3) is defined as a fixed value obtained by the above equations, and the remaining two state time periods are defined as variables based upon the PWM control. Since a feedback loop is carried out to stabilize the output voltage Vout with the PWM control, the remaining two state time periods, on which the PWM-control is performed, fall within the state time periods obtained by the above equations.

FIG. 7 illustrates a waveform diagram of the DC-DC converter 1 in the steady state. The clock signal CLK is a clock pulse of an operation cycle T. An output current Iout is an average value of the inductor current IL. FIG. 7 illustrates operations of the DC-DC converter 1 . In the operations, a value of the input voltage Vin is close to a value which is substantially equal to that of the output voltage Vout, and a gradient of a current sensing signal Vs in the state ( 3 ) is zero or close to zero.

At a point of time P 1 ( FIG. 7 ), the state signal ST 1 output from the PWM control circuit PC illustrated in FIG. 1 makes a transition to a high level (arrow A 1 ) in response to a falling edge of the clock pulse of the clock signal CLK. The state signal ST 3 make a transition to a low level. The status control circuit SC illustrated in FIG. 1 causes the control signal VQ 2 to make a transition to a high level and causes the control signal *VQ 2 to make a transition to a low level (arrow A 2 ) in response to an input of the state signal ST 1 at a high level. The transition to the state ( 1 ) is performed and the operation cycle T is started. Since the choke coil L 1 receives the energy from the input side with its output side being shutoff, in the state ( 1 ), the inductor current IL increases with the steep gradient.

The PWM control circuit PC illustrated in FIG. 1 includes a comparator (not illustrated). The comparator compares the current sensing signal obtained by detecting the inductor current IL to the output voltage Eout. At a point of time P 2 , the state signal ST 1 output from the PWM control circuit PC makes a transition to a low level when the current sensing signal reaches the output signal Eout. The state signal ST 2 output from the AND circuit AD 1 illustrated in FIG. 1 makes a transition to a high level (arrow A 3 ) in response to the state signal ST 1 making the transition to a low level. The status control circuit SC causes the control signals VQ 1 and VQ 2 to make a transition to a low level and the control signals *VQ 1 and *VQ 2 to a high level (arrow A 4 ) in response to the state signal ST 2 at a high level being input. The state ( 1 ) is switched to the state ( 2 ). In the state ( 2 ), since the output side of the choke coil L 1 is coupled contemporaneously upon the input side being shut off, the inductor current IL decreases with the steep gradient.

At a point of time P 3 after the a fixed time period t 3 off has elapsed from the point of time P 1 , the control signal CT 3 output from the state ( 3 ) time control circuit TC 3 makes a transition to a high level. The time period t 3 off is a value (fixed value) obtained by subtracting the time period t 3 in the state ( 3 ) from the operation cycle T. In response to a rising edge of the control signal CT 3 , the state signal ST 3 makes a transition to a high level and the state signal ST 2 makes a transition to a low level (arrow A 5 ). The status control circuit SC causes the control signal VQ 1 to make the transition to a low level and the control signal *VQ 1 to a high level, in response to the state signal ST 3 at a high level. The state ( 2 ) is switched to the state ( 3 ).

The state ( 3 ) is maintained until a point of time P 4 , at which the time period t 3 has elapsed. In the state ( 3 ), since the input voltage Vin is close to the output voltage Vout, the gradient of the inductor current IL is zero or close to zero as illustrated in FIG. 7 . The inductor current IL is maintained at a value of the point of time P 3 . The inductor current IL is maintained substantially at a minimum current value during the state ( 3 ).

At a point of time P 4 , the state signal ST 1 makes the transition to a high level (arrow A 7 ) in response to a falling edge of the clock signal CLK. The state signal ST 3 makes the transition to a low level. Then the operation cycle T is terminated. The time period t 3 is defined as the fixed time in the steady state of the output voltage Vout. The PWM control circuit PC PWM-controls the time periods of the state ( 1 ) and of the state ( 2 ).

The time period t 3 is obtained by means of Equation (3) based upon a relationship between the input voltage Vin and the output voltage Vout. The circuit illustrated in FIG. 2 may be one example of a circuit that determines the time period t 3 according to Equation (3).

FIG. 8 illustrates a waveform diagram of the state ( 3 ) time control circuit. Data is fed into the flip-flop FF illustrated in FIG. 2 at a falling edge of the clock signal CLK, and the control signal CT 3 makes a transition to a low level (arrow All in FIG. 8 ). Upon the control signal CT 3 making the transition to a low level, the transistor M 1 turns OFF and a current Ic output from the constant current source CC as illustrated in FIG. 2 is stored in the capacitor C, thereby the voltage V 2 rising (arrow A 12 ).

Upon the voltage V 2 reaching the output voltage V 1 at a point of time P 12 , an output voltage of the comparator COMP illustrated in FIG. 2 makes a transition to a low level, and the flip-flop FF is reset. The control signal CT 3 makes a transition to a high level and the time period t 3 off is terminated (arrow A 13 ). Upon the control signal CT 3 making the transition to a high level, the transistor M 1 turns ON and capacitor C discharges the current, thereby maintaining the voltage V 2 at or near zero. In a point of time P 13 , the control signal CT 3 makes the transition to a low level in response to a falling edge of the clock signal CLK, and the time period t 3 is terminated (arrow A 14 in FIG. 8 ). One operation cycle T is terminated.

The output voltage V 1 output from the amplifier AMP illustrated in FIG. 2 is determined based upon the relationship between the input voltage Vin and the output voltage Vout. Since the output voltage V 1 drops in response to a drop in the output voltage Vout, an ON-duty state in the time period t 3 increases. Since the output voltage V 1 rises in response to a rise in the output voltage Vout, the ON-duty state in the time period t 3 decreases. If the current Ic and a capacitance of the capacitor C are appropriately determined, the time period t 3 may be determined so that Equation (3) is satisfied based upon the input voltage Vin and the output voltage Vout using the state ( 3 ) time control circuit TC 3 .

The transitions among the states in the operation cycle T are repeated in the following order: state ( 1 )→state ( 2 )→state ( 3 ). Since the energy is supplied to the output terminal Tout side in an area illustrated as a shaded area of the inductor current IL in FIG. 7 , the output current Iout is supplied to the load.

FIG. 9 illustrates a waveform diagram of the DC-DC converter 1 in a transient response. In FIG. 9 , a sudden increase in load makes the DC-DC converter 1 perform the transient response. Operations performed from cycle T 1 to cycle T 4 are shown in FIG. 9 . For example, a load suddenly increases due to a sudden power consumption caused by concurrent operations of a variety of circuits in an electronic device, such as a mobile device or the like, when such an electronic device returns to a normal state after being in a stand-by state that limits the power supply voltage supplied to the circuits to extend the operating time of the device.

The steady state is maintained in the cycle T 1 . The time t 3 is defined as the fixed value in the cycle T 1 and the PWM control is performed in the state ( 1 ) and in the state ( 2 ).

The load suddenly increases at a point of time P 21 after a transition to the cycle T 2 . The transient response takes place during the cycle T 2 . The output current Iout rises, the output voltage Vout drops, and the output signal Eout rises. In response to the rise in the output signal Eout, a period where the state signal ST 1 attains a high level in the operation cycle T becomes longer. If the period where the state signal ST 1 is at a high level exceeds a point of time P 22 that corresponds to a rising edge of the control signal CT 3 , the AND circuit AD 1 masks the state signal ST 2 (area R 21 ).

In response to the state signal ST 1 making a transition to a low level at a point of time P 23 , the state signal ST 3 output from the AND circuit AD 3 makes a transition to a high level (arrow A 21 ). The state ( 1 ) is switched to the state ( 3 ).

The transition to the state ( 2 ) is not performed in the cycle T 2 . The PWM control circuit PC and the logic unit LC PWM-control the time periods of the state ( 1 ) and of the state ( 3 ) in the cycle T 2 . Owing to the PWM control carried out in the state ( 1 ) and in the state ( 3 ), the ON-duty of the time period t 1 of the state ( 1 ) may be increased in response to load states. Consequently, the greater energy is stored in the choke coil L 1 through the input voltage Vin side. For a steep rise in the inductor current IL, the speed of a transient response is improved.

Due to the transient response, the transition to the state ( 2 ) is not performed in the cycle T 3 , and the PWM control is performed in the state ( 1 ) and in the state ( 3 ). The steady state is restored at a point of time P 25 in the cycle T 4 when the inductor current IL rises to a preferable necessary level. Since the steady state is maintained in the cycle T 4 , the time period t 3 is defined as the fixed value, and the PWM control is performed in the state ( 1 ) and in the state ( 2 ).

In the first embodiment, the time period t 3 is fixed in the cycle T 1 and in the cycle T 4 where the steady state is maintained, and the PWM control is performed in the state ( 1 ) and in the state ( 2 ). The waveforms illustrated in FIGS. 6A to FIG. 6C are achieved, and the efficiency may be improved. The transition to the state ( 2 ) is not performed in the cycle T 2 and in the cycle T 3 where the transient response to the sudden increase in load takes place, and the PWM control is performed in the state ( 1 ) and in the state ( 3 ). Since the time period of the state ( 1 ) is made longer in response to the load states, the speed of the transient response may be improved. A method of control may be switched so that the PWM control is performed in the state ( 1 ) and in the state ( 2 ) during the steady state, and the PWM control is performed in the state ( 1 ) and in the state ( 3 ) where the transient response takes place. In consequence, the improvement of the efficiency in the steady state and also the response speed of the transient response to a sudden increase in load may be achieved.

FIG. 10 illustrates a second embodiment. A step up/step down DC-DC converter 1 a as illustrated in FIG. 10 includes a sensing resistor Rs 1 between a coupling path of an input terminal Tin and a choke coil L 1 . Both ends of the sensing resistor Rs 1 are coupled to a current sensing unit IS via a terminal TS 1 and a terminal TS 2 . An output terminal of the current sensing unit IS is coupled to a node ND 3 via a switch SWs. An offset voltage Voffset is input to the node ND 3 via a resistor element Rs 2 . The offset voltage Voffset is input to a state ( 3 ) time control circuit TC 3 a . The node ND 3 is coupled to a non-inverting input terminal of a comparator COMP.

A PWM control circuit PCa includes the comparator COMP and a flip-flop FF 2 . A voltage value of the node ND 3 is input, as a current sensing signal Vsense, to the non-inverting input terminal of the comparator COMP. An output signal Eout is input to an inverting input terminal of the comparator COMP. An output terminal of the comparator COMP is coupled to an R terminal of the flip-flop FF 2 , and an output terminal of an oscillator OSC is coupled to an S terminal of the flip-flop FF 2 . The state ( 3 ) time control circuit TC 3 a receives the output signal Eout, the offset voltage Voffset, and a clock signal CLK. The state ( 3 ) time control circuit TC 3 a outputs a control signal CT 3 . A state signal ST 1 output from the flip-flop FF 2 is input to a status control circuit SC and to the switch SWs. Other structural elements in the second embodiment are the same as those of the DC-DC converter 1 ( FIG.1 ) in the first embodiment and detailed descriptions thereof are reduced or omitted.

FIG. 11 illustrates the state ( 3 ) time control circuit TC 3 a . The state ( 3 ) time control circuit TC 3 a is different from the state ( 3 ) time control circuit TC 3 ( FIG. 2 ) in the first embodiment and includes a current conversion unit IT. The offset voltage Voffset is input to a non-inverting input terminal of the current conversion unit IT, and the output signal Eout is input to an inverting input terminal. An output terminal of the current conversion unit IT is coupled to a node ND 2 . A current Id corresponding to a difference between the offset voltage Voffset and the output signal Eout is induced to flow through a constant current source of the current conversion unit IT. Other structural elements in the state ( 3 ) time control circuit TC 3 a are the same as those of the state ( 3 ) time control circuit TC 3 in the first embodiment and detailed descriptions thereof are reduced or omitted.

FIG. 12 illustrates a waveform diagram of the DC-DC converter 1 a in a steady state. Since a load state is constant in FIG. 12 , an output voltage Vout becomes the steady state. The level of the output signal Eout becomes equal to or higher than that of the offset voltage Voffset in the steady state.

At a point of time P 31 , the state signal ST 1 output from the PWM control circuit PCa makes a transition to a high level (arrow A 31 ) in response to a falling edge of a clock pulse of the clock signal CLK. A state signal ST 3 makes a transition to a low level. Transition to a state ( 1 ) is performed and an operation cycle T is started.

Since the switch SWs illustrated in FIG. 10 becomes conductive in a period where the state signal ST 1 is a high level, the current sensing signal Vsense, to which the offset voltage Voffset is supplied, is input to the non-inverting input terminal of the comparator COMP (arrow A 32 ). The comparator COMP illustrated in FIG. 10 compares the current sensing signal Vsense to the output signal Eout. At a point of time P 32 , upon the current sensing signal Vsense reaching the output signal Eout, the comparator COMP outputs a pulse signal Vcomp at a high level. Since the flip-flop FF 2 illustrated in FIG. 10 is reset, the state signal ST 1 makes a transition to a low level (arrow A 33 ). A state signal ST 2 output from an AND circuit AD 1 makes a transition to a high level (arrow A 34 ) in response to the state signal ST 1 making the transition to a low level. The state ( 1 ) is switched to a state ( 2 ).

At a point of time P 33 after a time period t 3 off has elapsed from the point of time P 31 , the control signal CT 3 a output from the state ( 3 ) time control circuit TC 3 a makes a transition to a high level. The state signal ST 3 makes a transition to a high level and the state signal ST 2 makes a transition to a low level (arrow A 35 ) in response to a rising edge of the control signal CT 3 a . The state ( 2 ) is switched to a state ( 3 ).

The state ( 3 ) is maintained until a point of time P 34 at which a time period t 3 has elapsed. At the point of time P 34 , the state signal ST 1 makes the transition to a high level (arrow A 37 ) in response to a falling edge of the clock signal CLK. The state signal ST 3 makes the transition to a low level. The operation cycle T is terminated.

The time period t 3 may be obtained by means of Equation (3) based upon a relationship between an input voltage Vin and an output voltage Vout. The circuit in FIG. 11 determines the time period t 3 according to Equation (3).

FIG. 14 illustrates a correlation between the output signal Eout of an error amplifier ERA and the current Id induced to flow through the current conversion unit IT. The current Id is zero or close to zero in an area where the level of the output signal Eout is equal to or higher than that of the offset voltage Voffset. The current Id increases in response to a decrease in the output signal Eout in an area R 11 where the level of the output signal Eout is equal to or lower than that of the offset voltage Voffset.

At a point of time P 31 , data is fed into the flip-flop FF illustrated in FIG. 11 at the falling edge of the clock signal CLK, and the control signal CT 3 a makes a transition to a low level, thereby turning OFF a transistor M 1 . A current (Ic-Id) is stored in a capacitor C. Since the level of the output signal Eout is made equal to or higher than that of the offset voltage Voffset in the steady state of the output voltage Vout, the current Id is zero or close to zero and the current (Ic-Id) attains a maximum value. As a result, a rising gradient of a voltage V 2 reaches a maximum value. At a point of time P 33 , upon the voltage V 2 reaching an output voltage V 1 , the control signal CT 3 a makes the transition to a high level and the time period t 3 off is terminated. At a point of time P 34 , in response to the falling edge of the clock signal CLK, the control signal CT 3 a makes the transition to a low level and the time period t 3 is terminated. One operation cycle T is terminated.

If the output voltage Vout is in the steady state, the time period t 3 is defined as a fixed value and PWM control is performed in the state ( 1 ) and in the state ( 2 ). The other operations in the second embodiment are the same as those of the state ( 3 ) time control circuit TC 3 ( FIG. 2 ) in the first embodiment and detailed descriptions are reduced or omitted.

FIG. 13 illustrates a waveform diagram of the DC-DC converter 1 a in the transient response. The load suddenly decreases as shown in FIG. 13 . An output current Iout decreases, the output voltage Vout rises, and the output signal Eout drops. In FIG. 13 , the level of the output signal Eout drops to equal to or lower than that of the offset voltage Voffset.

The state signal ST 1 makes the transition to a high level in response to a falling edge of the clock pulse of the clock signal CLK at a point of time P 41 , thereby providing the transition to the state ( 1 ). The flip-flop FF ( FIG. 11 ) is set in response to the falling edge of the clock signal CLK, and the control signal CT 3 a makes the transition to a low level.

The time period t 1 of the state signal ST 1 is fixed at a minimum value determined based upon a minimum PWM width of the PWM control circuit PCa during the transient response. After a minimum time period t 1 _min has elapsed, the state signal ST 1 makes the transition to a low level and the state signal ST 2 makes the transition to a high level, and the state ( 1 ) is switched to the state ( 2 ).

In a point of time P 42 after the time period t 3 off has elapsed from the point of time P 41 , the control signal CT 3 a output from the state ( 3 ) time control circuit TC 3 a makes the transition to a high level, thereby switching the state ( 2 ) to the state ( 3 ). The state ( 3 ) is maintained until the point of time P 43 , at which the time period t 3 has elapsed.

At the point of time P 41 , the current (Ic-Id) is stored in the capacitor C and the voltage V 2 starts to rise. At the point of time P 42 , upon the voltage V 2 reaching the output voltage V 1 , the control signal CT 3 a makes the transition to a high level, and the state ( 2 ) makes the transition to the state ( 3 ) (arrow A 41 ). The time period t 3 of the state ( 3 ) is determined based upon the rising gradient of the voltage V 2 .

In the transient response of the output voltage Vout, the level of the output signal Eout is made equal to or lower than that of the offset voltage Voffset. The current Id increases in response to a decrease in amount of the output signal Eout from the offset voltage Voff set. Since the current (Ic-Id) decreases upon the increase in the current Id, the rising gradient of the voltage V 2 becomes less. The time period t 3 of the state ( 3 ) becomes shorter in response to the decrease in amount of the output signal Eout from the offset voltage Voffset. In the transient response of the output voltage Vout, the time period t 1 of the state ( 1 ) is defined as the fixed time. The time periods of state ( 2 ) and of the state ( 3 ) are PWM-controlled in response to the decrease in amount of the output signal Eout from the offset voltage Voffset.

In the DC-DC converter 1 a according to the second embodiment, the state ( 3 ) time control circuit TC 3 a detects a state where the level of the output signal Eout becomes equal to or lower than that of the offset voltage Voffset. The DC-DC converter 1 a makes the time period t 3 of the state ( 3 ) shorter in response to the decrease in amount of the output signal Eout from the offset voltage Voffset. The PWM control is performed in the state ( 2 ) and in the state ( 3 ) in the transient response since an ON-duty state during the time period t 2 of the state ( 2 ) is increased, greater energy is discharged to an output terminal Tout side owing to this, the inductor current IL quickly decreases.

In the DC-DC converter 1 a according to the second embodiment, in the steady state illustrated in FIG. 12 , the PWM control is performed in the state ( 1 ) and in the state ( 2 ) by fixing the time period t 3 . Since a period of the time period t 1 is set to a given value, efficiency may be improved. In the transient response in a sudden increase in load as illustrated in FIG. 13 , the PWM control is performed in the state ( 2 ) and in the state ( 3 ). Thus, an improvement of the efficiency in the steady state and a faster response speed in the transient response in the sudden increase in load may be achieved.

FIG. 15 illustrates a third embodiment. In the first and the second embodiments, the time period t 3 in the state ( 3 ) is defined as the fixed time. In the third embodiment, a time period t 1 in a state ( 1 ) is defined as a fixed time. In a step down DC-DC converter 1 b according to the third embodiment, speed of a transient response in a sudden increase in load is high.

A control circuit 11 b illustrated in FIG. 15 includes an error amplifier ERA, comparators COMP 1 and COMP 2 , a state ( 1 ) time control circuit TC 1 , a status control circuit SCb, an oscillator OSCb, a logic unit LCb, and resistor elements R 1 and R 2 . The logic unit LCb includes an AND circuit AD 4 , an OR circuit OR 1 , a NOR circuit NR 1 , and inverters INV 5 and INV 6 .

The oscillator OSCb outputs triangular waves W 1 and W 2 . An output signal Eout is input to a non-inverting input terminal of the comparator COMP 1 and the triangular wave W 1 is input to an inverting input terminal of the comparator COMP 1 . The output signal Eout is input to a non-inverting input terminal of the comparator COMP 2 and the triangular wave W 2 is input to an inverting input terminal of the comparator COMP 2 . An output signal Vc 1 output from the comparator COMP 1 is input to a state ( 1 ) time control circuit TC 1 , the AND circuit AD 4 , and the inverter INV 6 . An output of the state ( 1 ) time control circuit TC 1 is input via the inverter INV 5 to the AND circuit AD 4 . An output signal Vc 2 output from the comparator COMP 2 and an output from the AND circuit AD 4 are input to the OR circuit OR 1 . A state signal ST 1 output from the OR circuit OR 1 is input to the status control circuit SCb and the NOR circuit NR 1 . A state signal ST 2 output from the inverter INV 6 is input to the status control circuit SCb and the NOR circuit NR 1 . A state signal ST 3 output from the NOR circuit NR 1 is input to the status control circuit SCb. Other structural elements in the third embodiment are the same as those of the step up/step down DC-DC converter 1 ( FIG. 1 ) in the first embodiment and detailed descriptions are reduced or omitted.

FIG. 16 illustrates a waveform diagram of the DC-DC converter 1 b in a steady state. The two triangular waves W 1 and W 2 are generated so that a maximum value of the triangular wave W 1 and a minimum value W 2 of the triangular wave W 2 come in contact with each other at a threshold value voltage Vth. When the level of the output signal Eout is equal to or lower than that of the threshold value voltage Vth, the comparator COMP 1 compares the output signal Eout to the triangular wave W 1 . When the level of the output signal Eout is equal to or higher than that of the threshold value voltage Vth, the comparator COMP 2 compares the output signal Eout to the triangular wave W 2 .

If the output voltage Vout is in the steady state, the level of the output signal Eout becomes equal to or lower than that of the threshold value Vth. The comparator COMP 1 compares the output signal Eout and the triangular wave W 1 . In a time period t 2 where the level of the output signal Eout is higher than that of the triangular wave W 1 , an output signal Vc 1 becomes a low level and the state signal ST 2 at a high level (arrow A 51 ) is output from the inverter INV 6 . A transition to a state ( 2 ) is performed during the time period t 2 .

A delayed inverting signal Vc 1 i that is delayed by a given delay time DT with the state ( 1 ) time control circuit TC 1 is output from the inverter INV 6 . An AND output Va of the output signal Vc 1 and the delayed inverting signal Vc 1 i are output from the AND circuit AD 4 . The comparator COMP 2 does not make a comparison and maintains the output signal Vc 2 at a low level. The OR circuit OR 1 chooses the AND output Va from the AND output Va and the output signal Vc 2 to output as the state signal ST 1 . At a point of time P 52 , the state signal ST 3 output from the NOR circuit NR 1 makes a transition to a high level upon the state signal ST 1 making a transition to a low level. At a point of time P 53 , the state signal ST 2 makes the transition to a high level in response to a falling edge of the output signal Vc 1 and the state signal ST 3 makes a transition to a low level. The state ( 3 ) is terminated.

In the steady state, the time period t 1 of the state ( 1 ) is determined based upon the delay time DT, which may be a constant value, regardless of an operation cycle T and a relationship between an input voltage Vin and an output voltage Vout. Time periods of the state ( 2 ) and the state ( 3 ) are PWM-controlled based upon the triangular wave W 1 and the output signal Eout.

FIG. 17 illustrates a waveform diagram of the DC-DC converter 1 b in the transient response. The output voltage Vout suddenly decreases and the output signal Eout suddenly increases.

The level of output signal Eout becomes equal to or higher than that of the threshold value voltage vth in the transient response. The comparator COM 2 compares the output signal Eout and the triangular wave W 21 . In the time period t 1 where the output signal Eout is higher than the triangular wave W 2 , the output signal Vc 2 becomes a high level. The comparator COMP 1 does not make a comparison and the comparator COMP 1 maintains the output signal Vc 1 at a high level since the OR circuit OR 1 chooses the output signal Vc 2 to output as the state signal ST 1 , a transition to the state ( 1 ) is performed (arrow A 61 ). At a point of time P 61 , the state signal ST 3 output from the NOR circuit NR 1 makes the transition to a high level upon the state signal ST 1 making the transition to a low level. A transition to the state ( 3 ) is performed. At a point of time P 62 , the state signal ST 1 makes a transition to a high level in response to a rising edge of the output signal Vc 2 and the state signal ST 3 makes the transition to a low level. The state ( 3 ) is switched to the state ( 1 ).

The transition to the state ( 2 ) is not performed in the transient response. Time periods of the state ( 1 ) and the state ( 3 ) are PWM-controlled based upon on the triangular wave W 2 and the output signal Eout.

In the DC-DC converter 1 b according to the third embodiment, the time period t 1 is defined as a fixed period and the PWM control is performed in the state ( 2 ) and in the state ( 3 ) during the steady state. Since the waveforms as illustrated in FIGS. 6A to 6C are achieved, efficiency may be improved. In the DC-DC converter 1 b , the transition to the state ( 2 ) is not performed in the transient response in a sudden increase in load and the PWM control is performed in the state ( 1 ) and in the state ( 3 ). Since the time period of the state ( 1 ) is made longer in response to load states, speed in the transient response may be improved. In the steady state, the PWM control is performed in the state ( 1 ) and in the state ( 2 ). On the other hand, the PWM control is performed in the state ( 1 ) and in the state ( 3 ) in the transient response. As a result, an improvement of the efficiency in the steady state and a faster response speed in the transient response in the sudden increase in load may be achieved.

Since the input voltage vin and the output voltage Vout are close to one another in the above embodiments, a gradient of a current sensing signal Vs in the state ( 3 ) is substantially zero or close to zero. However, the present embodiments are not limited. The present embodiments are applicable to any case where the input voltage Vin is higher than the output voltage Vout or where the input voltage Vin is lower than the output voltage Vout.

A compensation signal may be added to a current sensing signal Vsense and the output signal Eout to achieve stabilized control.

The transistors FET 2 and FET 4 are used as synchronous rectifying elements in the embodiments. However, a diode element that performs rectification may also be used. For example, at least one of the transistors FET 2 and FET 4 may be replaced with the diode. It is also possible to provide diodes arranged in parallel to at least one of the transistors FET 2 and FET 4 .

Although the transistors FET 1 , FET 2 , FET 3 , and FET 4 are N-type FET, any of the transistors FET 1 , FET 2 , FET 3 , and FET 4 or all of the transistors FET 1 to FET 4 may be replaced with a P-type transistor.

Although the inductor current IL induced to flow through the choke coil L 1 is detected in the above embodiments, it is possible that a current, which is induced to flow through either the transistor FET 1 or the transistor FET 3 , or both transistors, may be detected.

The control circuits 11 , 11 a , and 11 b in the embodiments may be formed as a single semiconductor chip or as a plurality of semiconductor chips. Alternatively, the DC-DC converter may be formed as a single semiconductor chip, as a plurality of semiconductor chips, or as a module.

Example embodiments of the present invention have now been described in accordance with the above advantages. It will be appreciated that these examples are merely illustrative of the invention. Many variations and modifications will be apparent to those skilled in the art.