Oscillator and driving circuit and oscillation method thereof

This application claims the priority benefit of Taiwan application serial no. 97135244, filed on Sep. 12, 2008. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

1. Field of the Invention

The present invention relates to an oscillator. More particularly, the present invention relates to an oscillator, a driving circuit and an oscillation method thereof, which can avoid loading noise of different frequency bands into a clock signal.

2. Description of Related Art

With development of technology, electronic products are continually innovated. Normal operation of the electronic product depends on an oscillator providing clocks. Based on the precise clock generated by the oscillator, internal chips of the electronic product can sequentially process received data or signals and transmit the processed data or signal to a next stage circuit at a correct time. A quartz oscillator can not only provide the precise clock, but also has a feature of not being influenced by factors such as temperature, humidity, fabrication process and operation voltage, etc. Therefore, the quartz oscillators are applied to most of the electronic products for providing the required clock.

FIG. 1 is a circuit diagram of a conventional oscillator. Referring to FIG. 1 , the oscillator 100 includes a crystal 101 , an inverter 102 , a resistor R and a capacitor C. Since a mechanical-electrical resonance of the crystal 101 is quite stable, the oscillator 100 can output a relatively stable clock signal based on the above characteristic of the crystal 101 . However, whether oscillation of the oscillator can be started is influenced by a quality of the crystal 101 , and a waveform of a clock signal Xtal_out generated after the oscillation is also influenced by a quality of the crystal 101 .

Generally, when a designer designs the oscillator 100 , the quality of the crystal 101 cannot be known in advance. To eliminate a possibility that the oscillation of the oscillator 100 cannot be started due to a quality difference of the crystal 101 , the inverter 102 with relatively great amplification is generally applied to the oscillator 100 for actuating the oscillation starting of the oscillator 100 .

However, the inverter 102 with the relatively great amplification can also amplify amplitude of the clock signal Xtal_out generated after the oscillation starting of the crystal 101 , which may lead to a full swing of the waveform thereof. Such full swing waveform is liable to be loaded with noises of different frequency bands, which can lead to instability of the waveform of the clock signal Xtal_out, and can influence a frequency of the clock signal Xtal_out.

For the oscillator, an optimal oscillation waveform is a sine waveform, which is not liable to be loaded with noises of different frequency bands, and the frequency of the provided clock signal is the most stable. However, for the oscillator applying the inverter with the relatively great amplification, due to the influence of the full swing waveform, if the quality of the utilized crystal is poor, the noises of different frequency bands generated by the crystal can be amplified, so that the waveform and frequency of the clock signal of the oscillator are influenced.

The present invention is directed to a driving circuit, which can control a gain of a buffer according to a voltage level of a clock signal or an oscillation signal.

The present invention is directed to an oscillator, which can avoid loading noise of different frequency bands into a clock signal.

The present invention is directed to an oscillation method, by which after oscillation of a clock signal is stable, a gain of a buffer is decreased, so as to avoid excessive amplification of noises generated by a crystal.

The principle aspect of the present invention provides a driving circuit suitable for being coupled in parallel to a crystal to generate a clock signal. The driving circuit includes a buffer unit and a control unit. The buffer unit is coupled in parallel to the crystal, and used to amplify an oscillation signal outputted from the crystal to generate the clock signal. The control unit is coupled to the buffer unit, and used to generate a control signal to the buffer unit. The control unit determines a voltage level of the control signal by detecting whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal, so as to control a gain of the buffer unit.

Another aspect of the present invention provides an oscillator including a crystal and a driving circuit, and wherein the driving circuit includes a buffer unit and a control unit. The driving circuit is coupled in parallel to the crystal, and used to generate a clock signal. The buffer unit is coupled in parallel to the crystal, and used to amplify an oscillation signal outputted from the crystal to generate the clock signal. The control unit is coupled to the buffer unit, and used to generate a control signal to the buffer unit. The control unit determines a voltage level of the control signal by detecting whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal, so as to control a gain of the buffer unit.

Additional aspect of the present invention also provides an oscillation method for driving an oscillator having a crystal, so as to generate a clock signal. The method can be described as follows. First, an oscillation signal output from the crystal is amplified to generate the clock signal. Next, whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal is detected. Finally, an amplification gain of the oscillation signal is controlled according to a detecting result, and wherein the detecting result represents whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal.

According to the oscillator and driving circuit and oscillation method of the present invention, whether the crystal is stably oscillated is confirmed by detecting the clock signal or the oscillation signal, and after the oscillation is stable, an amplification gain of the clock signal is reduced so as to avoid excessive amplification of the noise generated by the crystal. By such means, noise of different frequency bands loaded into the clock signal can be avoided, so as to improve a stability of the frequency of the clock signal.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred exemplary embodiment accompanied with figures is described in detail below.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a circuit diagram of a conventional oscillator.

FIG. 2A is a system block diagram illustrating an oscillator according to an exemplary embodiment of the present invention.

FIG. 2B is a circuit diagram illustrating an oscillator of FIG. 2A .

FIG. 2C is a waveform diagram of a system voltage, a trigger signal, a reset signal, a control signal, an oscillation signal and a clock signal of FIG. 2B .

FIG. 3A is a system block diagram illustrating an oscillator according to another exemplary embodiment of the present invention.

FIG. 3B is a circuit diagram illustrating an oscillator of FIG. 3A .

FIG. 3C is a waveform diagram of a system voltage, a detecting signal, a control signal, an oscillation signal and a clock signal of FIG. 3B .

FIG. 4 is an application schematic diagram according to an exemplary embodiment of the present invention.

FIG. 5 is a flowchart illustrating an oscillation method according to an exemplary embodiment of the present invention.

FIG. 6 is a flowchart of an oscillation method according to another exemplary embodiment of the present invention.

FIG. 7 is a flowchart of an oscillation method according to still another exemplary embodiment of the present invention.

To avoid influences on frequency and waveform of a clock signal caused by an oscillator applying the poor quality crystal, the present invention provides an oscillator and a driving circuit and an oscillation method thereof to reduce an amplification gain of the oscillation signal, so as to mitigate the influence caused by the poor quality crystal. To fully convey the spirit of the present invention, exemplary embodiments are provided bellow for detailed description.

FIG. 2A is a system block diagram illustrating an oscillator according to an exemplary embodiment of the present invention. Referring to FIG. 2A , the oscillator 200 includes a crystal X 1 , a driving circuit 210 , capacitors C 1 and C 2 , and a resistor R 1 . The driving circuit 210 is coupled in parallel to the crystal X 1 . The capacitor C 1 is coupled between one terminal of the crystal X 1 and a ground voltage. The capacitor C 2 is coupled between another terminal of the crystal X 1 and the ground voltage. The resistor R 1 is coupled in parallel to a buffer unit 211 . The buffer unit 211 is coupled in parallel to the crystal X 1 . The buffer unit 211 is used to amplify an oscillation signal S OSC output from the crystal X 1 , and to output the amplified signal as a clock signal S CLK . The capacitor C 2 filters a noise of the oscillation signal S OSC , and the capacitor C 1 and the resistor R 1 modify a waveform of the clock signal S CLK according to electrical characteristics thereof, so as to trim the waveform of the clock signal S CLK to close to a sine waveform. Meanwhile, the resistor R 1 determines a direct current (DC) voltage level of the control signal. Then, the crystal X 1 again converts the clock signal S CLK into the oscillation signal S OSC , and the converted oscillation signal S OSC is again amplified by the buffer unit 211 to generate the clock signal S CLK , so as to oscillate the oscillator.

The control unit 212 is coupled to the buffer unit 211 , and generates a control signal S COL to the buffer unit 211 . The control unit 212 determines a voltage level of the control signal S COL by detecting whether the clock signal S CLK or the oscillation signal S OSC satisfies an oscillation condition of the crystal X 1 . An amplification gain of the buffer unit 211 is controlled according to the voltage level of the control signal S COL . The oscillation condition is for example a condition that amplitude of the oscillation signal S OSC is greater than a predetermined value, or amplitude of the clock signal S CLK is greater than the predetermined value. Wherein the predetermined value can be set to amplitude that is great enough to drive the control unit 211 to switch the voltage level of the control signal S COL , and the predetermined value can be designed by those skilled in the art.

For example, when the oscillator 200 is just powered, the amplitude of the oscillation signal S OSC is about zero, and since the buffer unit 211 can inversely amplify the amplitude of the oscillation signal S OSC , oscillation of the oscillator 200 is started, and the amplitude of the oscillation signal S OSC is gradually increased. To quickly start the oscillation of the oscillator 200 , during starting of the oscillation, the buffer unit 211 applies a relatively great gain. Here, assuming a maximum gain of the buffer unit 211 is 10, and the maximum gain can be varied according to actual requirements. Before the amplitude of the oscillation signal S OSC reaches the predetermined value, it represents that the oscillator 200 is not stably oscillated. Now, the oscillator 200 still requires the relatively great gain to accelerate the oscillation starting of the crystal X 1 , and the control unit 212 can output the control signal S COL having a logic high voltage level (for example, a system voltage VCC). When the buffer unit 211 receives the control signal S COL having the logic high voltage level, it represents that the oscillator 200 still requires the relatively great gain, so that the buffer unit 211 can adjust the gain thereof to be 10.

After the oscillation is started for a while, the amplitude of the oscillation signal S OSC can be greater than the predetermined value, which represents that the oscillation of the crystal X 1 is stable. Now, the oscillator 200 only requires a low gain to maintain the oscillation, so that the control unit can output the control signal S COL having a logic low voltage level (for example, the ground voltage). When the buffer unit 211 receives the control signal S COL having the logic low voltage level, it represents that the oscillator 200 does not require the relatively great gain, so that the buffer unit 211 can adjust the gain thereof to a lower value (for example, to be 1) for providing to the oscillator 200 to maintain the oscillation. By such means, after the oscillation of the oscillator 200 is stable, excessive amplification of the noise of different frequency bands generated by the crystal X 1 can be avoided, so as to avoid loading the noise into the clock signal S CLK .

Moreover, it should be noted that in the aforementioned exemplary embodiment, though it is assumed that the gain of the buffer unit 211 is 10 when the oscillation of the oscillator 200 is just started, and after the oscillation of the oscillator 200 is stable, the gain of the buffer unit 211 is 1, it is only an exemplary embodiment, and those skilled in the art can design the gain of the buffer unit 211 when the oscillation of the oscillator 200 is just started, and the gain of the buffer unit 211 after the oscillation of the oscillator 200 is stable according to the spirit of the present invention. Moreover, in the aforementioned exemplary embodiment, though it is assumed that when the buffer unit 211 receives the control signal S COL having the logic high voltage level, it represents that the oscillator 200 still requires the relatively great gain, it is only an exemplary embodiment, and those skilled in the art can design a signal meaning of the control signal S COL according to the spirit of the present invention.

In the following content, another exemplary embodiment is provided for those skilled in the art to fully convey the spirit of the present invention. FIG. 2B is a circuit diagram illustrating an oscillator of FIG. 2A . Referring to FIG. 2A and FIG. 2B , in the present exemplary embodiment, the buffer unit 211 includes a first driving device 211 a and a second driving device 211 b . The first and second driving devices 211 a and 211 b are for example, NAND gates. However, those skilled in the art should understand that OR gates (with input terminals coupling NOT gates) or other logic circuits equivalent to the NAND gate can also be applied. For simplicity's sake, a gain of the second NAND gate 211 b is set to 1, and a gain of the first NAND gate 211 a is greater than that of the second NAND gate 211 b . Here, the gain of the first NAND gate 211 a is set to 10, and the gains of the NAND gates 211 a and 211 b can be varied according to a design requirement. The control unit 212 includes a first latch module 212 a and a detecting module 212 d . The detecting module 212 d includes a first trigger 212 b , a second trigger 212 c , a first transistor M 1 , a second transistor M 2 and a resistor R 2 . Wherein the first latch module 212 a is a D-type latch, the first transistor M 1 and the second transistor M 2 are respectively a PMOS transistor and a NMOS transistor, and the first trigger 212 b and the second trigger 212 c are for example, Schmitt triggers.

The first trigger 212 b has a first terminal and a second terminal. Wherein the first terminal of the first trigger 212 b is coupled to the crystal X 1 , and the second terminal of the first trigger 212 b is coupled to a trigger terminal CK of the latch 212 a . A first terminal of the resistor R 2 is coupled to the system voltage VCC, and a second terminal thereof is coupled to a source of the first transistor M 1 . A drain of the first transistor M 1 is coupled to a first terminal of the second trigger 212 c , and a gate of the first transistor M 1 is coupled to the second terminal of the first trigger 212 b . A drain of the second transistor M 2 is coupled to the first terminal of the second trigger 212 c , a source of the second transistor M 2 is coupled to the ground voltage, and a gate of the second transistor M 2 is coupled to the second terminal of the first trigger 212 a.

The latch 212 a has an input terminal D, an inverting output terminal Q , the trigger terminal CK and a reset terminal RS. Wherein the input terminal D is coupled to the system voltage VCC, and the trigger terminal CK is coupled to the second terminal of the first trigger 212 b . The trigger terminal CK receives a trigger signal S TRI , and the reset terminal RS is coupled to the second terminal of the second trigger 212 c . The reset terminal RS receives a reset signal S RS . The first NAND gate 211 a has a first terminal, a second terminal and an output terminal, and wherein the first terminal thereof is coupled to the inverting output terminal Q of the first latch 212 a . The first terminal of the first NAND gate 221 a receives the control signal S COL , and the second terminal and the output terminal of the first terminal of the first NAND gate 221 a are coupled to the crystal X 1 in parallel. The second NAND gate 211 b has a first terminal, a second terminal and an output terminal. Wherein the first terminal of the second NAND gate 211 b is coupled to the system voltage VCC, and the second terminal and the output terminal of the second NAND gate 211 b are coupled to the crystal X 1 in parallel.

FIG. 2C is a waveform diagram of the system voltage VCC, the trigger signal S TRI , the reset signal S RS , the control signal S COL , the oscillation signal S OSC and the clock signal S CLK of FIG. 2B . Referring to FIGS. 2B and 2C , as the system voltage VCC increases, internal components of the oscillator 200 may also generate voltages corresponding to the voltage level of the system voltage VCC, and the triggers 212 b and 212 c are preset to output the logic low voltage level. When the system voltage VCC is stable, the internal components of the oscillator 200 can operate normally. Now, since the trigger 212 c is preset to output the logic low voltage level (i.e. the reset signal S RS ), the latch 212 a is in a reset state, namely, the output terminal Q of the latch 212 a outputs the logic low voltage level, and the inverting output terminal Q of the latch 212 a outputs the logic high voltage level (i.e. the control signal S COL ).

In the buffer unit 211 , the first terminal of the NAND gate 211 a now receives the control signal S COL having the logic high voltage level, so that the NAND gate 211 a inversely amplifies the oscillation signal S OSC received from the second terminal thereof. Since the first terminal of the NAND gate 211 b is coupled to the system voltage VCC (the logic high voltage level), the NAND gate 211 b inversely amplifies the oscillation signal S OSC received from the second terminal thereof. Now, the NAND gates 211 a and 211 b of the buffer unit 211 both inversely amplify the oscillation signal S OSC , so that an amplification gain of the buffer unit 211 equals a sum of the gain of the NAND gate 211 a and the gain of the NAND gate 211 b (i.e. the gain is 11). By amplifying the oscillation signal S OSC , the oscillation starting of the crystal X 1 can be accelerated.

Next, though the amplification gain of the buffer unit 211 is 11, since the amplitude of the oscillation signal S OSC at the beginning is almost zero, the amplitudes of the oscillation signal S OSC and the clock signal S CLK at the beginning are relatively small. After multi resonance of the crystal X 1 and multi amplifications of the buffer unit 211 , the amplitudes are gradually amplified. When the amplitude of the oscillation signal S OSC is amplified to a degree that a peak and a trough voltage levels are great enough to drive the trigger 212 b to change the voltage level of the output signal thereof, the trigger 212 b can generate the trigger signal S TRI with a narrow square waveform or a pulse waveform in response to the oscillation signal S OSC . Now the amplitude of the oscillation signal S OSC is great enough to drive the trigger 212 b to change the voltage level of the trigger signal S TRI , and meanwhile the trigger 212 c is indirectly triggered to switch the voltage level of the output reset signal S RS . In the case, the current clock signal S CLK or the oscillation signal S OSC satisfies the oscillation condition of the crystal X 1 .

Referring to the trigger signal S TRI and the reset signal S RS of FIG. 2B and FIG. 2C , when the level of the trigger signal S TRI is a logic high voltage level H 1 , since the transistor M 1 can be turned on in response to the logic low voltage level, and the transistor M 2 can be turned on in response to the logic high voltage level, the transistor M 2 is now turned on, so that the ground voltage is transmitted to the trigger 212 c . Since the trigger 212 c is preset to output the logic low voltage level, the voltage level of the reset signal S RS is the logic low voltage level before the trigger 212 c receives the ground voltage. After the ground voltage is received, the trigger 212 c switches the voltage level of the reset signal S RS to the logic high voltage level, and a waveform thereof is shown as the reset signal S RS in FIG. 2C . Moreover, in FIG. 2C , a time delay is generated when the reset signal S RS is changed from the logic low voltage level to the logic high voltage level. This is because that the transistor M 2 is switched when the transistor M 1 is turned on, and after the trigger signal S TRI switches the voltage level, the transistor M 1 is turned off and the transistor M 2 is turned on for discharging. Therefore, when the voltage level of a connecting terminal between the transistor M 2 and the transistor M 1 is decreased enough via the discharging that can drive the trigger 212 c to switch the voltage level (for example, the ground voltage) of the output reset signal S RS , the voltage level of the control signal S COL is switched to the logic low voltage level.

Next, referring to the trigger signal S TRI , the voltage level thereof is changed from the logic high voltage level to a logic low voltage level L 1 . Now, the transistor is turned on in response to the logic low voltage level, so that the system voltage VCC is transmitted to the trigger 212 c via the resistor R 2 . However, since the resistor R 2 generates a voltage drop, the voltage level transmitted to the trigger 212 c is not great enough to drive the trigger 212 c to switch the voltage level of the reset signal S RS . After the voltage level of the reset signal S RS is switched to the logic high voltage level in response to the logic high voltage level of the trigger signal S TRI , the logic high voltage level of the trigger signal S TRI then cannot again changes the voltage level of the reset signal S RS , so that the voltage level of the reset signal S RS is maintained to the logic high voltage level.

Referring to the trigger signal S TRI and the reset signal S RS of FIG. 2B and FIG. 2C again, the pulse waveform of the trigger signal S TRI can be transmitted to the latch 212 a , so as to trigger the latch 212 a to transmit the system voltage VCC received from the input terminal D thereof to the output terminal Q. Before the voltage level of the reset signal S RS is switched to the logic high voltage level, since the reset signal S RS has the logic low voltage level, the latch 212 a is in the reset state, so that the output terminal Q of the latch 212 a outputs the logic low voltage level, and the inverting output terminal Q outputs the logic high voltage level. When the voltage level of the reset signal S RS is switched to the logic high voltage level, if the trigger signal S TRI triggers the latch 212 a , the latch 212 a then transmits the system voltage VCC received from the input terminal D to the output terminal Q, so that the output terminal Q of the latch 212 a outputs the system voltage VCC (the system voltage VCC can be regarded as the logic high voltage level), and the inverting output terminal Q of the latch 212 a outputs the logic low voltage level (i.e. the control signal S COL is at the logic low voltage level).

When the control signal S COL having the logic low voltage level is transmitted to the first terminal of the NAND gate 211 a , the output terminal of the NAND gate 211 a is in a floating state, i.e. the NAND gate 211 a is disconnected from the clock signal S CLK , so that the NAND gate 211 a cannot inversely amplify the oscillation signal S OSC . Now, in the buffer unit 211 , only the NAND gate 211 b functions, and the gain of the buffer unit 211 is changed to 1. By such means, the noise generated due to excessive amplification of the signal or the poor quality of the crystal X 1 can be avoided, so as to avoid influence of the frequency and waveform of the clock signal S CLK due to the noise of different frequency bands loaded into the clock signal S CLK .

In other exemplary embodiments of the present invention, the buffer unit 211 of the oscillator 200 can only utilize the NAND gate 211 a to inversely amplify the oscillation signal S OSC when the oscillation of the oscillator is started, and after the oscillation is stable, the NAND gate 211 b is switched to inversely amplify the oscillation signal S OSC . Certainly, in such other exemplary embodiments, the gain of the buffer unit 211 can also be controlled by determining whether the oscillation is stable.

Moreover, since before the system voltage VCC is stable, the circuit operation thereof is not stable either. If the circuit design is poor, the oscillator can be influenced. Therefore, a power-detecting unit can be applied to control the buffer unit to start operation after the system voltage VCC is stable. FIG. 3A is a system block diagram illustrating an oscillator according to another exemplary embodiment of the present invention. Referring to FIG. 2A and FIG. 3A , the greatest difference therebetween is a power-detecting unit 313 within the oscillator 300 . Operations of a buffer unit 311 and a control unit 312 are similar to that of the buffer unit 211 and the control unit 212 within the oscillator 200 , and therefore detailed descriptions thereof are not repeated.

The power-detecting unit 313 is coupled to the buffer unit 311 . The power-detecting unit 313 is used to output a detecting signal S DT to the buffer unit 311 , and to determine a voltage level of the detecting signal S DT according to whether the system voltage VCC is stable, so as to control the buffer unit 311 whether to amplify the oscillation signal S OSC . Wherein, whether the system voltage VCC is stable can be judged according to whether the system voltage VCC reaches a predetermined value. For example, when the system voltage VCC is not stable, the power-detecting unit 313 transmits the detecting signal S DT having the logic low voltage level to the buffer unit 311 . When the buffer unit 311 receives the detecting signal S DT having the logic low voltage level, the buffer unit 311 does not amplify the oscillation signal S OSC . Conversely, when the system voltage VCC is stable, the power-detecting unit 313 transmits the detecting signal S DT having the logic high voltage level to the buffer unit 311 . When the buffer unit 311 receives the detecting signal S DT having the logic high voltage level, the buffer unit 311 amplifies the oscillation signal S OSC . By such means, operation of the oscillator under unstable system voltage VCC can be avoided, so as to accelerate an oscillation starting speed of the oscillator 300 .

In the following content, another exemplary embodiment is provided to describe the oscillator 300 in detail. FIG. 3B is a circuit diagram illustrating an oscillator of FIG. 3A . Referring to FIG. 3A and FIG. 3B , in the present exemplary embodiment, the buffer unit 311 includes a third driving device 311 a and a fourth driving device 311 b , and wherein the third and fourth driving devices 311 a and 311 b are for example, NAND gates. The control unit 312 includes a second latch module 312 a and a third trigger 312 b . The second latch module 312 a is for example, a D-type latch, and the third trigger 312 b is for example a Schmitt inverting trigger. The power-detecting unit can be implemented by a plurality of approaches, for example, implemented by a Schmitt trigger or other approaches known by those skilled in the art. For simplicity's sake, the gain of the NAND gate 311 b is for example 1, and the gain of the NAND gate 311 a is greater than that of the NAND gate 311 b . Here, the gain of the NAND gate 311 a is for example 10.

An input terminal D of the latch 312 a is coupled to the system voltage VCC, and an trigger terminal CK of the latch 312 a is coupled to the trigger 312 b . The trigger terminal CK of the latch 312 a receives the trigger signal S TRI . A reset terminal RS of the latch 312 a is coupled to the power-detecting unit 313 , and the reset terminal RS of the latch 312 a receives the detecting signal S DT . An inverting output terminal Q of the latch 312 a is coupled to the NAND gate 311 a , and the inverting output terminal Q of the latch 312 a outputs the control signal S COL to the NAND gate 311 a . A first terminal of the trigger 312 b is coupled to the crystal X 1 , and receives the oscillation signal S OSC . A second terminal of the trigger 312 b is coupled to the trigger terminal CK of the latch 312 a , and provides the trigger signal S TRI . The NAND gate 311 a has a first terminal, a second terminal, a third terminal and an output terminal. Wherein the first terminal of the NAND gate 311 a is coupled to the inverting output terminal Q of the latch 312 a , and receives the control signal S COL . The second terminal of the NAND gate 311 a is coupled to the power-detecting unit 312 , and receives the detecting signal S DT . The third terminal and the output terminal of the NAND gate 311 a are coupled in parallel to the crystal X 1 . The second NAND gate 311 b has a first terminal, a second terminal, a third terminal and an output terminal. Wherein the first terminal of the second NAND gate 311 b is coupled to the system voltage VCC. The second terminal of the second NAND gate 311 b is coupled to the detecting unit 313 , and receives the detecting signal S DT . The third terminal and the output terminal of the second NAND gate 311 b are coupled in parallel to the crystal X 1 .

FIG. 3C is a waveform diagram of the system voltage VCC, the detecting signal S DT , the control signal S COL , the oscillation signal S OSC and the clock signal S CLK of FIG. 3B . Referring FIG. 3B and FIG. 3C , in the present exemplary embodiment, the power-detecting unit 313 first detects whether the system voltage VCC is stable. If the system voltage VCC is not stable, the voltage level of the detecting signal S DT is the logic low voltage level. The latch 312 a can be reset in response to the detecting signal S DT having the logic low voltage level, so that the control signal S COL output from the inverting output terminal Q of the latch 312 a has the logic high voltage level. Similarly, the NAND gates 311 a and 311 b can also receive the detecting signal S DT having the logic low voltage level, and the detecting signal S DT having the logic low voltage level switches the output terminals of the NAND gates 311 a and 311 b in the floating state, so that the NAND gates 311 a and 311 b cannot inversely amplify the oscillation signal S OSC . As shown in FIG. 3C , as the system voltage VCC increases, voltage levels of the control signal S COL , the oscillation signal S OSC and the clock signal S CLK may correspond to the voltage level of the system voltage VCC.

Next, when the system voltage VCC is stable, the power-detecting unit 313 outputs the detecting signal S DT having the logic high voltage level. Now, the latch 312 a is not in the reset state. Since the oscillation signal S OSC cannot drive the trigger 312 b to switch the voltage level of the trigger signal S TRI , namely, the system voltage VCC received by the input terminal D of the latch 312 a cannot be transmitted to the output terminal Q, the inverting output terminal Q of the latch 312 a can maintain the original logic high voltage level to serve as the voltage level of the control signal S COL . When the NAND gates 311 a and 311 b receive the detecting signal S DT having the logic high voltage level, the NAND gate 311 b starts to inversely amplify the oscillation signal S OSC . Then, if the control signal S COL having the logic high voltage level is transmitted to the NAND gate 311 a , the NAND gate 311 a starts to amplify the oscillation signal S OSC . Now, the buffer unit 311 starts to amplify the oscillation signal S OSC for starting the oscillation of the oscillator 300 , and now the gain of the buffer unit 311 equals to a sum of the gains of the NAND gates 311 a and 311 b , i.e. the gain of the buffer unit 311 is 11.

Referring to FIG. 3C again, when the oscillation of the oscillator is started, the oscillation signal S OSC and the clock signal S CLK are also from none to some, and amplitudes thereof are gradually increased until a full swing amplitude. Referring to FIG. 3B , when the amplitude of the oscillation signal S OSC is great enough to drive the trigger 312 b to switch the voltage level of the trigger signal S TRI , the voltage level of the trigger signal S TRI is switched from the logic low voltage level to the logic high voltage level, and such switch operation triggers the latch 312 a to transmits the system voltage VCC (regarded to be the logic high voltage level) to the output terminal Q. Meanwhile, the inverting output terminal Q of the latch 312 a outputs the logic low voltage level to serve as the voltage level of the control signal S COL . When the first terminal of the NAND gate 311 a receives the control signal S COL having the logic low voltage level, the output terminal of the NAND gate 311 a is in the floating state, so that the NAND gate 311 a cannot inversely amplify the oscillation signal S OSC . Now, in the buffer unit 311 , only the NAND gate 311 b functions, i.e. the gain of the buffer unit 311 is changed to 1.

Components of the aforementioned exemplary embodiment can be integrated into a chip. FIG. 4 is an application schematic diagram according to an exemplary embodiment of the present invention. Referring to FIG. 4 , FIG. 4 is a block diagram of a chip 400 , and the buffer unit, the control unit, the resistor and even the power-detecting unit of the aforementioned exemplary embodiment can all be integrated into a block 410 . Furthermore, pins Xin and Xout are coupled to two ends of the crystal, and are respectively coupled to the capacitors C 1 and C 2 . The clock signal S CLK generated by the oscillator is provided to a physical layer block of the chip 400 , so as to operate the chip 400 normally.

According to another aspect, an oscillation method is provided based on the aforementioned exemplary embodiments. In the following content, another exemplary embodiment is provided for describing the oscillation method of the present invention. FIG. 5 is a flowchart illustrating an oscillation method according to an exemplary embodiment of the present invention. Referring to FIG. 5 , the oscillation method of the present exemplary embodiment can be applied to the oscillator of FIG. 2A . First, in step S 501 , the oscillation signal output from the crystal is amplified to generate the clock signal, and now an amplification gain of the oscillation signal is a high amplification gain (for example, a amplification gain is 10). Next, in step S 502 , whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal is detected. Finally, in step S 503 , the amplification gain of the oscillation signal is controlled according to the detecting result, and wherein the detecting result represents whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal.

For example, if none of the clock signal and the oscillation signal satisfies the oscillation condition of the crystal, the amplification gain of the oscillation signal is not varied (i.e. the amplification gain is 10). Conversely, if the clock signal or the oscillation signal satisfies the oscillation condition of the crystal, the amplification gain of the oscillation signal is then decreased (for example, the amplification gain is 1). Therefore, before the oscillation of the crystal is stable, the high amplification gain is applied to amplify the oscillation signal, so as to accelerate oscillation starting of the crystal. After the oscillation of the crystal is stable, the low amplification gain is applied to amplify the oscillation signal, so as to avoid noises generated due to excessive amplification of the signal and the poor quality of the crystal. Applying the low amplification gain to amplify the oscillation signal is continually performed after the oscillation of the crystal is stable, and such continuous amplification of the oscillation signal corresponds to a stable oscillation waveform of the oscillation signal S OSC of FIG. 2C .

Further, another oscillation method is provided for describing an actual operating method of the exemplary embodiment of FIG. 5 , and such oscillation method can be applied to the exemplary embodiment of FIG. 2B . FIG. 6 is a flowchart of an oscillation method according to another exemplary embodiment of the present invention. Referring to FIG. 6 , in step S 601 , the oscillation signal output from the crystal is amplified to generate the clock signal, and now the amplification gain of the oscillation signal is for example 10. Next, in step S 602 , amplitude of the oscillation signal is detected. Next, in step S 603 , whether the amplitude of the oscillation signal is greater than a predetermined value is judged. Wherein the predetermined value is for example one half of a full swing amplitude of the clock signal S CLK , and the predetermined value can be adjusted according to actual requirements. If a judgement result of the step S 603 is “negative”, namely, the amplitude of the oscillation signal is not greater than the predetermine value, the step S 602 is then repeated for continuously detecting the amplitude of the oscillation signal. When the amplitude of the oscillation signal is greater than the predetermined value, the judgement result of the step S 603 is “affirmative”, and then step S 604 is executed for decreasing the amplification gain of the oscillation signal, for example, the amplification gain is decreased to 1.

For the exemplary embodiment of FIG. 5 , the amplitude of the clock signal can be detected, or the clock signal and the oscillation signal can be simultaneously detected for confirming whether the oscillation of the crystal is stable, so as to control the amplification gain of the oscillation signal.

Moreover, an oscillation method that can detect the system voltage is further provided based on the oscillator 300 . FIG. 7 is a flowchart of an oscillation method according to still another exemplary embodiment of the present invention. Referring to FIG. 7 , in step S 701 , the system voltage is detected. Next, in step S 702 , whether the system voltage is stable is judged. If the system voltage is not stable, a judgement result of the step S 702 is then “negative”, and step S 703 is executed, by which the oscillation signal is not amplified. Then, the step S 701 is repeated for continuously detecting the system voltage. Before the system voltage is stable, the steps S 701 -S 703 are continuously repeated. When the system voltage is stable, the judgement result of the step S 702 is then “affirmative”, and step S 704 is executed for amplifying the oscillation signal. Here, the amplification gain of the oscillation signal is for example 10. Thereafter, amplification of the oscillation signal is continuously performed. Next, in step S 705 , the amplitude of the oscillation signal is detected. Next, in step S 706 , whether the amplitude of the oscillation signal is greater than the predetermined value is judged, wherein the predetermined value is for example one half of a full swing amplitude of the clock signal. If a judgement result of the step S 706 is “negative”, namely, the amplitude of the oscillation signal is not greater than the predetermine value, the step S 705 is then repeated for continuously detecting the amplitude of the oscillation signal. When the amplitude of the oscillation signal is greater than the predetermined value, the judgement result of the step S 706 is “affirmative”, and step S 707 is executed for decreasing the amplification gain of the oscillation signal, for example, the amplification gain is decreased to 1. Moreover, it should be noted that the method can be implemented by a software, a firmware, or a hardware.

In summary, according to the oscillator, and the driving circuit and the oscillation method thereof of the present invention, whether the system voltage is stable is detected first, so as to determine whether to amplify the oscillation signal. When the system voltage is stable, the oscillation signal is amplified to accelerate the oscillation starting of the crystal. Next, whether the oscillation of the crystal is stable is determined by detecting the clock signal or the oscillation signal, and after the oscillation is stable, the amplification gain of the oscillation signal is decreased to avoid excessive amplification of the noise generated by the crystal. By such means, oscillation starting speed of the crystal can be accelerated, and excessive amplification of the noise generated by the crystal can be avoided, so that loading of the noise of different frequency bands into the clock signal is avoided, and a frequency stability of the clock signal is improved.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.