Power supply circuit

1. Technical Field

The present disclosure relates to power supply circuits and, particularly, to a power supply circuit for a motherboard in a computer.

2. Description of the Related Art

Motherboards are the most important parts in computers. Power supply circuits provide working voltages for electronic components on the motherboards, and are necessary, especially for a memory controller hub (MCH). The MCH, also known as a north bridge, is configured to connect to a central processing unit (CPU), an accelerated graphics port (AGP) bus, and a memory. However, a voltage about 1.25V provided by a conventional power supply circuit to the MCH may be not stable due to influence by interferential signals, which may lead to computer malfunctions.

FIG. 1 is a circuit diagram of an exemplary embodiment of a power supply circuit for a motherboard.

FIG. 2 is a circuit diagram of another exemplary embodiment of a power supply circuit for a motherboard.

Referring to FIG. 1 , an exemplary embodiment of a power supply circuit 100 is configured to supply power to a memory controller hub (MCH) 30 on a motherboard. The power supply circuit 100 includes a first N type metal oxide semiconductor (NMOS) transistor Q 1 and a second NMOS transistor Q 2 , two induction coils L 1 and L 2 , four resistors R 1 -R 4 , five capacitors C 1 -C 4 and C 6 , a voltage regulator module (VRM) 10 , a resistor-capacitor (RC) delay circuit 40 , and a pulse width modulation (PWM) controller 20 . The PWM controller 20 is configured for providing a PWM signal for the VRM 10 . The VRM 10 is configured for controlling the first NMOS transistor Q 1 and the second NMOS transistor Q 2 to be turned on according the PWM signal.

A gate of the NMOS transistor Q 1 is connected to an upper gate drive output (UGATE) pin of the VRM 10 via the resistor R 1 . A source of the NMOS transistor Q 1 is connected to a PHASE pin of the VRM 10 , and connected to the MCH 30 via the induction coil L 1 . The source of the NMOS transistor Q 1 is also connected to a BOOT pin of the VRM 10 via the capacitor C 1 and the resistor R 2 in series. The capacitor C 1 is capable of storing power for the BOOT pin of the VRM 10 . The BOOT pin is associated with the UGATE pin of the VRM to drive the first NMOS transistor Q 1 . The drain of the NMOS transistor Q 1 is arranged to receive a 12V system power 12V_SYS via the induction coil L 2 , and also grounded via the capacitors C 2 , C 3 , and C 4 in parallel. The induction coil L 2 and the capacitors C 2 , C 3 , and C 4 are configured for wave filtering and reducing influence of interferential signals.

A gate of the NMOS transistor Q 2 is connected to a lower gate drive output (LGATE) pin of the VRM 10 via the resistor R 3 . A source of the NMOS transistor Q 2 is grounded. A drain of the NMOS transistor Q 2 is connected to the source of the NMOS transistor Q. The drain of the NMOS transistor Q 2 is also connected to an external buffer PWM current protection signal (VTT_OPS) pin of the PWM controller 20 via the resistor R 4 . The VTT_OPS pin of the PWM controller 20 is configured for over current protection. The drain of the NMOS transistor Q 2 is also connected to the RC delay circuit 40 . The RC delay circuit 40 includes a resistor R 5 and a capacitor C 5 . The resistance of the resistor R 5 ranges from about 2.09 ohms to 2.31 ohms. The capacitance of the capacitor C 5 is about 1 nF. A first end of the resistor R 5 is connected to the drain of the NMOS transistor Q 2 . A second end of the resistor R 5 is grounded via the capacitor C 5 .

A PVCC pin and a VCC pin of the VRM 10 are both arranged to receive the system power 12V_SYS, and also grounded via the capacitor C 6 . The PWM pin of the VRM 10 is connected to an external buffer PWM control output signal (VTT_PWM) pin of the PWM controller 20 . A GND pin of the VRM 10 is grounded.

At a stage after the VRM 10 is initially powered, voltages at the VCC and PVCC pins of the VRM 10 are lower than 12V and voltages at the UGATE and the LGATE pins are both at a low voltage level. The NMOS transistors Q 1 and Q 2 are both turned off. 100-500 ms later, the voltages at the VCC and PVCC pins of the VRM 10 reach 12V. The PWM pin of the VRM 10 receives the PWM signal output from the VTT_PWM pin of the PWM controller 20 . When the PWM signal is at a high voltage level, the UGATE pin of the VRM 10 outputs a high voltage level signal to turn on the first NMOS transistor Q 1 , and the LGATE pin of the VRM 10 outputs a low voltage level signal to keep the second NMOS transistor Q 2 off. When the PWM signal is at a low voltage level, the LGATE pin of the VRM 10 outputs a high voltage level signal to turn on the second NMOS transistor Q 2 , and the UGATE pin of the VRM 10 outputs a low voltage level signal to turn off the first NMOS transistor Q 1 . Such that, the VRM 10 controls the first and second NMOS transistors Q 1 , Q 2 to turn on in alternating manner, and thereby the PHASE pin of the VRM 10 is regulated to output a 1.25V voltage signal. The 1.25V voltage signal is provided to the MCH 30 via the RC delay circuit 40 and the induction coil L 1 . The RC delay circuit 40 delays the 1.25 voltage signal to make the 1.25 voltage signal sufficient stable. The induction coil L 1 is configured for current shunting and wave filtering.

In the present exemplary embodiment, the first and second NMOS transistors Q 1 and Q 2 , functioning as switches, are turned on in alternating manner controlled by the VRM 10 , thereby to make the PHASE pin of the VRM 10 output the 1.25V voltage signal for the MCH 30 . The first and second NMOS transistors Q 1 and Q 2 can also be replaced by other switches correspondingly, such as NPN transistors, PNP transistors and the like. Furthermore, the RC delay circuit 40 can be replaced by other kinds of a delay circuit, such as an induction-capacitor (LC) delay circuit.

Referring to FIG. 2 , the capacitors C 2 , C 3 , C 4 , C 6 , and the resistors R 1 ˜R 4 of the power supply circuit 200 can be canceled to form a power supply circuit 200 for reducing manufacture cost, in accordance with another embodiment.

It is to be understood, however, that even though numerous characteristics and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.