Method and apparatus for reducing power supply introduced data dependent jitter in high-speed SerDes transmitters

This application claims the benefit of priority to previously filed U.S. provisional patent application Ser. No. 60/980,603, filed Oct. 17, 2007, entitled A METHOD TO ELIMINATE POWER SUPPLY INTRODUCED DATA DEPENDENT JITTER IN HIGH-SPEED SERDES TRANSMITTER. That provisional application is hereby incorporated by reference in its entirety.

1. Field of the Invention

The present invention relates generally to data transmission, and more particularly to reducing jitter introduced by power supplies.

2. Description of Related Art

A SerDes, or Serializer/deserializer converts a parallel data stream to a serial data stream and vice versa. SerDes chips facilitate the transmission of parallel data between two points in high-speed serial streams over a differential media, reducing the number of signal paths and thus the number of connecting pins or wires required. SerDes devices may be used in wireless network routers, fiber optic communications systems, USB interfaces, PCIE (Peripheral Component Interconnect Express), and storage applications, and are capable of operating at speeds in excess of 10 Gbps.

Transmission jitter can include a random jitter component and a deterministic jitter component. Predicting causes of random jitter can be difficult. Deterministic jitter may result from conditions such as Duty Cycle Distortion (DCD), Data Dependent Jitter (DDJ), and Periodic Jitter.

DDJ, sometimes called Inter-symbol Interference (ISI), is usually the result of a bandwidth limitation problem in either a transmitter or physical media over which transmission is occurring. Reduction in transmitter or media bandwidth may result in varying amplitudes of data bits and changes in the time domain. Jitter depends not only on repeating-bit lengths, but also on states of preceding bits, so that jitter is correlated with the sequence of bits in a data stream.

FIG. 1 illustrates a currently available high-speed serial data transmitter which converts a parallel data input into a serial data output. As shown, an N to 2 multiplexer (MUX) 101 may convert N parallel input data streams into 2 parallel data streams: D odd consisting of the odd numbered bits of a serial data stream D and D even consisting of the even numbered bits of the serial data stream D. At the final stage of multiplexing the parallel data streams into the serial data stream D, a 2 to 1 MUX 102 may receive D odd and D even and combine them into the serial data stream D. A low jitter clock 103 may be used to retime the serial data stream D and to clean up the data, thus avoiding DDJ at the output of the 2 to 1 MUX 102 . The low jitter clock 103 may be, e.g. a Phase Locked Loop (PLL). The clean data may then go to a pre-driver 104 before reaching a final transmitter driver 106 . At this point, DDJ may start to accumulate due to limited bandwidth and non-ideal power supply.

Currently, inverter based pre-drivers are widely used in high-speed low power data communications. The pre-driver 104 may be coupled to a power supply 105 , as shown in FIG. 1 . The voltage output of the power supply 105 may fluctuate even when a dedicated regulated power supply is used. Not only is it difficult to keep the pre-driver power supply 105 constant over time, but also the fluctuation is often not able to settle before the next data bit arrives in high-speed data transmissions. The residue of a preceding data bit interferes with a next data bit or later bits through the power supply 105 , introducing data dependent jitter (DDJ). The DDJ introduced by the power supply 105 is a primary jitter source in currently available high-speed low power transmitters.

One conventional way to reduce the DDJ introduced by the power supply 105 is to add decoupling capacitors to the power supply 105 , in order to reduce the fluctuation in the power supply 105 . However, adding decoupling capacitors to low impedance nodes may take a lot of space and is not efficient. Meanwhile, it may increase the settling time for the power supply 105 before the next bit arrives. The other extreme is to remove all decoupling capacitors on the power supply 105 to minimize the settling time, but in high speed applications, the power supply 105 still cannot settle within a bit time.

With careful design, data transitions may become fast enough so that the rise/fall of the current bit data does not depend on preceding bit states, and the major source of DDJ may be from the power supply. Therefore, it may be desirable to provide a method and apparatus which may reduce power supply introduced data dependent jitter in high-speed SerDes transmitters.

Embodiments of the present invention are described herein with reference to the accompanying drawings, similar reference numbers being used to indicate functionally similar elements.

FIG. 1 illustrates a currently available high-speed serial data transmitter which converts a parallel data input into a serial data output.

FIG. 2 illustrates a high-speed serial data transmitter according to one embodiment of the present invention.

FIG. 3A illustrates waveforms obtained during the operation of a high-speed serial data transmitter according to one embodiment of the present invention.

FIG. 3B illustrates waveforms obtained during the operation of a high-speed serial data transmitter according to one embodiment of the present invention

The present invention provides a high-speed SerDes transmitter which may reduce power supply introduced data dependent jitter. The accuracy of a power supply of a pre-driver may vary depending on the pattern of an input data stream. Instead of providing a constant voltage output, the output voltage of the power supply may gradually go up when there are consecutive 0s in a data stream, and may gradually go down when there are consecutive 1s in a data stream.

Instead of trying to make the output voltage of a power supply of a pre-driver constant, the present invention tries to make the output voltage of the power supply return to its normal level periodically, e.g., after each bit time, to follow the data rate of an input data stream. A complementary pre-driver may be used to create a complementary data stream which may be at the same data rate as the input data rate. The complementary data stream may have a transition when there is no transition between two consecutive bits in the input data stream, but have no transition when there is a transition in the input data stream. As a result, there is a transition at the power supply during each bit time, and the power supply may be drawn back to its normal level during each bit time.

Consequently, the power supply variation is periodic at the beat of the input data rate, and the power supply may have the same impact on each data bit. Thus, each bit in the input data stream may see the same level of power supply, and the data dependent jitter may be reduced or eliminated.

FIG. 2 illustrates a high-speed transmitter according to one embodiment of the present invention. As shown, a complementary data stream may be added to the power supply 105 . The complementary data stream may add a transition to the power supply 105 when the input data stream D of the pre-driver 104 does not have a transition between two consecutive bits, but may add nothing when the input data stream D has a transition between two consecutive bits. The transition may be a rise or a fall. The complementary data stream may be created by a complementary pre-driver 207 coupled to the power supply 105 . The complementary pre-driver 207 may be coupled to a complementary 2 to 1 multiplexer 208 .

In one embodiment, the input of the complementary 2 to 1 multiplexer 208 may be D even and the inverse of D odd . FIG. 3A illustrates waveforms of signals in this example. As shown, a sub-stream D even at one input of the 2 to 1 multiplexer 102 may be, for example:

0 1 1 1 0 0 at bits 0 , 2 , 4 , 6 , 8 , 10 , 12 , and 14 .

A sub-stream D odd at the other input of the 2 to 1 multiplexer 102 may be, for example:

1 1 0 1 1 0 0 0 at bits 1 , 3 , 5 , 7 , 9 , 11 , 13 , and 15 .

Consequently, the output of the 2 to 1 multiplexer 102 may be, e.g.,

1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 0 at bits 0 - 15 .

The inverse of D odd at one input of the complementary 2 to 1 multiplexer 208 may be, for example:

0 0 1 0 0 1 1 1 at bits 1 , 3 , 5 , 7 , 9 , 11 , 13 , and 15 .

The complementary 2 to 1 multiplexer 208 may multiplex the sub-stream D even and the inverse of the sub-stream D odd , and its output may be, for example:

1 0 0 0 0 1 1 0 1 0 1 1 0 1 0 1 at bits 0 - 15 .

Thus, the complementary 2 to 1 multiplexer 208 may create a transition at the power supply 105 when there is no transition between two consecutive bits in the data stream D. For example, there is no transition from bit 0 to bit 1 in the data stream D, but the complementary 2 to 1 multiplexer 208 creates a transition from bit 0 to 1 in a data stream D complementary ; and there is no transition from bit 4 to 5 in the data stream D, but the complementary 2 to 1 multiplexer 208 creates a transition from bit 4 to 5 in the data stream D complementary . Similarly, transitions are also created from bit 6 to 7 , from bit 7 to 8 , from bit 8 to 9 , from bit 9 to 10 , from bit 11 to 12 , from bit 12 to 13 , from bit 13 to 14 , and from bit 14 to 15 in the data stream D complementary . Thus, the power supply 105 may see a transition during each bit time, and the voltage output of the power supply 105 may be drawn back to its normal level during each bit time. Since the regulated power supply 105 is at the same voltage level at each data transition point, the data dependent jitter may be eliminated or reduced.

In another embodiment, D odd and the invert of D even may be applied to the input of the complementary 2 to 1 multiplexer 208 . FIG. 3B illustrates waveforms of signals in this example. As shown, the inverse of D even may be, for example:

0 1 1 0 0 0 1 1 at bits 0 , 2 , 4 , 6 , 8 , 10 , 12 , and 14

The complementary 2 to 1 multiplexer 208 may multiplex the sub-stream D odd and the inverse of the sub-stream D even , and its output D complementary may be, for example:

0 1 1 1 1 0 0 1 0 1 0 0 1 0 1 0 at bits 0 - 15 .

Similarly to the embodiment shown in FIG. 3A , the complementary 2 to 1 multiplexer 208 may create a transition at the power supply 105 when there is no transition between two consecutive bits in the data stream D. For example, there is no transition from bit 0 to bit 1 in the data stream D, but the complementary 2 to 1 multiplexer 208 may create a transition from bit 0 to 1 in the data stream D complementary ; and there is no transition from bit 4 to 5 in the data stream D, but the complementary 2 to 1 multiplexer 208 may create a transition from bit 4 to 5 in the data stream D complementary . Similarly, transitions may also be created from bit 6 to 7 , from bit 7 to 8 , from bit 8 to 9 , from bit 9 to 10 , from bit 11 to 12 , from bit 12 to 13 , from bit 13 to 14 , and from bit 14 to 15 in the data stream D complementary . Thus, the voltage output of the power supply 105 may be drawn back to its normal level during each bit time, and the data dependent jitter may be eliminated or reduced.

Several features and aspects of the present invention have been illustrated and described in detail with reference to particular embodiments by way of example only, and not by way of limitation. Alternative implementations and various modifications to the disclosed embodiments are within the scope and contemplation of the present disclosure. Therefore, it is intended that the invention be considered as limited only by the scope of the appended claims.