Managing data movement in a cell broadband engine processor

This patent claims the benefit of the priority date of a prior foreign application filed under 35 U.S.C. §119, namely counterpart Chinese Patent Application No. 200710153176.0, entitled “Method of Managing Data Movement and Cell Broadband Engine Processor Using the Same,” which was filed on Sep. 28, 2007. The foreign application is incorporated herein by reference in its entirety.

The present invention relates to a cell broadband engine processor, and particularly to a method of managing data movement in the cell broadband engine processor and a cell broadband engine processor using the same.

Cell broadband engine (CellBE for short hereinafter) processor is a kind of microprocessor utilizing parallel processing. Generally, basic configuration of a CellBE processor comprises a Power Processing Element (PPE), eight Synergistic Processing Elements (SPEs), a Memory Flow Control (MFC), an Internal Interrupt Control (IIC), and a Main Memory. Computing components of the CellBE processor are PPE and SPEs. Componential parts of the CellBE processor are connected via high-speed bus of “Elements Interconnection Bus” (EIB). Any two of the eight SPEs may exchange data through a high-speed bus of 25.6 GB therebetween, while only a bus of 25.6 GB totally is between SPEs and the main memory. Bus transfers between SPEs and bus transfers between respective SPEs and the main memory may be in parallel. CellBE processor is applicable to various applications from handhold devices to main computers.

CellBE processor presents a step change in computer architecture by eight SPEs which may process in parallel, thereby improving computer performance of computer greatly. In order to solve memory wall problem in CellBE processor, each of SPEs in the CellBE processor is provided with a specific local storage and may only access its local storage (LS) directly. Introduction of LS can reduce the memory latency. Usually, however, size of LS is 256 KB, and such size of storage space brings trouble for developers for its limitation for programs' binary size. Besides, such SPEs lack cache, which will decrease computing performance of CellBE processor for processing data massive application, such as high performance computing, digital media, and financial applications.

To solve the above problems, existing CellBE processor incorporates a specific physical cache for SPE. Although the computing performance is improved, architecture of the CellBE processor is more complex, resulting in increase of cost. Another approach is soft-cache. This approach uses part of LS as a soft-cache. Drawback for this solution is in that the technology decreases available space of LS, and once size of a program is becoming large, the soft-cache will not be usable.

Further, another problem in the related art is persistent data management. Due to the limited size of LS, most persistent data must be put into main memory managed by PPE. There are several shortcomings for communication with the main memory. Firstly, the processing in PPE is probably switched out by OS, and communication overhead between PPE and SPE will increase. Secondly, data in the main memory may be swapped out into hard disk swap partition, and latency will be increased. Thirdly, irregular data movement is easily to cause a cache inconsistent problem, such as cache false sharing.

To solve at least one of above problems, the present invention provides an effective persistent data management method to enhance the performance and utilization of software management cache.

Therefore, according to an aspect of the present invention, a method of managing data movement in a cell broadband engine processor is provided, comprising: determining one or more idle synergistic processing elements (SPEs) among multiple SPEs in the cell broadband engine processor as a managing SPE, and informing a computing SPE among said multiple SPEs of a starting effective address of a LS of said managing SPE and an effective address for a command queue; and said managing SPE managing movement of data associated with computing of said computing SPE based on the command queue from the computing SPE.

According to another aspect of the present invention, a cell broadband engine processor is provided, comprising a power processing element (PPE), multiple synergistic processing elements (SPEs), a memory flow control (MFC) and a local storage (LS) associated with each SPE, an internal interrupt control (IIC), and a main memory, characterized in that when said cell broadband engine processor runs an application, said power processing element is used to create a computing SPE from said multiple SPEs and to create a managing SPE among idle SPEs from said multiple SPEs, and informs the computing SPE among the multiple SPEs that executes the application of a starting effective address of the LS associated with said managing SPE and an effective address for a command queue, and the LS in said managing SPE includes a part for storing said command queue and a buffer part for buffering data, and is used to manage movement of data related to computing of said computing SPE based on the command queue from the computing SPE.

Hereinafter, embodiments of the invention will be described in detail, by way of example only, with respect to the attached figures in which:

FIG. 1 shows a flowchart of loading data in a method of managing data movement in a CellBE processor according to the invention;

FIG. 2 shows a flowchart of storing data in the method of managing data movement in the CellBE processor according to the invention; and

FIG. 3 shows architecture of a managing SPE and a computing SPE in the CellBE processor according to the invention.

One aspect of the invention is to provide a method of managing data movement in a cell broadband engine processor, comprising: determining one or more idle synergistic processing elements (SPEs) among multiple SPEs in the cell broadband engine processor as a managing SPE, and informing a computing SPE among said multiple SPEs of a starting effective address of a LS of said managing SPE and an effective address for a command queue; and said managing SPE managing movement of data associated with computing of said computing SPE based on the command queue from the computing SPE.

FIG. 1 shows a flowchart of loading data in a method of managing data movement in a CellBE processor according to the invention. At first, when the CellBE processor runs an application therein, a computing SPE for performing this application is created in a PPE which will be described as FIG. 3 later, and an idle SPE among multiple SPEs is created as a managing SPE for the computing SPE. The managing SPE is used to manage movement of data of the computing SPE (step S 102 ). As described with respect to FIG. 3 later, each SPE has one Runtime, and the managing SPE has a part for storing command queue and a buffer for buffering data. While PPE creates the managing SPE, a starting effective address of LS of the managing SPE and an effective address of command queue are informed to the computing SPE. The computing SPE sends a data loading command to the command queue in the managing SPE during executing the application or in advance. This command instructs the managing SPE loading into the computing SPE the data needed by the computing SPE in time (step S 103 ). The computing SPE can issue this command through DMA, mailbox or other SPE-SPE communication method. The data loading command is a quaternion (SRC, DEST, SIZE, READYBIT_EA) as described below in which the sequence of respective elements may be various. SRC is an effective address of data which need to be loaded, and generally is an effective address of the data in the main memory or an address of LS in the managing SPE during the loading stage, DEST is an effective address of data which need to be stored, and generally is an effective address in the computing SPE during the loading stage. SIZE is size of the data which need to be moved or loaded. READYBIT_EA is an effective address of a ready bit, that is, runtime (Runtime) in the computing SPE will set the data into valid when the data has been transferred from the managing SPE to the computing SPE. The managing SPE confirms reception of the data loading command and prepares to execute the data loading command (step S 104 ).

After the managing SPE confirms existence of the data loading command in the command queue, firstly, it determines whether there is data to be loaded in buffer of its local storage LS according to the loading command described by the quaternion (YES of step S 105 ). If the data to be loaded has been buffered in the buffer, the managing SPE issues DMA (direct memory access) and send the data that need to be loaded from the buffer of the managing SPE to destination effective address DEST in the computing SPE (step S 106 ). Then the data loading command is removed from the command queue (step S 107 ) and loading process ends (step S 108 ).

If the managing SPE determines that no data to be loaded is in the buffer of its local storage LS according to the loading command described by the quaternion (NO of step S 105 ), it needs to judge whether there is no space in its buffer to buffer the data which need to be loaded (step S 109 ). If judgment result at step S 109 is “NO”, the process goes to step S 113 where the managing SPE issues DMA (direct memory access) based on the loading command described by the quaternion so as to buffer the data which need to be loaded from the main memory to the buffer of the managing SPE. Sequentially, the process goes to step S 106 .

On the other hand, if the managing SPE judges that there is no space in its buffer to buffer the data which need to be loaded at step S 109 , the process goes to step S 110 , where the managing SPE uses the principle of Least Recently Use (LRU) to find out least-recently-used data buffered in the buffer and determines whether input entry of the least-recently-used data is modified. Generally, the data is marked as “load” if it is not modified, otherwise is marked as “store”. If judgment result at step S 110 is “NO”, the process goes to step S 112 where the managing SPE issues DMA (direct memory access) based on the loading command described by the quaternion so as to directly buffer and overwrite the data which need to be loaded to the address of the least-recently-used data in the buffer of the managing SPE from the main memory. Then the process goes to step S 106 .

Besides, if the managing SPE determines that the input entry of the least-recently-used data was modified, e.g. the least-recently-used data was marked as “store”, then the process goes to step S 111 where DMA (direct memory access) is issued. The managing SPE issues DMA (direct memory access) based on the loading command described by the quaternion so as to store the modified least-recently-used data from its buffer to original effective address of the main memory. Then the process goes to step S 112 .

FIG. 2 shows a flowchart of storing data in the method of managing data movement in the CellBE processor according to the invention. Like description with reference to FIG. 1 , firstly, when the CellBE processor runs an application therein, a computing SPE for performing this application is created in a PPE which will be described as FIG. 3 later, and an idle SPE among multiple SPEs is created as a managing SPE for the computing SPE. The managing SPE is used to manage movement of data of the computing SPE (step S 102 ). The managing SPE has a part for storing command queue and a buffer for buffering data. While PPE creates the managing SPE, the computing SPE has obtained the starting effective address of LS of the managing SPE and the effective address for command queue. The computing SPE sends a data storing command to the command queue in the managing SPE when executing the application and requiring storing the generated data. This command instructs the managing SPE to buffer the data generated by the computing SPE into buffer of the managing SPE and then to the main memory (step S 203 ). The computing SPE can issue this command through DMA, mailbox or other SPE-SPE communication method. The data storing command is also a quaternion (SRC, DEST, SIZE, READYBIT_EA) in which SRC is an effective address of data which need to be stored, and generally is an effective address of the data in the main memory during the storing stage; DEST is an effective address of data which need to be stored, and generally is an effective address in the main memory or the buffer of the managing SPE during the storing stage; SIZE is the size of the data which need to be moved or stored; and READYBIT_EA is an effective address of a ready bit, that is, runtime (Runtime) in the managing SPE will set the data which has been buffered in the buffer into valid. The managing SPE confirms reception of the data storing command and prepares to execute the data storing command (step S 204 ).

After the managing SPE confirms existence of the data storing command in the command queue, firstly, it determines whether there is data to be stored in buffer of its local storage LS according to the loading command described by the quaternion (YES at step S 205 ). If the data to be stored has been buffered in the buffer, the managing SPE removes the data storing command from the command queue (step S 207 ) and terminates the storing process (step 3208 ). Or the data to be stored may be overwritten to the address of same data in the buffer directly in the case where the data to be stored has been in the buffer.

If the managing SPE determines that no data to be stored is in the buffer of its local storage LS according to the storing command described by the quaternion (NO of step S 205 ), it needs to judge whether there is no space in its buffer to buffer the data which need to be stored (step S 209 ). If judgment result at step S 209 is “NO”, the process goes to step S 213 where the managing SPE issues DMA (direct memory access) based on the storing command described by the quaternion so as to buffer the data which need to be stored from the main memory to the buffer of the managing SPE. Then the process goes to step S 207 .

On the other hand, if the managing SPE judges that there is no space in its buffer to buffer the data which need to be stored at step S 209 , the process goes to step S 210 , where the managing SPE uses the principle of Least Recently Use (LRU) to find out least-recently-used data buffered in the buffer and determines whether input entry of the least-recently-used data was modified. If judgment result at step S 110 is “NO”, for example, the data is marked as “load”, the process goes to step S 212 where the managing SPE issues DMA (direct memory access) based on the storing command described by the quaternion so as to directly buffer and overwrite the data which need to be stored to the address of the least-recently-used data in the buffer of the managing SPE from the computing SPE. Then the process goes to step S 207 .

Besides, if the managing SPE determines that the input entry of the least-recently-used data was modified, e.g. the least-recently-used data was marked as “store”, then the process goes to step S 211 where DMA (direct memory access) is issued. The managing SPE issues DMA (direct memory access) based on the storing command described by the quaternion so as to store the modified least-recently-used data from its buffer to original effective address of the main memory. Then the process goes to step S 212 .

Another aspect of the present invention provides a cell broadband engine processor for running the above data movement managing method, comprising a Power Processing Element (PPE), multiple Synergistic Processing Elements (SPEs), a Memory Flow Control (MFC), an Internal Interrupt Control (IIC), and a Main Memory, characterized in that when the cell broadband engine processor runs an application, the power processing element is used to create a computing SPE from the multiple SPEs and to create a managing SPE among idle SPEs from the multiple SPEs, and informs the computing SPE among the multiple SPEs that executes the application of a starting effective address of LS associated with the managing SPE and an effective address for a command queue, and the LS in the managing SPE includes a part for storing the command queue and a buffer part for buffering data, and is used to manage movement of the data related to computing of the computing SPE based on the command queue from the computing SPE.

FIG. 3 shows a schematic diagram of a managing SPE and a computing SPE of the CellBE processor according to the present invention. To simplicity, several elements without direct relationships with respect to the present invention are omitted. Same elements are indicated by like reference numbers.

As shown in FIG. 3 , the cell broadband engine processor according to the present invention mainly comprises a Power Processing Element (PPE) 1 , a computing Synergistic Processing Element (SPE) 2 , a managing Synergistic Processing Element (SPE) 3 and a Main Memory 4 . Each synergistic processing element may include a local storage (LS) 5 and a runtime (Runtime) 6 which is used to manage local storage 5 in the synergistic processing element that it belongs to and date access from other synergistic processing elements. The LS of the managing SPE includes a command queue storing part for storing commands sent from the computing SPE and a data buffer for buffering data. The Runtime may pre-fetch data from the main memory 4 and responds for writing the data buffered in the data buffer into the main memory 4 or LS of the computing SPE 2 according to the data loading command in the command queue.

During the cell broadband engine processor executing the application, the managing SPE is an agent for PPE-SPE and SPE-SPE data communication. The managing SPE responds for loading data from the main memory and local storage, for storing data into the main memory and local storage, and for writing the modified data back into the main memory and local storage.

The runtime runs in the managing SPE in response to data loading and storing request from other SPEs. It issues DMA to loading data from the main memory (or the local storage) and put the data into the data buffer, and the runtime will handle the data movement for other SPEs.

The command queue is a communication channel between the computing SPE and the managing SPE. The computing SPE sends its data loading/storing command into the command queue, and the managing SPE retrieves request from the queue.

Referring to FIG. 3 , when the cell broadband engine processor executes an application, the PPE creates a SPE thread for managing SPE, and informs the computing SPE of the starting effective address of LS associated with the managing SPE and the effective address for command queue. In order to perform data loading/storing operations, the computing SPE issues request or command to the management data movement SPE. The computing SPE can issue this command through DMA, mailbox or other SPE-SPE communication method. The data storing command is a quaternion (SRC, DEST, SIZE, READYBIT_EA) in which SRC is an effective address of data which need to be stored; DEST is an effective address of data which need to be stored; SIZE is the size of the data which need to be moved or stored; and READYBIT_EA is an effective address of a ready bit, and Runtime will set the data into valid when it is prepared. SRC, DEST and READYBIT_EA may be addresses of the main memory or the local storage.

With the present invention, available buffer space when the cell broadband engine processor of the invention executes the application is significantly larger than existing soft-cache solution, and available space for programs will not be decreased. The invention does not conflict with up-and-coming technologies for SPE, and not need extra hardware support. Due to application of the invention, data stored in the managing SPE will not be swapped into hard disk swap by the operation system. Also, memory flow control (MFC) of running program in the computing SPE can be used for PPE-SPE communication because data loading and storing works are performed by the managing SPE. With providing the buffer in the managing SPE, more persistent data may be buffered, reducing cost for communication. Further, because of minimal setup time for local memory, the latency and throughput of the computing SPE to PPE data movement will be better.

It should be noted that the present invention does not set limitation to amount of SPE for data management, and the embodiments may use all available SPEs or some part of the SPEs. Also, one managing SPE may serve a plurality of SPE. Other buffer management and data pre-fetch techniques are not limited.

Description of the present invention is provided for purpose of illustration, but not exhaustive or limited to the embodiments disclosed. Many modifications and variations are clear to those skilled in this art. These embodiments are chosen for explaining principle and actual application of the present invention and for other skilled in this art to understand the invention, so as to implement various embodiments with various modifications that may be appropriate for other desired usage.