Integrated circuit

This application claims priority to German Patent Application 10 2007 046 729.1, which was filed Sep. 28, 2007 and is incorporated herein by reference.

The invention relates to an integrated circuit generating an output signal having a high level, which is used, for example, for controlling a transistor operating as a switch, which connects different networks.

Embodiments of the present invention will be detailed subsequently referring to the appended drawings, in which:

FIG. 1 is an embodiment of an integrated circuit for generating an output signal for switching an isolating transistor;

FIG. 2 is a signal diagram for the embodiment of the integrated circuit shown in FIG. 1 ;

FIG. 3 is a second embodiment of an integrated circuit for generating an output signal for switching an isolating transistor;

FIG. 4 is a signal diagram for the embodiment of the integrated circuit shown in FIG. 3 ;

FIG. 5 is a third embodiment of an integrated circuit for generating an output signal for switching an isolating transistor;

FIG. 6 is a fourth embodiment of an integrated circuit for generating an output signal for switching an isolating transistor;

FIG. 7 is a signal diagram for the embodiment of the integrated circuit shown in FIG. 6 ; and

FIG. 8 is an embodiment of an integrated semiconductor memory having an integrated circuit for generating an output signal for switching isolating transistors.

Read amplifiers are used in the cell field of a memory chip, which amplify a voltage on a bit line that results, for example, from reading out a memory cell. In a so-called shared SA concept, a read amplifier is connected on both sides to one bit line pair each. If memory access to a memory cell connected to one of the two bit line pairs takes place, the other of the bit line pairs has to be disconnected from the read amplifier. Disconnecting a deactivated bit line and connecting the active bit line to the read amplifier, respectively, is performed via an isolating transistor (MUX device), which is connected between the read amplifier and the connected bit line.

For controlling the isolating transistor to be conductive or non-conductive, respectively, a control signal having a control voltage level is applied to a control terminal of the transistor. For writing a 1-data value, the read amplifier generates a high output voltage, which has to be transmitted via the controllable path of the isolating transistor, in order to be fed into the activated bit line. For transmitting a high load via the control path of the isolating transistor, the control voltage (gate voltage) for controlling the isolating transistor to be conductive has to be significantly higher than the voltage level representing the 1-data value. Typically, the high control voltage has to be pumped from a supply voltage of the semiconductor memory with low efficiency.

The capacitive load of the control signal is very high, since the control signal is fed into all control terminals of the isolating transistors of a read amplifier strip. Every switch process of the isolating transistor contributes significantly to the overall current consumption during activation.

FIG. 1 shows an embodiment of an integrated circuit 1 for generating an output signal MUX that can be used as a control signal for controlling an isolating transistor in an integrated semiconductor memory. The integrated circuit has an input terminal E 1 for applying a supply voltage Vext. The supply voltage Vext is, for example, generated by a voltage network (mains supply) N 1 , which is connected to the input terminal E 1 . The input terminal E 1 is connected to an output terminal O for generating the output signal MUX via a switching unit I 10 , which comprises a controllable switch N 10 and a controllable switch P 10 .

Further, the integrated circuit 1 has a first input terminal E 2 for applying a voltage Vpp. The voltage Vpp is generated by a further voltage network N 2 , which is connected to the input terminal E 2 . After power-up of the integrated semiconductor memory, the voltage Vpp has a level that is higher than the level of the voltage Vext. The input terminal E 2 is connected to the output terminal O of the integrated circuit via a switching unit I 20 comprising a controllable switch P 20 . The controllable switches P 10 and P 20 can be implemented as switching transistors. The substrate terminals SB 10 and SB 20 of the switching transistors are each connected to the input terminal E 2 for applying the voltage Vpp.

Further, the output terminal O is connected to a terminal B for applying a reference voltage Gnd via a controllable switch N 20 . In the embodiment of FIG. 1 , the controllable switches N 10 and N 20 are each implemented as n-channel field-effect transistors, whereas the controllable switches P 10 and P 20 are implemented as p-channel field-effect transistors.

For controlling the controllable switches, the integrated circuit has a control terminal K for applying a control signal IN. After a delay by the delay members INV 1 and INV 2 , the control signal IN is supplied to a control terminal A 30 of the controllable switch N 20 . A control terminal A 10 of the controllable switch P 10 is connected to a control circuit SE 0 . The control circuit SE 0 has a logic gate S 10 to which the delayed control signal IN is supplied on the input side. Further, the control circuit SE 0 comprises a delay circuit VS 0 comprising several delay members VG 1 , . . . , VG 5 . The logic gate S 10 is implemented as NAND gate, which is connected to the control terminal A 10 on the output side.

Further, the integrated circuit 1 comprises a logic gate S 20 , which is also implemented as NAND gate. The control signal IN is supplied in a delayed manner to the NAND gate S 20 at a terminal A 20 on the input side. A further terminal A 10 of the NAND gate S 20 is connected to an output side of the NAND gate S 10 . The NAND gate S 20 generates a control signal on the output side, which is supplied to a control terminal A 00 of the controllable switch P 20 .

The mode of operation of the integrated circuit 1 will be described with regard to FIG. 2 . FIG. 2 shows the waveforms of the control signal IN at the terminal K as well as the waveform of the output signal MUX and the waveforms at the terminals A 00 , A 10 , A 20 and A 30 . During a time t 1 , the control terminal K is controlled by a high level of the control signal IN. Thereby, the switching transistors P 10 and P 20 are controlled to be non-conductive, wherein the controllable switch N 20 is controlled to be conductive. Thus, the output terminal O is connected to the terminal B for applying the reference voltage Gnd, so that the control signal MUX has a low level.

At the time t 2 , the control signal IN is applied to the control terminal K with a low level. Thereby, the controllable switch N 20 remains controlled to be conductive at first and the controllable switch P 10 remains controlled to be non-conductive. At the time t 3 , the signal at the terminal A 10 changes to a lower level, whereby the controllable switch P 10 is controlled to be conductive. The controllable switch P 20 remains non-conductive. Further, a state change of a signal applied to the terminal A 30 occurs, whereby the controllable switch N 20 is controlled to be non-conductive.

After the signal applied to the input side of the delay circuit VS 0 has passed through the delay circuit, the signal at the terminal A 10 at the time t 4 changes to a high level. Thereby, the controllable switch P 10 is non-conductive again. Thus, both controllable switches P 10 and P 20 are non-conductive at the time t 4 . At the time t 5 , the NAND gate S 20 generates a low signal level on the output side at the control terminal A 00 of the controllable switch P 20 , whereby the controllable switch P 20 is controlled to be conductive, while the controllable switch P 10 remains controlled to be non-conductive.

While the output terminal O is fed by the voltage network N 1 providing the voltage Vext at the time t 3 , feeding of the output terminal O takes place via the voltage network N 2 providing the voltage Vpp at the time t 5 . Thereby, the level of the control signal MUX at the output terminal O increases continually. At the time t 6 , when the control signal IN has a high level again, the controllable switches P 10 and P 20 are again controlled to be non-conductive, whereas the controllable switch N 20 connects the output terminal O to the terminal B to be conductive for applying the reference voltage Gnd. Thereby, the level at the output terminal O decreases again.

By the integrated circuit shown in FIG. 1 , the output terminal O is, at first, connected to the input terminal E 1 where the voltage Vext is provided. Subsequently, the voltage network N 1 is separated from the output terminal O and the input terminal E 2 , where the higher voltage Vpp is provided, is connected to the output terminal O. Thereby, the output signal MUX is first pulled to the non-pumped external voltage Vext and then to the increased voltage level Vpp. By increasing the voltage in two stages, current consumption can be reduced.

During power-up of an integrated memory, the so-called power-up state of the memory, the voltage Vpp still has a level lying below the level of the external supply voltage Vext. In this case, the well-source diode of the p-channel field-effect transistor P 10 driving the output signal MUX against the voltage Vext is controlled to be conductive. During power-up of the memory chip, the input signals of the Vpp logic are not yet defined, which can result in a state of the memory chip having such a high current consumption that the chip is damaged or the voltage supply of the overall system breaks down. Thus, a barrier has to be provided between the voltage network N 1 for providing the voltage Vext and the voltage network N 2 for providing the pumped voltage Vpp that protects the voltage network N 2 from a low-impedance connection to the voltage network N 1 during power-up of the memory chip.

In the circuitry shown in FIG. 1 , protection of the voltage network N 2 is obtained by the control circuit SE 0 with the delay circuit VS 0 and the NAND gate S 10 and by the NAND gate S 20 . The voltage Vext generated at the input terminal A 1 is switched via the NAND structure S 10 , whereby the voltage Vext is disconnected from the output terminal O after a fixed time. After a delay time resulting from the NAND gate S 20 , the input terminal E 2 for providing the voltage Vpp is connected to the output terminal O.

For protecting the voltage network N 2 during power-up of the memory, an n-channel field-effect transistor N 10 is connected between the transistor P 10 including the critical well-source diode, and the input terminal E 1 for applying the voltage Vext. A control terminal G 10 of the transistor N 10 is permanently clamped to the voltage Vpp, whereby, in a fully charged Vpp network, the input terminal E 1 for providing the voltage Vext is connected to the output terminal O by the switching unit I 10 . During power-up of the memory chip, however, the voltage Vpp is smaller than the voltage Vext. Thereby, the well-source diode of the transistor P 10 is controlled to be conductive, but the connection between the voltage networks N 1 and N 2 is interrupted, since the gate-source voltage at N 10 is too small.

FIG. 3 shows a further embodiment of an integrated circuit 10 for generating an output signal MUX, which can, for example, be used as a control signal for controlling isolating transistors of an integrated semiconductor memory. Thereby, the output signal MUX is generated with a voltage level lying above a voltage level of the externally provided supply voltage Vext.

The voltage Vext is provided at an input terminal E 1 of the integrated circuit 10 . The voltage Vext can, for example, be an external supply voltage, which is generated by a voltage network N 1 , which is connected to the input terminal E 1 . The input terminal E 1 is connected to an output terminal O of the integrated circuit for generating the output signal MUX via a switching unit I 11 comprising a controllable switch N 31 and a controllable switch P 11 . Further, the integrated circuit has an input terminal E 2 where a voltage Vpp is provided. After power-up of a memory chip, in which the circuit 10 can be integrated, the voltage Vpp has a voltage level lying above the voltage level of the external supply voltage Vext. For generating the voltage Vpp, a voltage network N 2 can be connected to the input terminal E 2 , by which the voltage Vext is pumped to the increased level Vpp. The input terminal E 2 is connected to the output terminal O of the integrated circuit via a switching unit I 21 , which includes a controllable switch P 21 . The controllable switches can be implemented, for example, as field-effect transistors. The voltage Vpp is fed in at a substrate terminal SB 11 of the transistor P 11 as well as at a substrate terminal SB 21 of the transistor P 21 . Therefore, the substrate terminal can, for example, be connected to the input terminal E 2 .

In order to pull the output signal MUX to a lower level, a controllable switch N 21 is provided, which is connected between a terminal B for applying a reference voltage Gnd and the output terminal O. The controllable switches N 31 , P 11 of the switching unit I 11 , the controllable switch P 21 of the switching unit I 21 as well as the controllable switch N 21 can, for example, be implemented as field-effect transistors or as controllable resistors.

A control switch SE 1 is provided for controlling the controllable switch N 31 and the controllable switch P 21 . For controlling the controllable switches N 31 , P 11 of the switching unit I 11 , for controlling the controllable switch P 21 of the switching unit I 21 , and for controlling the controllable switch N 21 , the control signal IN is applied to a control terminal K of the integrated circuit 10 . The control signal IN is supplied to a delay circuit INV 1 , which generates an internal control signal SK 3 on the output side, which is supplied to the control circuit SE 1 . After a further delay by a delay circuit INV 2 , a further internal control signal SK 4 is generated from the internal control signal SK 3 , which is supplied to a further input side of the control circuit SE 1 . Further, the internal control signal SK 4 serves for controlling the controllable switches P 11 and N 21 .

The internal control signal SK 4 is supplied to a delay circuit VS 1 of the control circuit SE 1 . The delay circuit VS 1 comprises several delay members VG 1 , . . . , VG 5 . The delay circuit VS 1 is connected to a terminal A 11 of a logic gate S 21 on the output side. After delaying the internal control signal SK 4 , the delay circuit VS 1 generates an internal control signal SK 2 at the terminal A 11 , which is supplied to the logic gate S 21 . The logic gate is advantageously implemented as NAND gate.

After connecting the states of the internal control signals SK 2 and SK 3 , the NAND gate S 21 generates an internal control signal SK 1 on the output side. The internal control signal SK 1 is supplied to a common control terminal A 01 of the controllable switches N 31 and P 21 . The controllable switches N 31 and P 21 are controlled in dependence on the internal control signal SK 1 .

The mode of operation of the integrated circuit 10 will be illustrated below with regard to FIG. 4 . In FIG. 4 , the waveforms of the control signal IN and the output signal MUX as well as the waveforms of the internal control signals SK 1 at the terminal A 01 , the internal control signal SK 2 at the terminal A 11 , the internal control signal SK 3 at the terminal A 21 , and the internal control signal SK 4 at the terminal A 31 are illustrated.

During a time t 1 , a high level of the control signal IN is applied to the control terminal K. By the high level of the control signal IN, the controllable switches P 11 and P 21 are non-conductive. The controllable switch N 31 is controlled to be conductive. Further, the controllable switch N 21 is controlled to be conductive so that the output signal MUX is pulled to a level of the reference voltage Gnd. At the time t 2 , a state change of the control signal IN is applied to the control terminal K.

At the time t 3 , the internal control signal SK 4 at the control terminal A 31 of the controllable switches P 11 and N 21 changes to a lower signal level. Thereby, the controllable switch N 21 is non-conductive and the controllable switch P 11 is controlled to be conductive. Since the internal control signal SK 1 assumes no state change, the controllable switch N 31 remains controlled to be conductive and the controllable switch P 21 remains controlled to be non-conductive. Thus, the output terminal O is connected to the input terminal E 1 for applying the external supply voltage Vext via the controllable switches P 11 and N 31 . Thereby, the level of the output signal MUX increases slowly.

At the time t 4 , the control circuit SE 1 generates a state change of the internal control signal SK 1 at the NAND gate S 21 on the output side. By the low level of the internal control signal SK 1 , the controllable switch N 31 is controlled to be non-conductive. The controllable switch P 21 is controlled to be conductive. The controllable switch P 11 remains controlled to be conductive. Since the controllable switch N 31 is controlled to be non-conductive when the controllable switch P 21 is controlled to be conductive, no delay occurs when charging the output terminal O. The charging process at the output terminal is continued by the connection of the input terminal E 2 to the output terminal O. Thus, the level of the output signal MUX increases further until the output terminal O has the increased voltage level Vpp. The increased level of the output signal MUX can be used for controlling isolated transistors of an integrated semiconductor memory to be conductive.

At the time t 5 , a state change of the control signal IN is applied to the control terminal K. Thereby, the controllable switches P 11 and P 21 are controlled to be non-conductive, and the controllable switch N 31 is again controlled to be conductive. Through the controllable switch N 21 controlled to be conductive, the output terminal O is connected to the terminal B for applying the reference voltage Gnd, and can thus discharge. Since the controllable switch N 31 is already controlled to be conductive, it is made possible to connect the input terminal E 1 to the output terminal O via the controllable switch P 11 without delay during subsequent charging of the output terminal O.

In the embodiment of the integrated circuit 10 shown in FIG. 3 , the driver circuit P 11 is no longer non-conductive when the driver circuit P 21 is controlled to be conductive, but remains permanently controlled to be conductive as long as the output signal MUX is held on the voltage level Vpp. Thus, no pulser circuit for controlling the driver circuit P 11 is necessitated. However, for disconnecting the external voltage network N 1 from the voltage network N 2 , the controllable switch N 31 is used instead. The controllable switch N 31 has a common control terminal A 01 with the controllable switch P 21 . The two controllable switches N 31 and P 21 are controlled by the same internal control signal SK 1 . Thereby, the voltage network N 2 is connected to the output terminal O via the controllable switch P 21 in a delayed manner with regard to the voltage network N 1 .

Since in the embodiment shown in FIG. 3 , the controllable switch N 31 is a field-effect transistor of the n-channel type, the controllable switch P 21 is a field-effect transistor of the p-channel type, the controllable switch N 31 is non-conductive when the controllable switch P 21 is controlled to be conductive. Thus, when switching the voltage networks for providing the voltage Vext and the voltage Vpp on and off, no delay occurs.

When the output signal MUX is again pulled to the reference voltage Gnd, for example, to isolate a bit line pair from a read amplifier, the driver circuit P 11 and the driver circuit P 21 are controlled to be non-conductive by the internal control signal SK 4 and the internal control signal SK 1 , respectively. Thereby, the controllable switch N 31 is controlled to be conductive. Thereby, becoming impossible to switch the voltage network N 1 for providing the external supply voltage Vext to the output terminal O without delay by controlling the driver circuit P 11 to be conductive, during the next connection of the read amplifier to the connected bit line pair.

Further, the controllable switch N 31 takes on the protection of the voltage network N 2 for providing the increased voltage Vpp from a low-impedance connection with the voltage network N 1 for providing the external supply voltage Vext. Such protection is particularly necessitated during power-up of the circuit 10 and during power-up of a memory chip in which the circuit 10 is integrated, respectively. Since the voltage level of the internal control signal SK 1 at the terminal A 01 is undefined at first during power-up of the integrated circuit, two cases are distinguished.

In the first case, it is assumed that the terminal A 01 is pulled to a voltage close to the reference voltage Gnd, for example, to a ground potential, by the NAND gate S 21 . In this case, the controllable switch N 31 is controlled to be non-conductive. The well-source diode of the controllable switch P 11 is opened, but disconnected from the terminal E 1 for applying the external supply voltage Vext by the controllable switch N 31 controlled to be non-conductive. Thereby, it is avoided that leakage current flows from the voltage network N 2 into the voltage network N 11 .

In the second case, it is assumed that the NAND gate S 21 pulls the terminal A 01 to the increased voltage potential Vpp. In this case, the controllable switch N 31 is controlled to be non-conductive, as long as the level of the voltage Vpp generated by the voltage network N 2 lies below the level of the external supply voltage Vext generated by the voltage network N 1 , since the gate-source voltage is too small. When the voltage level Vpp provided by the voltage network N 2 is already higher than the external voltage level Vext, the controllable switch N 31 is controlled to be conductive, but in this case the well-source diode of the controllable switch P 11 is controlled to be non-conductive.

Compared to the embodiment of the integrated circuit 1 shown in FIG. 1 , about 20% of the overall circuit area of the integrated circuit is saved in the embodiment of the integrated circuit 10 illustrated in FIG. 10 , since the NAND gate S 10 for controlling the controllable switch P 11 , as well as the controllable switch N 10 , are omitted. Further, the voltage network for providing the external supply voltage Vext is disconnected without delay, and the voltage network N 2 for providing the voltage Vpp is connected without delay. Thereby, the charging process for charging the output terminal O by the voltage network N 1 is only interrupted when the charging process is continued by the voltage network N 2 . Thereby, the charging time for generating the output signal MUX with the increased voltage level Vpp at the output terminal O is reduced.

FIG. 5 shows a further embodiment of the integrated circuit 10 . Here, the same circuit parts as in FIG. 3 are provided with the same reference numbers. Particularly, FIG. 5 shows an inner connection of the NAND gate S 21 . The NAND gate S 21 comprises a controllable switch T 1 connected between the input terminal E 2 and the terminal A 01 . Further, a series connection of controllable switches T 2 and T 3 is connected between the terminal A 01 and a terminal B for applying a reference voltage Gnd.

The controllable switch T 1 is, for example, implemented as a field-effect transistor of the p-channel type, whereas the controllable switches T 2 and T 3 can be implemented as field-effect transistors of the n-channel type. The control terminals of the transistors T 1 and T 2 are connected to the terminal A 21 , to which the internal control signal SK 3 is supplied. The transistor T 3 is controlled by the internal control signal SK 2 , which is generated by the delay circuit VS 1 . Since no glitch occurs at the terminal A 01 in the time t 2 of FIG. 4 , and thus the driver circuit P 21 remains securely non-conductive, providing a second field-effect transistor of the p-channel type connected to the transistor T 1 in series with the terminal E 2 is not necessitated for realizing the NAND gate S 21 . Since typical switching times for connecting the voltage networks N 1 and N 2 to the output terminal O are in the nanosecond range, lowering of the potential at the terminal A 01 by leakage current is not critical and the terminal A 01 can remain in a floating potential state during the switching time.

FIG. 6 shows a further embodiment of an integrated circuit 20 for generating the output signal MUX. Contrary to the embodiment shown in FIG. 5 , an internal control signal SK 2 ′ for controlling the transistor T 3 of the NAND gate S 21 is not derived from the control signal IN, but generated by feedback of the output signal MUX to a control circuit SE 2 . The output signal MUX is delayed by a delay circuit VS 2 of the control circuit SE 2 comprising the delay members VG 1 , . . . , VG 4 and provided as the internal control signal SK 2 ′ at the terminal A 11 .

In this switching variation, the voltage network N 1 for providing the external supply voltage Vext remains connected to the output terminal O until the level of the output signal MUX has risen to a defined value, so that the voltage network N 1 can be disconnected and the voltage network N 2 can be connected. Thereby, it becomes possible to derive the load carried by the voltage network N 1 in a flexible manner from the charging speed at the output terminal O.

If, for example, a long conductive trace LB with a heavy load L 1 , L 2 , . . . , Ln distributed across the line is connected to the output terminal O, a feedback path RP, through which the output signal MUX is supplied to the control circuit, can also, for example, be connected to a terminal O′ at the end of the conductive trace LB. Thereby, it is avoided that the voltage network N 2 for providing the voltage Vpp is already connected to the output terminal O when the voltage at the output terminal O has a sufficient level, but the voltage at the end of the conductive trace LB still has a lower level.

Since the typical starting voltages of the n-channel transistors of the NAND gate S 2 lie below a voltage level of the external supply voltage Vext, or for balancing out RC time constants of the output signal MUX, respectively, an additional delay can be provided between the output terminal O and the terminal A 11 of the NAND gate S 2 . This additional delay is effected, for example, by the delay members VG 1 , . . . , VG 4 of the delay circuit VS 2 .

FIG. 7 shows signal states of the control signal IN, the output signal MUX, as well as the internal control signals SK 1 , SK 2 ′, SK 3 and SK 4 at the terminals A 01 , A 11 , A 21 and A 31 in the circuit 20 illustrated in FIG. 6 . The signal diagram is similar to the signal diagram of FIG. 4 . The arrow indicates the dependence of the rising edge of the internal control signal SK 2 ′ at the terminal A 11 from the waveform of the output signal MUX. In the waveforms shown in FIG. 7 , no glitch occurs at the terminal A 01 . Thus, even in this implementation of the integrated circuit, a second field-effect transistor of the p-channel type can be omitted in the structure of the NAND gate S 21 .

FIG. 8 shows a memory chip 100 , where the integrated circuit 1 , 10 , 20 is used for generating an output signal MUX. The output signal MUX serves as a control signal for controlling an isolating transistor 12 connecting a read amplifier 11 to a bit line BL. The read amplifier 11 and the isolating transistor 12 are arranged in a memory cell field 30 . The memory cell field 30 has a plurality of memory cells SZ, which are connected between bit lines BL and word lines WL.

The memory cells SZ can, for example, be DRAM (dynamic random access memory) memory cells. A DRAM memory cell SZ, illustrated exemplarily in FIG. 8 , has a memory capacitor SC that is connected to the bit line BL via a controllable switch, for example, a selection transistor AT. For reading out the memory cell SZ or for writing a data value into the memory cell SZ, respectively, the memory cell SZ is activated by a corresponding control signal on the word line WL and connected to the bit line BL to be conductive.

During memory access to memory cells connected to the bit line BL, the integrated circuit 1 , 10 , 20 generate the output signal MUX at its output terminal O, which is supplied to a control terminal S 12 of the isolating transistor 12 . By the increased level of the control signal, the isolating transistor is controlled to be conductive, so that the bit line BL is connected to the read amplifier 11 .

For generating the increased voltage level Vpp, the output signal MUX provided by the circuit 1 , 10 or 20 , respectively, is first raised to the level of the external supply voltage Vext by the voltage network N 1 and then to the level of the increased voltage Vpp. The external supply voltage Vext can be supplied to the semiconductor memory, for example, at a supply terminal V. It is also possible that the voltage Vext is generated on the memory chip of the semiconductor memory from an externally supplied voltage by a voltage network N 1 , which includes, for example, a voltage generator circuit. The increased voltage level Vpp is generated, for example, by the voltage network N 2 , which can include a pump circuit. The integrated circuit ensures, particularly during power-up of the memory chip, that no low-impedance connection between the voltage network N 1 for providing the voltage Vext and the voltage network N 2 for providing the voltage Vpp is caused by the integrated circuit 1 , 10 , 20 .

While this invention has been described in terms of several advantageous embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.