Switching regulator configured to detect and shutdown reverse current

The present disclosure relates to a switching regulator, and more particularly, to a switching regulator capable of preventing reverse current.

Recently, energy saving has been actively promoted to protect the environment. For battery-powered portable equipment, such as mobile phones, digital cameras, and the like, energy efficiency is especially important to prolong battery life. Such portable equipment typically uses a switching regulator that includes an inductor because it is efficient and can be made compact.

FIG. 1 is a circuit diagram of a known switching regulator. The switching regulator 100 is a step-down synchronous-rectification type switching regulator. In FIG. 1 , the switching regulator 100 includes a switching transistor S 101 , a synchronous rectification transistor S 102 , an inductor L 101 , an output capacitor C 101 , comparators 103 , 105 , and 107 , an oscillator 104 , an output driver 106 , and bleeder resistors R 101 and R 102 . A load 110 is connected between an output terminal OUT (Vout) and ground.

The switching regulator 100 operates in a continuity mode and a discontinuity mode. In the continuity mode, a current flows through the inductor L 101 continuously. By contrast, in the discontinuity mode, the current does not flow through the inductor L 101 continuously. Consequently, when the switching regulator operates in the discontinuity mode under light load conditions, a reverse current may flow from the output,terminal OUT to ground through the synchronous rectification transistor S 102 .

To avoid such reverse current, the switching regulator 100 employs the comparator 107 which compares a voltage VLx at a junction node Lx between the switching transistor S 101 and the synchronous rectification transistor S 102 with a ground potential GND. When the voltage VLx at the junction node Lx exceeds the ground potential GND, the synchronous rectification transistor S 102 is cut off so that the reverse current is avoided.

However, in the switching regulator 100 shown in FIG. 1 , the synchronous rectification transistor S 102 may not be cut off before generation of the reverse current due to a delay at the comparator 107 , resulting in the reverse current flowing from the output terminal OUT to the inductor L 101 . As a result, performance efficiency of the switching regulator decreases.

The ground potential GND input to inverted input terminal of the comparator 107 may be replaced by a low voltage that is lower than the ground potential GND by a predetermined voltage. Then, the comparator 107 compares the voltage VLx at the junction node Lx with the low voltage so as to detect an indication of the reverse current. Accordingly, it is possible to cut off the synchronous rectification transistor S 102 before generation of the reverse current, thus avoiding the reverse current. In this switching regulator 100 , however, a voltage change of the voltage VLx at the junction node Lx is relatively small with respect to time. Accordingly, it takes a long time to obtain enough of a voltage change to cause the comparator 107 to invert the output voltage thereof. To cause the comparator 107 to invert the output voltage with such small voltage change, it is necessary to increase a supply current to the comparator 107 . When the supply current to the comparator 107 is increased, however, the performance efficiency of the switching regulator 100 decreases due to large power consumption under light load conditions.

This patent specification describes a novel switching regulator that includes a first switch, an inductor, a second switch, a controller to control a switching operation by switching the first switch and switching the second switch complementally to the first switch, and a reverse current detector to detect a reverse current that flows from an output terminal toward the second switch. The reverse current detector generates a proportional voltage that is proportional to a voltage at a junction node between the second switch and the inductor, and detects a generation or an indication of the reverse current based on the proportional voltage. The controller turns the second switch off to create a shutdown state when the reverse current detector detects the generation or the indication of the reverse current.

This patent specification further describes a novel switching regulator that includes a reverse current detector. The reverse current detector compares a proportional voltage with a reference voltage to detect a generation or an indication of a reverse current.

A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is circuit diagram of a known switching regulator;

FIG. 2 a circuit diagram of a switching regulator according to a first example embodiment;

FIG. 3 is circuit diagram of a proportional voltage generator of FIG. 2 ;

FIG. 4 is a schematic representing a relation among a proportional voltage, a reference voltage, and a voltage at a junction node between a switching transistor and a synchronous rectification transistor in the switching regulator according to the first example embodiment;

FIG. 5 is another switching regulator according to the first example embodiment;

FIG. 6 is a circuit diagram of a switching regulator according to a second example embodiment;

FIG. 7 is a schematic diagram representing a relation among a proportional voltage, a reference voltage, and a voltage at a junction node between a switching transistor and a synchronous rectification transistor in the switching regulator according to the second example embodiment;

FIG. 8 is a circuit diagram of a reference voltage generation circuit;

FIG. 9 is a circuit diagram of a switching regulator according to a third example embodiment;

FIG. 10 is a schematic representing a relation among a proportional voltage, a reference voltage, and a voltage at a junction node between a switching transistor and a synchronous rectification transistor in the switching regulator according to the third example embodiment;

FIG. 11 is another example of a proportional voltage generation circuit;

FIG. 12 is another example of a proportional voltage generation circuit using an NMOS transistor; and

FIG. 13 is another example of a proportional voltage generation circuit using a PMOS transistor.

In describing preferred embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner and achieve a similar result.

Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, particularly to FIG. 2 , a switching regulator according to exemplary embodiment is described.

First Embodiment

FIG. 2 is a circuit diagram of a switching regulator according to a first example embodiment. The switching regulator 1 is a step-down switching regulator that converts an input voltage Vin input at an input terminal IN to a predetermined voltage, and outputs the converted voltage as an output voltage Vout from an output terminal OUT to a load 10 . The switching regulator 1 includes a switching transistor S 1 and a synchronous rectification transistor S 2 . The switching transistor S 1 is a PMOS transistor, and performs a switching operation to control output of the input voltage Vin. The synchronous rectification transistor S 2 is an NMOS transistor.

Further, the switching regulator 1 includes a first reference voltage generator 2 , resistors R 1 and R 2 , an inductor L 1 , an error amplifier 3 , an oscillator 4 , a PWM comparator 5 , a control circuit 6 , and a reverse current detector 7 . The resistors R 1 and R 2 detect the output voltage Vout, and the control circuit 6 controls the switching transistor S 1 and the synchronous rectification transistor S 2 . The reverse current detector 7 includes a proportional voltage generator 11 , a second reference voltage generator 12 and a comparator 13 .

The switching transistor S 1 forms a first switching element, and the synchronous rectification transistor S 2 forms a second switching element. The first reference voltage generator 2 , the resistors R 1 and R 2 , the inductor L 1 , the error amplifier 3 , the oscillator 4 , the PWM comparator 5 and the control circuit 6 together form a control circuit unit. The reverse current detector 7 forms a reverse current detection circuit unit. Further, the second reference voltage generator 12 forms a second reference voltage generation circuit unit, and the comparator 13 forms a reverse current detection circuit.

Excepting the inductor L 1 and a capacitor C 1 , all the circuit elements may be integrated on a single chip. Further, excepting switching transistor S 1 , the synchronous rectification transistor S 2 , the inductor L 1 and a capacitor C 1 , all the circuit elements may be integrated on a single chip.

The first reference voltage generator 2 generates and outputs a predetermined first reference voltage Vref 1 . The resistors R 1 and R 2 generate a divided voltage Vfb by dividing the output voltage Vout, and outputs the divided voltage Vfb. The error amplifier 3 amplifies a voltage difference between the divided voltage Vfb and the first reference voltage Vref 1 to generate and output an output signal EAo. The oscillator 4 generates and outputs a predetermined triangular wave signal TW. The PWM comparator 5 compares the output signal EAo with the triangular wave signal TW to generate and output a PWM pulse signal Spwm to perform a PWM control.

The control circuit 6 turns on either the switching transistor S 1 or the synchronous rectification transistor S 2 exclusively in accordance with the PWM pulse signal Spwm.

The reverse current detector 7 detects an indication of a reverse current that flows from the output terminal OUT to the synchronous rectification transistor S 2 . When the reverse current detector 7 detects an indication of the reverse current, the reverse current detector 7 outputs a predetermined signal Vdet to the control circuit 6 . The control circuit 6 turns the synchronous rectification transistor S 2 off to create a shutdown state so that the reverse current is prevented.

The switching transistor S 1 and the synchronous rectification transistor S 2 are connected in series between the input terminal IN and ground. The inductor L 1 is connected between the output terminal OUT and a junction node Lx between the switching transistor S 1 and the synchronous rectification transistor S 2 . Between the output terminal OUT and ground, the resistors R 1 and R 2 are connected in series and the capacitor C 1 is connected in parallel. The divided voltage Vfb is output from a junction node between the resistors R 1 and R 2 . In the error amplifier 3 , the divided voltage Vfb is input to a non-inversion terminal, and the first reference voltage Vref 1 is input to an inversion terminal. An output terminal of the error amplifier 3 is connected to a non-inversion terminal of the PWM comparator 5 .

The triangular wave signal TW is input to an inversion terminal of the PWM comparator 5 . The PWM pulse signal Spwm output from the PWM comparator 5 is input to the control circuit 6 . The control circuit 6 outputs control signals to each gate of the switching transistor S 1 and the synchronous rectification transistor S 2 for operational control thereof.

The voltage VLx at the junction node Lx between the switching transistor S 1 and the synchronous rectification transistor S 2 is input to the proportional voltage generator 11 so that the proportional voltage generator 11 generates and outputs a proportional voltage Vs 1 that is proportional to the voltage VLx. The second reference voltage generator 12 generates and outputs a predetermined second reference voltage Vref 2 . In the comparator 13 , the proportional voltage Vs 1 is input to a non-inversion terminal and the second reference voltage Vref 2 is input to an inversion terminal. The comparator 13 generates and outputs a comparison result signal Vdet indicating a comparison result between the proportional voltage Vs 1 and the second reference voltage Vref 2 to the control circuit 6 .

With this circuit configuration, when the proportional voltage Vs 1 is below the second reference voltage Vref 2 , i.e., there is no indication of the reverse current from the node Lx to ground, and the comparator 13 outputs a low-level comparison result signal Vdet. Under these condition, when the output voltage Vout is increased, the output signal EAo of the error amplifier 3 decreases so that a pulse width of the PWM pulse signal Spwm output from the PWM comparator 5 changes. More specifically, the on-time of the switching transistor S 1 decreases, and the on-time of the synchronization rectification transistor S 2 increases. Consequently, the output voltage Vout of the switching regulator 1 is decreased.

When the output voltage Vout of the switching regulator 1 decreases, the output signal EAo of the error amplifier 3 increases. Further, the pulse width of the pulse signal Spwm from the PWM comparator 5 changes. More specifically, the on-time of the switching transistor S 1 increases, and the on-time of the synchronization rectification transistor S 2 decreases. Consequently, the output voltage Vout of the switching regulator 1 is increased.

The above operations are repeated so that the output voltage Vout is maintained at a predetermined constant voltage.

When an indication of the reverse current is detected, for example, when the proportional voltage Vs 1 is higher than the second reference voltage Vref 2 , the comparator 13 outputs a high-level comparison result signal Vdet. The control circuit 6 then switches off the synchronization rectification transistor S 2 to create a shutdown state independently of the pulse signal Spwm input from the PWM comparator 5 .

FIG. 3 is a circuit diagram of the proportional voltage generator 11 of FIG. 2 . Referring to FIG. 3 , operation of the proportional voltage generator 11 will be described.

The proportional voltage generator 11 includes an operational amplifier 17 , an NMOS transistor M 1 , PMOS transistors M 2 and M 3 , and resistors R 3 and R 4 . The NMOS transistor M 1 forms a first transistor, the resistor R 3 forms a first resistor, and the resistor R 4 forms a second resistor. The PMOS transistors M 2 and M 3 form a current mirror circuit. Each source of the PMOS transistors M 2 and M 3 is connected to an input terminal IN which inputs an input voltage Vin, and each gate is connected in common and is connected to a drain of the PMOS transistor M 2 .

The NMOS transistor M 1 and the resistor R 3 are connected in series between the drain of the PMOS transistor M 2 and the junction node Lx. A junction node between the NMOS transistor M 1 and the resistor R 3 is connected to an inversion terminal of the operational amplifier 17 . A non-inversion terminal of the operational amplifier 17 is connected to ground. An output terminal of the operational amplifier 17 is connected to a gate of the NMOS transistor M 1 . The resistor R 4 is connected between a drain of the PMOS transistor M 3 and ground. The proportional voltage Vs 1 is output from a junction node between the PMOS transistor M 3 and the resistor R 4 .

Where a voltage at a junction node between the NMOS transistor M 1 and the resistor R 3 is “Va”, a voltage across the resistor R 3 is expressed as (Va−VLx). Accordingly, a current i 1 flowing from the PMOS transistor M 2 to the NMOS transistor M 1 and the resistor R 3 is expressed as

i 1=( Va−VLx )/ r 3   (1)

where resistance of the resistor R 3 is r 3 .

A current i 2 output from the PMOS transistor M 3 is expressed as

i 2 =i 1 ×gm 3 /gm 2=( gm 3 /gm 2)×( Va−VLx ) /r 3   (2)

where transconductance of the PMOS transistors M 2 is gm 2 and transconductance of the PMOS transistors M 3 is gm 3 .

The transconductance gm is generally expressed as gm=μ×Cox×W/L×(Vgs−Vth), where mobility of the MOS transistor is μ, capacitance of gate oxide is Cox, gate width is W, gate length is L, and threshold voltage is Vth.

Accordingly, the proportional voltage Vs 1 is expressed as

Vs 1 =i 2 ×r 4=( Va−VLx )×( gm 3 /gm 2)×( r 4 /r 3)   (3)

where resistance of the resistor R 4 is r 4 .

The operational amplifier 17 controls the NMOS transistor M 1 so that the voltage Va becomes the ground potential GND, i.e., Va=0. Therefore, formula (3) can be rewritten as

Vs 1 =k ×(− VLx )=− k ×( VLx )   (4)

where K=(gm 3 /gm 2 )×(r 4 /r 3 ). Thus, the proportional voltage generator 11 outputs the proportional voltage Vs 1 obtained by multiplying the voltage VLx by a factor −k. Further, |k|>1.

FIG. 4 is a schematic diagram representing a relation among the voltage VLx, the proportional voltage Vs 1 , and the second reference voltage Vref 2 .

In FIG. 4 , at time t 1 , the switching transistor S 1 is off and the synchronous rectification transistor S 2 is on. Accordingly, the voltage VLx drops to a low voltage that is lower than the ground potential GND so that a current flows from ground to the node Lx. Energy stored in the inductor L 1 discharges because the synchronous rectification transistor S 2 is on. Accordingly, the voltage VLx increases. In FIG. 4 , the proportional voltage Vs 1 output from the proportional voltage generator 11 is shown by a bold solid line. It is found that the bold solid line is obtained from the voltage VLx. A dotted line is created by making a line symmetry of the voltage VLx about the ground potential GND. Then, the factor k is multiplied to the dotted line so as to obtain the bold solid line, i.e., Vs 1 .

To detect the reverse current at time t 2 , the second reference voltage Vref 2 is determined so that a magnitude relation between the proportional voltage Vs 1 and the second reference voltage Vref 2 at time t 2 becomes the reverse of the magnitude relation at time t 1 . More specifically, the proportional voltage Vs 1 becomes lower than the second reference voltage Vref 2 after time t 2 . Since a slope m 1 of the line of the voltage VLx is generally expressed by the following formula:

m 1 =R on×(− V out/ L )   (5)

where on-resistance of the synchronous rectification transistor S 2 is Ron, and inductance of the inductor L 1 is L, a slope m 2 of the line of the proportional voltage Vs 1 is obtained by multiplying the slope ml by the factor −k, as follows:

m 2 =−k×R on×(− V out/ L )   (6)

In the known switching regulator 100 shown in FIG. 1 , the slope of the line of the voltage VLx is relatively small with respect to time. Accordingly, an input error voltage input at each terminal of the comparator 107 is relatively small. As a result, it takes a long time for the output voltage of the comparator 107 to be inverted by the input error voltage of the comparator 107 .

When a necessary input error voltage of the comparator 107 to cause the comparator 107 to invert the output voltage is defined as Verr, a delay time T dly1 until the comparator 107 inverts the output voltage may be expressed as

T dly1 =Verr/|m 1|  (7)

When the delay time T dly1 is long, it is not possible to prevent the reverse current in advance before it occurs, resulting in reduced performance efficiency of the switching regulator.

In the switching regulator according to the first example embodiment, when a necessary input error voltage that causes the comparator 13 to invert the output voltage Vdet is defined as Verr, a delay time T dly2 until the output voltage Vdet is inverted is expressed as

T dly2 =Verr/|m 2|  (8)

Since |m 2 |=k×|m 1 | based on the formulas (5) and (6), the formula (8) becomes

T dly2 =Verr/|m 1| /k   (9)

Referring now to formula (9), it can be seen that the delay time is reduced by 1/k compared to formula (7) for the known switching regulator.

In the switching regulator according to the first example embodiment as shown in FIG. 2 , the switching regulator 1 employs the second reference voltage generator 12 that generates the second reference voltage Vref 2 . However, as shown in FIG. 5 , the first reference voltage Vref 1 may be used instead of the second reference voltage Vref 2 . Accordingly, the first reference voltage Vref 1 is input to the inverted input terminal of the comparator 13 . As a result, it is possible to simplify the circuit configuration because the second reference voltage generator 12 is not necessary, resulting in cost reduction.

As described above, in the switching regulator according to the first example embodiment, it is possible to shorten the delay time caused by the comparator 13 , to shorten a required time to detect a generation of the reverse current, and to start a preventing operation to prevent the reverse current quickly when the reverse current does occur. Further, it is possible to prevent the reverse current from occurring in the first place. Consequently, it is possible to reduce power consumption of the comparator 13 , resulting in even better performance efficiency of the switching regulator.

Second Embodiment

In the switching regulator according to the first example embodiment, the second reference voltage Vref 2 is input to the inversion terminal of the comparator 13 . However, in a switching regulator according to a second example embodiment, a reference voltage Vs 2 , which is obtained by adding a predetermined voltage V 1 to the voltage VLx, is used for input to the inversion terminal of the comparator 13 .

FIG. 6 is a circuit diagram of the switching regulator 1 a according to the second example embodiment. In FIG. 6 , identical reference characters are assigned to circuit members that are identical or similar to those shown in FIG. 2 and descriptions thereof are omitted.

The switching regulator 1 a shown in FIG. 6 differs from the switching regulator 1 shown in FIG. 2 in that the second reference voltage generator 12 is removed and a reference voltage generator 21 is provided between the inversion terminal of the comparator 13 and the junction node Lx. Accordingly, the reverse current detector 7 is changed to a reverse current detector 7 a.

The switching regulator 1 a is a step-down switching regulator which converts an input voltage Vin input at an input terminal IN to a predetermined voltage, and outputs the converted voltage as an output voltage Vout from an output terminal OUT to a load 10 . The switching regulator 1 a includes a switching transistor S 1 , a synchronous rectification transistor S 2 , a first reference voltage generator 2 , resistors R 1 and R 2 , an inductor L 1 , an error amplifier 3 , an oscillator 4 , a PWM comparator 5 , a control circuit 6 , and the reverse current detector 7 a . The reverse current detector 7 a forms a reverse current detection circuit unit. The reference voltage generation circuit 21 forms a second reference voltage circuit unit, and the reference voltage Vs 2 forms a second reference voltage.

Excepting the inductor L 1 and a capacitor C 1 , all the circuit elements may be integrated on a single chip. Further, excepting switching transistor S 1 , the synchronous rectification transistor S 2 , the inductor L 1 and a capacitor C 1 , all the circuit elements may be integrated on a single chip.

The reverse current detector 7 a detects an indication of a reverse current that flows from the output terminal OUT to the synchronous rectification transistor S 2 . When the reverse current detector 7 a detects an indication of a reverse current, the reverse current detector 7 a outputs a predetermined comparison result signal Vdet to the control circuit 6 . The control circuit 6 switches off the synchronous rectification transistor S 2 to create a shutdown state so as to prevent the reverse current.

In the comparator 13 , the proportional voltage Vs 1 is input to a non-inversion terminal, and the reference voltage Vs 2 is input to an inversion terminal. The comparator 13 generates the comparison result signal Vdet, and outputs the comparison result signal Vdet indicating a comparison result between the proportional voltage Vs 1 and the reference voltage Vs 2 to the control circuit 6 .

FIG. 7 is a schematic diagram representing a relation among the voltage VLx, the proportional voltage Vs 1 , and the reference voltage Vs 2 with this circuit configuration. A slope of the line of the reference voltage Vs 2 (=VLx+V 1 ) input to the non-inversion terminal of the comparator 13 is m 1 . Accordingly, when a necessary input error voltage with which the comparator 13 inverts the output voltage is defined as Verr, a delay time T dly3 until the comparator 13 inverts the output voltage is

T dly3 =Verr /(| m 2 |+|m 1|)   (10)

Since |m 2 |=k×|m 1 | based on formulas (5) and (6), the formula (10) becomes a following formula (11),

T dly3 =Verr/|m 1|/( k+ 1)   (11)

Referring now to formula (11), it can be seen that the delay time can be reduced by 1/(k+1) compared to formula (7).

The reference voltage generation circuit 21 can be implemented using a simple circuit like that shown in FIG. 8 . In FIG. 8 , the reference voltage generation circuit 21 includes a constant current source 25 and a resistor R 5 . The constant current source 25 generates a predetermined constant current i 3 . The constant current source 25 and the resistor R 5 are connected in series between the input terminal IN and the junction node Lx. The reference voltage Vs 2 is output from a junction node between the constant current source 25 and the resistor R 5 . Since a current i 3 flows through the resistor R 5 , a voltage (i 3 ×r 5 ) is generated where the resistance of the resistor R 5 is r 5 . Accordingly, the reference voltage Vs 2 becomes a summation of the voltage VLX and the voltage (i 3 ×r 5 ), and is expressed by the following (12)

Vs 2 =VLx+i 3 ×r 5   (12)

When the voltage (i 3 ×r 5 ) is defined as a predetermined voltage V 1 , formula (12) becomes

Vs 2 =VLx+V 1   (13)

Thus, in the switching regulator according to the second example embodiment, the reference voltage generation circuit 21 generates the reference voltage Vs 2 by adding a predetermined voltage V 1 to the voltage VLx, and the reference voltage Vs 2 is input to the inverted input terminal of the comparator 13 . As a result, the switching regulator according to the second example embodiment can shorten a delay time caused by the comparator 13 in addition to providing an effect similar to that of the switching regulator according to the first example embodiment. Further, it is possible to shorten a required time to detect a generation of the reverse current, and to start a preventing operation to prevent the reverse current quickly when the reverse current starts to occur.

Third Embodiment

In the switching regulator according to the first example embodiment, the proportional voltage generator 11 generates and outputs a proportional voltage Vs 1 proportional to the voltage VLx. In a switching regulator according to a third example embodiment, a proportional voltage Vs 3 is created by multiplying the voltage VLx by a factor k, and a negative reference voltage −Vref 3 is input to the inversion terminal of the comparator 13 .

FIG. 9 is a circuit diagram of a switching regulator 1 b according to the third example embodiment. In FIG. 9 , identical reference characters are assigned to circuit members that are identical or similar to those shown in FIG. 2 and descriptions thereof are omitted.

The switching regulator 1 b shown in FIG. 9 differs from the switching regulator 1 shown in FIG. 2 in that the proportional voltage generator 11 is replaced by a proportional voltage generator 31 which generates and outputs the proportional voltage Vs 3 which is created by multiplying the voltage VLx by the factor k. Further, the second reference voltage generator 12 is replaced by a third reference voltage generator 32 which generates and outputs a predetermined negative reference voltage −Vref 3 . Accordingly, the reverse current detector 7 is changed to a reverse current detector 7 b.

The switching regulator 1 b is a step-down switching regulator which converts an input voltage Vin input at an input terminal IN to a predetermined voltage, and outputs the converted voltage as an output voltage Vout from an output terminal OUT to a load 10 .

The switching regulator 1 b includes a switching transistor SI, a synchronous rectification transistor S 2 , a first reference voltage generator 2 , resistors R 1 and R 2 , an inductor L 1 , an error amplifier 3 , an oscillator 4 , a PWM comparator 5 , a control circuit 6 , and the reverse current detector 7 b . The reverse current detector 7 b includes the proportional voltage generator 31 , the third reference voltage generator 32 , and a comparator 13 . The reverse current detector 7 b forms a reverse current detection circuit unit, and the third reference voltage generator 32 forms a third reference voltage generation circuit.

Excepting the inductor L 1 and a capacitor C 1 , all the circuit elements may be integrated on a single chip. Further, excepting switching transistor S 1 , the synchronous rectification transistor S 2 , the inductor L 1 and a capacitor C 1 , all the circuit elements may be integrated on a single chip.

The reverse current detector 7 b detects an indication of a reverse current that flows from the output terminal OUT to the synchronous rectification transistor S 2 . When the reverse current detector 7 b detects an indication of a reverse current, the reverse current detector 7 b outputs a predetermined comparison result signal Vdet to the control circuit 6 . The control circuit 6 switches off the synchronous rectification transistor S 2 to create a shutdown state to prevent the reverse current.

In the comparator 13 , the proportional voltage Vs 3 is input to a non-inversion terminal, and the negative reference voltage −Vref 3 is input to an inversion terminal. The comparator 13 generates and outputs the comparison result signal Vdet indicating a comparison result between the proportional voltage Vs 3 and the negative reference voltage −Vref 3 to the control circuit 6 .

FIG. 10 is a schematic diagram representing a relation among the voltage VLx, the proportional voltage Vs 3 and the third reference voltage −Vref 3 . Here, k in FIG. 4 is replaced by −k, and −k in FIG. 4 is replaced by k in FIG. 10 . The proportional voltage Vs 1 is replaced by the proportional voltage Vs 3 , and the second reference voltage Vref 2 is replaced by the third reference voltage −Vref 3 .

In the switching regulator according to the first example embodiment, the proportional voltage Vs 1 is generated by multiplying the voltage VLx by a factor −k. By contrast, in the switching regulator according to the third example embodiment, the proportional voltage Vs 3 is generated by multiplying the voltage VLx by a factor k. Accordingly, the proportional voltage generation circuit 31 can be achieved by a simple circuit.

As a result, the switching regulator according to the third example embodiment can simplify the proportional voltage generation circuit so that the proportional voltage generation circuit can be made compact in addition to providing an effect similar to that of the switching regulator according to the first example embodiment.

Moreover, the proportional voltage generation circuit 11 used in the switching regulators according to the first and second example embodiments is not intended to be limited to the circuit configuration shown in FIG. 3 .

FIG. 11 is another example of the proportional voltage generation circuit. In FIG. 11 , identical reference characters are assigned to circuit members that are identical or similar to those shown in FIG. 3 . The proportional voltage generation circuit 11 includes an operational amplifier 17 , PMOS transistors M 2 and M 3 , resistors R 3 and R 4 . The PMOS transistor M 2 forms a first transistor, and the PMOS transistor M 3 forms a second transistor.

In the PMOS transistors M 2 and M 3 , each source is connected to input terminal IN. Each gate of the PMOS transistors M 2 and M 3 is connected in common, and connected to an output terminal of the operational amplifier 17 . The resistor R 3 is connected between a drain of the PMOS transistor M 2 and the node Lx. A junction node between the PMOS transistor M 2 and the resistor R 3 is connected to the non-inversion terminal of the operational amplifier 17 . An inversion terminal of the operational amplifier 17 is connected to ground. The resistor R 4 is connected between a drain of the PMOS transistor M 3 and ground. The proportional voltage Vs 1 is output from a junction node between the PMOS transistor M 3 and the resistor R 4 . A formula representing the proportional voltage Vs 1 of FIG. 10 is equal to the formula for the proportional voltage generation circuit of FIG. 3 .

FIG. 12 is another example circuit of the proportional voltage generation circuit. In FIG. 12 , identical reference characters are assigned to circuit members identical or similar to those shown in FIG. 3 . The proportional voltage generation circuit 11 includes an operational amplifier 17 , an NMOS transistors M 1 , and resistors R 3 and R 4 . A drain of the NMOS transistor M 1 is connected to the input terminal IN. The resistors R 3 and R 4 are connected in series between a source of the NMOS transistor M 1 and the node Lx. A gate of the NMOS transistor M 1 is connected to an output terminal of the operational amplifier 17 . A junction node between the resistors R 3 and R 4 is connected to an inversion terminal of the operational amplifier 17 . A non-inversion terminal of the operational amplifier 17 is connected to ground. The proportional voltage Vs 1 is output from a junction node between the NMOS transistor M 1 and the resistor R 4 .

The NMOS transistor M 1 in FIG. 12 can be replaced by a PMOS transistor M 1 a, and FIG. 13 is another example circuit of the proportional voltage generation circuit 11 using the PMOS transistor M 1 a. In both FIGS. 12 and 13 , a proportional voltage Vs 1 is expressed by the same formula (4) excepting the factor k. The factor k for FIGS. 12 and 13 is r 4 /r 3 (k=r 4 /r 3 ).

The switching regulators according to the first, second, and third example embodiments may be configured so that the proportional voltage generator detects whether or not the synchronous rectification transistor S 2 is turned off to create a shutdown state based on the control signal output from the control circuit. When the synchronous rectification transistor S 2 is turned off, the proportional voltage generator stops operation, or generates and outputs a voltage signal to cause the comparator 13 to output a high-level comparison result signal Vdet.

Numerous additional modifications and variations are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein.

This patent specification is based on Japanese Patent Application, No. 2007-235065 filed on Sep. 11, 2007 in the Japanese Patent Office, the entire contents of which are incorporated by reference herein.