Display data channel interface circuit

1. Field of the Invention

The present invention relates to interface circuits and, particularly, to a display data channel (DDC) interface circuit on a motherboard.

2. Description of the Related Art

DDC is a standard communications channel between a computer and a monitor. A monitor contains a read-only memory (ROM) chip programmed by the manufacturer with information about the graphics modes that the monitor can display. The data in the monitor's ROM is held in a standard format called extended display identification data (EDID). The EDID is a data structure provided by the monitor to describe its capabilities for a graphics card of the computer. With this information, the computer knows what kind of monitor it is connected to. The EDID is defined by the video electronics standards association (VESA). The EDID includes manufacturer name, product type, phosphor or filter type, timings supported by the monitor, monitor size, luminance data and (for digital displays only) pixel mapping data. The EDID information is communicated to the computer over the DDC. The EDID and the DDC enable the computer and the monitor to communicate so that the computer can be configured to support specific features available in the monitor. However, the computer often cannot obtain the EDID because the computer cannot recognize an automatic color killer (ACK) signal output from the monitor.

What is needed, therefore, is a DDC interface circuit which can overcome the above problem.

The FIGURE is a circuit diagram of an embodiment of a DDC interface circuit on a motherboard in accordance with the present invention.

Referring to the FIGURE, a DDC interface circuit 200 on a motherboard in accordance with an embodiment of the present invention includes two N type metal oxide semiconductor (NMOS) transistors Q 1 and Q 2 , and five resistors R 1 , R 2 , R 3 , R 4 , and R 5 .

The gate of the NMOS transistor Q 1 is arranged to receive a system power 3.3V_SYS via the resistor R 1 . The source of the NMOS transistor Q 1 is connected to a display data channel clock (DDC_CLK) pin of a north bridge 100 on the motherboard. The drain of the NMOS transistor Q 1 is arranged to receive a system power 5V_SYS via the resistor R 2 , and also connected to a serial clock (SCL) pin of a video graphics array (VGA) interface 300 on the motherboard via the resistor R 3 . The gate of the NMOS transistor Q 2 is arranged to receive the system power 3.3V_SYS via the resistor R 1 . The source of the NMOS transistor Q 2 is connected to a display data channel data (DDC_DATA) pin of the north bridge 100 . The drain of the NMOS transistor Q 2 is arranged to receive the system power 5V_SYS via the resistor R 4 , and also connected to a serial data (SDA) pin of the VGA interface 300 via the resistor R 5 . The VGA interface 300 is also connected to an automatic color killer (ACK) 10 in a monitor 400 to receive an ACK signal and transmit the ACK signal to the DDC interface circuit 200 .

In the present embodiment, the system power 3.3V_SYS is provided for the gates of the NMOS transistors Q 1 and Q 2 via the resistor R 1 , such that the NMOS transistors Q 1 and Q 2 are turned on. The system power 5V_SYS is provided for the drains of the NMOS transistors Q 1 and Q 2 via the resistors R 2 and R 4 respectively. The resistances of the resistors R 2 and R 4 are all between 9.5 kΩ-10.5 kΩ. The ACK signal output from the ACK circuit 10 in the monitor 400 is transmitted to the north bridge 100 via the VGA interface 300 and the DDC interface circuit 200 . The north bridge 100 recognizes the ACK signal at a valid low level and then transmits a read instruction to the monitor 400 via the DDC interface circuit 200 and the VGA interface 300 . The monitor 400 transmits an extended display identification data (EDID) to the DDC_DATA pin of the north bridge 100 via the VGA interface 300 and the DDC interface 200 . Thereby the north bridge 100 controls the monitor 400 to display accurately according to the EDID. The VGA interface 300 is configured for converting a digital signal from the north bridge 100 to an analog signal to the monitor 400 , and vice versa.

It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.