Internal power-supply circuit

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-207500 filed on Aug. 9, 2007, the entire contents of which are incorporated herein by reference.

1. Technical Field

This is related to internal power-supply circuits having a reference-voltage generating unit in semiconductor integrated circuits.

2. Description of the Related Art

A semiconductor integrated circuit, for example, a DRAM, has an internal power-supply circuit for generating a internal power-supply step-down voltage from an externally supplied power-supply voltage Vdd, in order to achieve both high speed operation and low power consumption. The internal power-supply step-down voltage causes an internal circuit to operate. The internal power supply circuit also generates an internal power-supply step-up voltage and a bias voltage for current sources, which voltages are higher than the externally supplied power-supply voltage Vdd. It is required that internal voltages generated by the internal power-supply circuit, i.e., an internal power-supply step-up voltage, an internal power-supply step-down voltage, a bias voltage, and so on, have desired potentials. Accordingly, the internal power-supply circuit generates a desired reference voltage from the externally supplied power-supply voltage Vdd, and generates the internal voltages based on the reference voltage.

The internal power-supply step-down voltage is supplied to a peripheral circuit of the DRAM and is also supplied to a memory core having a memory cell array. The internal power-supply step-up voltage is supplied to the memory core. The current-source-bias voltage is supplied to current-source transistors of voltage-detection differential amplifier circuits and a delay circuit in the peripheral circuit to cause the current-source transistors to generate desired currents.

During power up, the internal power-supply circuit monitors the rising of the externally supplied power-supply voltage Vdd, and upon detecting the rising, the internal power-supply circuit starts a reference-voltage generating unit. After a reference voltage is generated, the internal power-supply circuit starts an internal-voltage generating unit that includes an internal power-supply step-down voltage generating circuit, an internal power-supply step-up voltage generating circuit, a current-source-bias generating circuit, and so on. Upon detecting the rising of all internal voltages and internal power-supply voltages, the internal power-supply circuit outputs a start signal indicating that the series of starting internal-power-supply operations has been completed. In response to the start signal, the internal circuit starts operation.

Since the above-described reference voltage is used as a reference voltage for the various internal power-supply voltages and the internal voltages, it is required that the reference voltage has a desired fixed level that is independent of the level of the externally supplied power-supply voltage Vdd. During a burn-in test, however, the potentials of the internal power-supply voltages are controlled so that they are higher than those for the normal operation to cause a defect in the integrated circuit to appear. Thus, it has been proposed that the reference voltage for the burn-in acceleration test is set to have a higher potential than that for the normal operation.

For example, Japanese laid-open patent publication No. 6-208791 discloses a technology in which a DRAM is provided with a first constant-voltage generating circuit for generating a first reference voltage that is independent of an external power-supply voltage and that is used for a normal operation and a second constant-voltage generating circuit for generating a second reference voltage that is dependent on the external power-supply voltage and that is used for a burn-in acceleration test.

Japanese laid-open patent publication No. 2004-55001 discloses a technology in which, during a burn-in test, a reference voltage for a burn-in test instead of a reference voltage used for a normal reading operation is applied to a memory device employing a TMR (tunneling magneto resistance) device. However, the burn-in test reference voltage is applied externally from a tester during the burn-in test.

Japanese laid-open patent publication No. 5-136680 discloses a technology in which a reference voltage during aging is set lower than a reference voltage of a current switch during a normal operation, for a level conversion circuit for a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuit with an ECL (emitter couple logic) interface. This publication is not directly related to the above-described burn-in test reference voltage.

The DRAM disclosed in Japanese laid-open patent publication No. 6-208791 described above is provided with the second constant-voltage generating circuit for generating the second reference voltage that is dependent on the external power-supply voltage and that is used for the burn-in acceleration test. Thus, by performing control to increase the potential of the external power-supply voltage during the burn-in acceleration test, it is possible to make the internal power-supply voltage in the cell array in a memory core to have a higher potential than that for the normal operation. This arrangement makes it possible to cause a defective portion to appear and makes it possible to detect a chip having a potential defect.

According to one aspect of embodiments, an internal power-supply circuit for generating an internal voltage based on a reference voltage, The internal power-supply circuit including: an external-power-supply terminal to which an external power-supply voltage having a first potential is applied during a normal operation and an external power-supply voltage having a second potential that is higher than the first potential is applied during a burn-in acceleration test; a reference-voltage generating unit for generating the reference voltage having a desired potential from the external power-supply voltage; and an internal-voltage generating unit for generating, upon receiving the reference voltage, the internal voltage based on the reference voltage.

During the normal operation, the reference-voltage generating unit generates a normal reference voltage that is independent of a potential of the external power-supply voltage, and during the burn-in acceleration test, the reference-voltage generating unit generates a first burn-in reference voltage that is dependent on the potential of the external power-supply voltage and a second burn-in reference voltage that has the same potential as the normal reference voltage.

FIG. 1 is a block diagram of a DRAM that is one type of semiconductor integrated circuit;

FIG. 2 is a diagram of a memory core in the DRAM;

FIG. 3 is a circuit diagram of a delay circuit;

FIG. 4 is a circuit diagram of a current-source-bias generating circuit;

FIG. 5 is a circuit diagram of a Vpp generating circuit;

FIG. 6 is a circuit diagram of a delay-circuit internal power-supply generating circuit (Vid generating circuit);

FIG. 7 is a diagram of a circuit for generating a control signal;

FIG. 8 is a graph showing relationships of an external power-supply voltage and internal power-supply voltages during a normal operation;

FIG. 9 is a graph showing relationships of the external power-supply voltage and the internal power-supply voltages during a burn-in acceleration test;

FIG. 10 is a block diagram of an internal power-supply circuit that enables the burn-in acceleration test;

FIG. 11 is a circuit diagram of a normal-reference-voltage generating circuit;

FIG. 12 is a circuit diagram of a burn-in reference voltage generating circuit;

FIG. 13 is another circuit diagram of the burn-in reference voltage generating circuit;

FIG. 14 is a block diagram of an internal power-supply circuit in a first embodiment;

FIG. 15 is a circuit diagram showing one example of a second burn-in reference voltage generating circuit;

FIG. 16 is a circuit diagram of a switch;

FIG. 17 is a graph showing relationships of the external power-supply voltage and the internal power-supply voltages during the burn-in acceleration test in the first embodiment;

FIG. 18 is a block diagram of an internal power-supply circuit in a second embodiment;

FIG. 19 is a circuit diagram of a switch; and

FIG. 20 is a graph showing relationships of the external power-supply voltage and the internal power-supply voltages during the burn-in acceleration test in the second embodiment.

Embodiments will be described below with reference to the accompanying drawings. However, the technical scope of the present invention is not limited to the embodiments and encompasses features disclosed in the claims and equivalents thereto.

FIG. 1 is a block diagram of a DRAM that is one type of semiconductor integrated circuit. The DRAM has an internal power-supply circuit 10 that generates internal power from externally supplied power-supply voltage Vdd, a peripheral circuit 16 to which internal voltages bias and Vid generated by the internal power-supply circuit 10 and the externally supplied power-supply voltage Vdd are supplied, and a memory core 17 to which internal power-supply step-down voltages Vii, Vpr, and Vcp and an internal power-supply step-up voltage Vpp are supplied.

The peripheral circuit 16 receives a control signal CON and an address ADD from a memory controller (not shown) and receives or outputs input/output data DQ. The peripheral circuit 16 has a delay circuit 18 , which generates a timing signal for operating a circuit in the memory core 17 .

The memory core 17 includes a word decoder, a column decoder, a memory cell array, a sense amplifier, and so on.

The internal power-supply circuit 10 has a reference-voltage generating unit 11 for generating a reference voltage Vref having a desired potential from the external power-supply voltage Vdd, a current-source-bias generating circuit 12 for generating a current-source-bias voltage bias from the reference voltage Vref, a power-supply step-up voltage generating circuit (a Vpp generating circuit) 13 for generating an internal power-supply step-up voltage Vpp from the external power-supply voltage Vdd and the reference voltage Vref, and a delay-circuit internal power-supply generating circuit (a Vid generating circuit) 14 for generating delay-circuit internal power-supply voltage Vid from the reference voltage Vref.

The current-source-bias generating circuit 12 , the Vpp generating circuit 13 , and the Vid generating circuit 14 constitute an internal-voltage generating unit.

Although not shown, the internal power-supply circuit 10 further has an internal power-supply step-down voltage generating circuit (not shown) for generating internal power-supply step-down voltages Vii, Vpr, and Vcp from the external power-supply voltage Vdd and the reference voltage Vref.

The Vpp generating circuit 13 and the internal power-supply step-down voltage generating circuit have therein detection circuits 15 for detecting the levels of the power-supply voltages Vpp and Vii generated thereby. A A burn-in control signal biz is input to the reference-voltage generating unit 11 . The level of the burn-in control signal biz goes high during a burn-in acceleration test and goes low during a normal operation.

The internal power-supply step-down voltage Vii has a lower potential than the external power-supply voltage Vdd and the internal power-supply step-down voltages Vpr and Vcp have lower potentials than the internal power-supply step-down voltage Vii. The internal power-supply step-up voltage Vpp has a higher potential than the external power-supply voltage Vdd. The internal circuit is operated with the internal power-supply step-down voltage to thereby allow low power consumption and high speed operation.

FIG. 2 is a block diagram of the memory core 17 in the DRAM. The memory core 17 includes word lines WL 0 and WL 1 , a pair of bit lines BL and /BL, a memory cell array having memory cells MC 0 and MC 1 provided at the intersections of the word and bit lines, a word-decoder/word-driver WDEC/WDR, a bit-line precharge circuit PRE, and a sense amplifier SA. The bit lines BL and /BL are connected to the bit-line precharge circuit PRE and the sense amplifier SA via bit-line transfer transistors BTR and /BTR. The gates of the bit-line transfer transistors BTR and /BTR are controlled by a bit-line transfer drive circuit BT. The sense amplifier SA is driven by an n-channel-side drive circuit NSA and a p-channel-side drive circuit PSA.

The power-supply step-up voltage Vpp generated by the internal power-supply circuit 10 is supplied to the word-decoder/word-driver WDEC/WDR to drive the word lines WL 0 and WL 1 up to the level of the power-supply step-up voltage Vpp. The bit-line transfer drive circuit BT is also driven by the power-supply step-up voltage Vpp. The internal power-supply step-down voltage Vii is supplied to the p-channel-side drive circuit PSA, and the sense amplifier SA is driven by the internal power-supply step-down voltage Vii and a ground potential Vss.

In contrast, the internal power-supply step-down voltage Vpr is connected to the bit-line precharge circuit PRE and is used for the precharge level of the bit lines BL and /BL. The internal power-supply step-down voltage Vcp is connected to electrodes opposite to the capacitors of the memory cells MC 0 and MC 1 . That is, the internal power-supply step-down voltage Vpr is bit-line precharge power and the internal power-supply step-down voltage Vcp is cell plate power.

The operation of the memory will now be described first, with the bit lines BL and /BL being precharged to have the level of the second internal power-supply step-down voltage Vpr, one of the word lines WL 0 and WL 1 is driven to have the level of the internal power-supply step-up voltage Vpp and information of the memory cell is read out to the bit lines. In this state, the sense amplifier SA is activated and the potential of one of the bit lines is increased to the internal power-supply step-down voltage Vii and the potential of the other bit line is reduced to the ground potential Vss.

In a burn-in acceleration test, at least the internal power-supply step-up voltage Vpp is set to have a higher potential than that for the normal operation and the word line WL is driven to have a higher potential than that for the normal operation. The driving with the high voltage causes, for example, a defect due to short circuiting between the word line and the bit line to appear. There is also case in which the internal power-supply step-down voltages Vii and Vpr and so on are set to have higher potentials than those for the normal operation to cause a defect to appear. Thus, during the burn-in acceleration test, a testing apparatus controls the potential of the externally supplied power-supply voltage Vdd so that it has a higher potential than that for the normal operation and also controls the reference voltage Vref so that it is higher than that for the normal operation. The detection circuit 15 in the Vpp generating circuit 13 detects the potential of the internal power-supply step-up voltage Vpp based on the reference voltage Vref that is higher than that for the normal operation. Thus, the Vpp generating circuit 13 generates the internal power-supply step-up voltage Vpp that is higher than that for the normal operation.

The circuit configuration of the internal power-supply circuit 10 and the delay circuit 18 shown in FIG. 1 will now be described in detail. A problem of the burn-in acceleration test will be described below.

FIG. 3 is a circuit diagram of the delay circuit 18 . The delay circuit 18 delays an input signal IN by a predetermined time to output an output signal OUT. For example, the delay circuit 18 receives a first control signal as the input signal IN, and outputs a second control signal as the output signal OUT after a predetermined time. Provision of multiple delay circuits 18 allows multiple control signals to be sequentially generated at predetermined timing. The control signals are used to control the operation timing of the circuit in the memory core 17 .

The delay circuit 18 has a CMOS inverter, a current-source transistor N 3 , a delay capacitor Cp, and an inverter INV 1 between the delay-circuit internal power supply Vid and ground Vss. The CMOS inverter includes a p-channel transistor P 1 and an n-channel transistor N 2 . The current-source transistor N 3 generates electrical current in accordance with the bias voltage bias. Hereinafter, P is affixed to the reference numeral of a p-channel transistor and N is affixed to the reference numeral of an n-channel transistor.

Upon application of the bias voltage bias, the current-source transistor N 3 is brought into conduction to allow generation of a desired current and the CMOS inverter, which includes the transistors P 1 and N 2 , are put into an active state. When the input signal IN is at a low level, the transistor P 1 is brought into conduction, so that the delay capacitor Cp is charged to have the potential of the delay-circuit internal power-power voltage Vid. In this state, the output signal OUT is at a low level. When the level of the input signal IN changes to high, the transistor N 1 is brought into conduction, so that the value of current flowing thorough the current-source transistor N 3 causes the delay capacitor Cp to discharge electricity and the level of the output signal OUT changes to high. Thus, the delay time depends on the potential of the delay-circuit internal power-supply voltage Vid and the potential of the current-source-bias voltage bias.

FIG. 4 is a circuit diagram of the current-source-bias generating circuit 12 . The current-source-bias generating circuit 12 has a resistor R 1 and a diode-connected transistor N 4 . A constant voltage, i.e., the reference voltage Vref, is applied as an input voltage Vin. Since the transistor N 4 is connected to a diode, current I 4 that flows through the resistor R 1 is given by:

I 4=( V in− V th)/ R 1

where Vth indicates a threshold voltage of the transistor N 4 .

The bias voltage bias is applied to the gate of a current-source transistor N 5 . That is, the same bias voltage is applied to the gates of the transistor N 4 and N 5 . Thus, when both transistors N 4 and N 5 are operating in their saturation regions, the ratio of currents I 4 to I 5 that flow through the transistors N 4 and N 5 is given by:

I 4: I 5=( W 4/ L 4):( W 5/ L 5)

where the transistor N 4 has a gate width W 4 and a gate length L 4 and the transistor N 5 has a gate width W 5 and a gate length L 5 .

That is, the current-source transistor N 5 can generate the current I 5 that is proportional to the sizes of both transistors N 4 and N 5 .

As described above, the current I 4 has the amount of current which depends on the input voltage Vin (the reference Vref). The amount of current of the current-source transistor N 5 to which the bias voltage bias is supplied also depends on the input voltage Vin (the reference voltage Vref). Thus, it can be understood that the amount of delay caused by the delay circuit 18 shown in FIG. 3 depends on the reference voltage Vref supplied to the current-source-bias generating circuit 12 .

FIG. 5 is a circuit diagram of the Vpp generating circuit 13 . The Vpp generating circuit 13 has the detection circuit 15 that detects whether or not the potential of the internal power-supply step-up voltage Vpp to be generated has a predetermined rate relative to the reference voltage Vref, an oscillation circuit 20 that performs oscillation operation in accordance with a detection output detz of the detection circuit 15 , and a pumping circuit 21 that performs pumping operation in response to an oscillation pulse oscz generated by the oscillation circuit 20 . In response to the oscillation pulse oscz, the pumping circuit 21 pumps charge from the external power-supply voltage Vdd to increase the potential of the internal power-supply step-up voltage Vpp.

The internal power-supply step-up voltage Vpp output from the pumping circuit 21 is fed back to the detection circuit 15 . The detection circuit 15 has a differential amplifier circuit that includes transistors P 10 , P 11 , N 13 , and N 14 , and a current-source transistor N 17 . The transistors P 10 and P 11 constitute a current mirror circuit. The transistors N 13 and N 14 compares a monitor voltage Vmoni 1 , obtained by dividing the fed-back internal power-supply step-up voltage Vpp by the resistance ratio of the resistors R 11 and R 12 , with the reference voltage Vref. The bias voltage bias is applied to the gate of the current-source transistor N 17 . When a drain-source voltage Vds exceeds a saturation voltage, the current source transistor N 17 causes a certain amount of current to flow so that the differential amplifier circuit operates with appropriate characteristics. The detection signal detz of the detection circuit 15 is supplied to the oscillation circuit 20 via an inverter INV 6 .

When an active signal actz is at a low level, the transistor P 12 is brought into conduction, transistors N 16 and N 18 are brought into non-conduction, the detection signal detz is fixed to a high level, and the oscillation operation of the oscillation circuit 20 stops. On the other hand, when the active signal actz is at a high level, the transistors N 16 and N 18 are brought into conduction, the transistor P 12 is brought into non-conduction, and the Vpp generating circuit 13 is put into an active state.

In the active state, the differential amplifier circuit to which the internal power-supply step-up voltage Vpp is fed back compares the monitor voltage Vmoni 1 with the reference voltage Vref and generates the detection signal detz so that the monitor voltage Vmoni 1 is equal to the reference voltage Vref. Thus, when the potential of the internal power-supply step-up voltage Vpp decreases and the monitor voltage Vmoni 1 falls below the reference voltage Vref, the level of the detection signal goes low, the oscillation circuit 20 starts oscillation operation, and the pumping operation of the pumping circuit 21 increases the potential of the power-supply step-up voltage Vpp. Conversely, when the potential of the internal power-supply step-up voltage Vpp increases and the monitor voltage Vmoni 1 exceeds the reference voltage Vref, the level of the detection signal detz goes high, the oscillation circuit 20 stops the oscillation operation, and the pumping circuit 21 also stops the pumping operation. As a result, the output Vpp is given by Vpp=Vref*(R 43 +R 44 )/R 44 . Thus, the potential of the internal power-supply step-up voltage Vpp is determined by the reference voltage Vref and the resistance ratio of the resistors R 43 and R 44 .

As described above, the Vpp generating circuit 13 controls the potential of the internal power-supply step-up voltage Vpp in accordance with the potential of the reference voltage Vref. Thus, during the burn-in acceleration test, increasing the potential of the reference voltage Vref makes it possible to perform control so that the potential of the internal power-supply step-up voltage Vpp is high.

FIG. 6 is a circuit diagram of the delay-circuit internal power-supply generating circuit (the Vid generating circuit) 14 . The Vid generating circuit 14 has a differential amplifier circuit that includes transistors P 20 and P 21 , an output transistor P 22 , transistors N 23 and N 24 , a current-source transistor N 25 , and resistors R 21 and R 22 . The transistors P 20 and P 21 constitute a current mirror circuit. The pair of transistors N 23 and N 24 compares the reference voltage Vref with a monitor voltage Vmoni 2 . A control signal Vcon 1 is supplied to the gate of the current-source transistor N 25 . The Vid generating circuit 14 further has an output capacitor C 1 . The control signal Vcon 1 has a fixed potential that is independent of the external power-supply voltage Vdd, for example, has a unique potential generated by a band-gap reference circuit (not shown). This causes the transistor N 25 to generate a minute amount of current.

The differential amplifier circuit to which the internal power-supply voltage Vid is fed back compares the monitor voltage Vmoni 2 , obtained by dividing the delay-circuit internal power-supply voltage Vid by the resistance ratio of the resistors R 21 and R 22 , with the reference voltage Vref, and generates the internal power-supply voltage Vid so that the monitor voltage Vmoni 2 is equal to the reference voltage Vref. Thus, when the monitor voltage Vmoni 2 is higher than the reference voltage Vref, the voltage at the drain node of the transistor N 23 increases to bring the transistor P 22 into non-conduction. When the monitor voltage Vmoni 2 is lower than the reference voltage Vref, the transistor P 22 is brought into conduction to increase the internal power-supply voltage Vid. Thus, the power-supply voltage Vid is given by Vid=Vref*(R 21 +R 22 )/R 22 .

As described above, the Vid generating circuit 14 controls the potential of the delay-circuit internal power-supply voltage Vid in accordance with the potential of the reference voltage Vref.

FIG. 7 is a diagram of a circuit for generating the control signal Vcon 1 . This control-signal generating circuit has transistors P 24 , P 25 , N 26 , and N 27 , a resistor P 2 , and a stabilizing capacitor C 3 . The control signal Vcon 1 is independent of the potential of the external power-supply voltage Vdd and has a fixed value. As a result, the current-source transistor N 25 shown in FIG. 6 generates a minute amount of current.

FIG. 8 is a graph showing relationships of the external power-supply voltage and the internal power-supply voltages during the normal operation. The horizontal axis indicates the potential of the external power-supply voltage Vdd and the vertical axis indicates the potentials of the internal power-supply voltages and internal voltages. When the external power-supply voltage Vdd increases in the horizontal axis, the external power-supply voltage Vdd also increases in the vertical direction. In an operation range OPrange, the reference voltage Vref has a constant potential. Thus, the internal voltages, such as the internal power-supply step-up voltage Vpp, the bias voltage bias, and the delay-circuit internal power-supply voltage Vid, which are generated based on the reference voltage Vref, also controlled to have constant values. Adjusting the resistance ratio of the feedback circuit allows generation of a reference voltage Vref having multiple potential levels, and in practice, allows a DRAM to generate a reference voltage Vref having multiple potential levels.

FIG. 9 is a graph showing relationships of the external power-supply voltage and the internal power-supply voltages during the burn-in acceleration test. In the burn-in acceleration test, it is necessary to apply a voltage higher than a normally applied voltage to a semiconductor integrated circuit in order to accelerate a potential factor of a defect in the semiconductor integrated circuit to cause a defect to appear. Thus, in the burn-in acceleration test, as shown in FIG. 9 , the external power-supply voltage Vdd is controlled so that it reaches a burn-in external power-supply voltage Vddbi that is higher than the range OPrange during the normal operation and the reference voltage Vref is also controlled so that it becomes high based on the external power-supply voltage Vddbi. Thus, controlling the external power-supply voltage Vdd so that it has an appropriate high potential allows the potential of the internal power-supply step-up voltage Vpp generated based on the high reference voltage Vref to have an appropriate high potential. As a result, for example, the internal power-supply step-up voltage Vpp serves as a power-supply voltage for setting word lines in the DRAM. Thus, performing control so that the internal power-supply step-up voltage Vpp is high makes it possible to appropriately perform the burn-in acceleration test.

FIG. 10 is a block diagram of an internal power-supply circuit that enables the burn-in acceleration test. In this internal power-supply circuit, the reference-voltage generating unit 11 has a normal-reference-voltage generating circuit 11 A and a burn-in reference voltage generating circuit 11 B. The normal-reference-voltage generating circuit 11 A generates a normal reference voltage Vrefnr that is independent of the external power-supply voltage Vdd and the burn-in reference voltage generating circuit 11 B generates a burn-in reference voltage Vrefbi that is dependent on the external power-supply voltage Vdd. The reference-voltage generating circuits 11 A and 11 B are activated by the burn-in control signal biz (which has a low level during the normal operation and a high level during the burn-in acceleration test)

During the normal operation, the normal-reference-voltage generating circuit 11 A is activated to generate the normal reference voltage Vrefnr and the burn-in reference voltage generating circuit 11 B is deactivated. On the other hand, during the burn-in acceleration test, the normal-reference-voltage generating circuit 11 A is deactivated and the burn-in reference voltage generating circuit 11 B is activated to generate the burn-in reference voltage Vrefnr having a potential that is dependent on the external power-supply voltage Vdd.

As described above, the reference voltage is supplied to the internal-voltage generating unit that includes the Vpp generating circuit 13 , the Vid generating circuit 14 , and the current-source-bias generating circuit 12 . The bias voltage bias is supplied to the detection circuit 15 in the Vpp generating circuit 13 and the delay circuit 18 , and the delay-circuit internal power-supply voltage Vid is supplied to the delay circuit 18 . During the normal operation, the reference voltage becomes the normal reference voltage Vrefnr that is independent of the external power-supply voltage Vdd, and based on the normal reference voltage Vrefnr, the internal power-supply step-up voltage Vpp, the delay-circuit internal power-supply voltage Vid, and the bias voltage bias are generated. On the other hand, during the burn-in acceleration test, the reference voltage becomes the burn-in reference voltage Vrefbi that is dependent on the external power-supply voltage Vdd, and based on the burn-in reference voltage Vrefbi, the internal power-supply step-up voltage Vpp is generated. During the burn-in acceleration test, the external power-supply voltage Vdd is controlled so that it is higher than that for the normal operation; therefore, the burn-in reference voltage Vrefbi and the internal power-supply step-up voltage Vpp also have higher potentials. With this arrangement, it is possible to apply stress caused by the higher voltage than that for the normal operation to the memory core to perform acceleration test.

FIG. 11 is a circuit diagram of the normal-reference-voltage generating circuit 11 A. The reference-voltage generating unit 11 has a differential amplifier circuit and a feedback circuit. The differential amplifier circuit has transistors P 30 and P 31 that constitute a current mirror circuit, a pair of transistors N 33 and N 34 that compares a fixed voltage Vcon 2 with a monitor voltage Vmoni 3 , a current-source transistor N 36 having a gate to which the control signal Vcon 1 is supplied, and an output transistor P 37 . The feedback circuit includes resistors R 31 and R 32 . The normal-reference-voltage generating circuit 11 A further has transistors P 32 , N 35 , and N 38 that are controlled by the burn-in control signal biz.

During the normal operation, the level of the burn-in control signal biz goes low and the normal-reference-voltage generating circuit 11 A is activated. The differential amplifier circuit having the feedback circuit drives and controls the output transistor P 37 so that the monitor voltage Vmoni 3 obtained by dividing the output normal reference voltage Vrefnr by the resistance ratio R 31 :R 32 is equal to the fixed voltage Vcon 2 . As a result, the output normal reference voltage Vrefnr is controlled so as to satisfy Vrefnr=Vcon 2 *(R 31 +R 32 )/R 32 . That is, adjusting the resistance ratio of the resistors R 31 and R 32 allows the normal reference voltage Vrefnr to have a desired potential and to be independent of the external power-supply voltage Vdd. Since the output impedance of the output transistor P 37 is low, the input impedance of a power-supplied circuit to which the output Vout is supplied may be high or low.

On the other hand, during the burn-in acceleration test, the level of the burn-control signal biz goes high, the output of the inverter INV 2 goes low, the transistor P 32 is brought into conduction, the transistors P 37 and P 38 are brought into non-conduction, and the output Vout is put into a high impedance state.

FIG. 12 is a circuit diagram of the burn-in reference voltage generating circuit 11 B. Similarly to the normal-reference-voltage generating circuit 11 A shown in FIG. 11 , the burn-in reference voltage generating circuit 11 B has a differential amplifier circuit that includes transistors P 40 , P 41 , N 43 , N 44 , N 46 , and P 47 and a feedback circuit that includes resistors R 41 and R 42 . However, a reference voltage Vrefv has a potential obtained by dividing the external power-supply voltage Vdd by the resistance ratio of the transistors R 43 and R 44 . Thus, when the level of the burn-in control signal biz goes high during the burn-in acceleration test, the transistors N 48 and N 49 are brought into conduction, the transistor P 42 is brought into non-conduction, and the reference voltage Vrefv has a potential that is dependent on the external power-supply voltage Vdd. By setting the external power-supply voltage Vdd to have a burn-in level Vddbi that is higher than that for the normal operation, it is possible to increase the reference voltage Vrefv. Thus, it is possible to perform control so that the burn-in reference voltage Vrefbi has a higher potential that the normal reference voltage Vrefnr.

Since the reference voltage Vrefv is given by Vrefv=Vdd*R 44 /(V 43 +V 44 ), the burn-in reference voltage Vrefbi is given by Vrefbi=Vdd*R 44 *(R 41 +R 42 )/(R 43 *R 44 )/R 42 . That is, the burn-in reference voltage Vrefbi has a potential that is dependent on the external power-supply voltage Vdd.

On the other hand, the level of the burn-in control signal biz goes high during the normal operation, the transistors P 47 and N 48 are brought into non-conduction and the output Vout is put into a high impedance state. The burn-in reference voltage generating circuit in FIG. 12 has low output impedance, similarly to the circuit shown in FIG. 11 , and the input impedance of a circuit to which the burn-in reference Vrefbi is supplied may be high or low.

FIG. 13 is another circuit diagram of the burn-in reference voltage generating circuit 11 B. In this circuit example, a transistor P 50 , resistors R 51 and R 52 , and a transistor N 51 are provided between the external power supply Vdd and ground Vss, and the burn-in control signal biz is supplied to the gate of the transistor N 51 and is supplied to the gate of the transistor P 50 via an inverter INV 3 . During the burn-in acceleration test, the transistors P 50 and N 51 are brought into conduction and the burn-in reference voltage Vrefbi has a potential that is a multiple of the resistance ratio of the (Vdd-Vss) resistors R 51 and R 25 . That is, Vrefbi=Vdd*R 52 /(R 51 +R 52 ) is given and the burn-in reference voltage Vrefbi has a potential that is dependent on the external power-supply voltage Vdd. On other hand, since the level of the burn-in control signal biz goes high during the normal operation, the transistors P 50 and N 51 are brought into non-conduction and the output Vout is put into a high impedance state.

In the burn-in reference voltage generating circuit shown in FIG. 13 , the resistors R 51 and R 52 increase the output impedance of the output terminal Vout. Thus, it is required that the input impedance of a circuit to which the burn-in reference voltage Vrefbi is supplied be high. However, the burn-in reference voltage generating circuit can operate even when then number of devices is reduced, the resistances of the resistors R 51 and R 52 are increased, and the circuit area is reduced. Thus, the area occupied by the generating circuit can be reduced.

Referring back to FIGS. 9 and 10 , during the burn-in acceleration test, the burn-in reference voltage generating circuit 11 B is operated to generate the burn-in reference voltage Vrefbi that is dependent on the external power-supply voltage Vdd. This arrangement can increase the internal power-supply step-up voltage Vpp to be higher than that for the normal operation and can apply an appropriate stress to devices.

However, since the burn-in reference voltage Vrefbi is higher than that for the normal operation, the bias voltage bias and the delay circuit internal power-supply voltage Vid which are generated based on the burn-in reference voltage Vrefbi also become high. As shown in FIG. 9 , the bias voltage bias and the internal power-supply voltage Vid are also high with respect to the external power-supply voltage Vddbi during the burn-in test. An increase in the bias voltage bias also increases the amount of current in the differential amplifier circuit including the delay circuit 18 ( FIG. 3 ) and the detection circuit 15 ( FIG. 15 ). The power-supply voltage Vid of the delay circuit 18 also increases. Thus, the delay time of the delay circuit 18 differs from that for the normal operation and the timing of a timing control signal generated by the delay circuit 18 differs from the timing of a timing controlling signal generated during the normal operation. In addition, the differential amplification operation in an appropriate operation range is not ensured because of an increase in the amount of current in the differential amplifier circuit in the detection circuit, and thus, malfunction can occur.

Accordingly, in the present embodiment, the reference-voltage generating unit generates a normal reference voltage Vrefnr that is independent of the potential of the external power-supply voltage Vdd during the normal operation and generates a first burn-in reference voltage that is dependent on the external power-supply voltage Vdd and a second burn-in reference voltage that has the same potential as the normal reference voltage Vrefnr. During the burn-in acceleration test, the first burn-in reference voltage is supplied to the Vpp generating circuit and the second burn-in reference voltage is supplied to the Vid generating circuit and the current-source-bias generating circuit.

Alternatively, in the first embodiment, the reference-voltage generating unit generates a normal reference voltage that is independent of the potential of the external power-supply voltage during the normal operation and generates a first burn-in reference voltage that is dependent on the potential of the external power-supply voltage and a second burn-in reference voltage that is dependent on the potential of the external power-supply voltage and that is lower than the first burn-in reference voltage. In this case, the first burn-in reference voltage is also supplied to the Vpp generating circuit and the second burn-in reference voltage is supplied to the Vid generating circuit and the current-source-bias generating circuit, as in the case described above.

In addition, in a second embodiment, the reference-voltage generating unit generates a normal reference voltage Vrefnr that is independent of the potential of the external power-supply voltage during the normal operation and generates a first burn-in reference voltage and a normal reference voltage that are dependent on the external power-supply voltage during the burn-in acceleration test. During the burn-in acceleration test, the first burn-in reference voltage is supplied to the Vpp generating circuit and the normal reference voltage is supplied to the Vid generating circuit and the current-source-bias generating circuit. A more specific description will be given below.

FIG. 14 is a block diagram of an internal power-supply circuit according to the first embodiment. In the first embodiment, the reference-voltage generating unit 11 has a normal-reference-voltage generating circuit 11 A, a first burn-in reference voltage generating circuit 11 B, and a second burn-in reference voltage generating circuit 11 C. The normal-reference-voltage generating circuit 11 A is activated during the normal operation to generate a normal reference voltage Vrefnr. The first burn-in reference voltage generating circuit 11 B is activated during the burn-in acceleration test to generate a first burn-in reference voltage Vrefbi 1 that is dependent on the external power-supply voltage Vdd. The second burn-in reference voltage generating circuit 11 C is also activated during the burn-in acceleration test to generate a second burn-in reference voltage Vrefbi 2 . The second burn-in reference voltage Vrefbi 2 has the same potential as the normal reference voltage Vrefnr, generated during the normal operation, with respect to the burn-in external power-supply voltage Vddbi applied during the burn-in acceleration test. The second burn-in reference voltage Vrefbi 2 has a lower potential than the first burn-in reference voltage Vrefbi 1 .

The reference-voltage generating unit 11 further has a switch SW 1 that is operated in response to the burn-in control signal biz. During the normal operation, the switch SW 1 selects the normal reference voltage Vrefnr to supply it to the Vid generating circuit 14 and the current-source-bias generating circuit 12 . On the other hand, during the burn-in acceleration test, the switch SW 1 selects the second burn-in reference voltage Vrefbi 2 to supply it to the Vid generating circuit 14 and the current-source-bias generating circuit 12 . During the normal operation, the normal reference voltage Vrefnr that is independent of the external power-supply voltage Vdd is supplied to the detection circuit 15 in the Vpp generating circuit 13 . During the burn-in acceleration test, the first burn-in reference voltage Vrefbi 1 that is dependent on the external power-supply voltage Vdd is supplied to the detection circuit 15 .

Thus, during the burn-in acceleration test, the Vpp generating circuit 13 generates an internal power-supply step-up voltage Vpp that is higher than that for the normal operation in response to the external power-supply voltage Vdd, the Vid generating circuit 14 generates a delay-circuit internal power-supply voltage Vid that has the same potential as that for the normal operation, and the current-source-bias generating circuit 12 generates a bias voltage bias that has the same potential as that for the normal operation. Thus, during the burn-in acceleration test, it is possible to accelerate a defective portion in the memory core and to allow the detection circuit 15 and the delay circuit 18 to operate with the same characteristics as those for the normal operation.

The normal-reference-voltage generating circuit 11 A has the same circuit configuration as the generating circuit shown in FIG. 11 . Thus, the normal-reference-voltage generating circuit 11 A is activated during the normal operation (i.e., at the low level of the burn-in control signal biz) to generate a normal reference voltage Vrefnr having a potential that is independent of the external power-supply voltage Vdd. During the burn-in acceleration test, the output Vout is put into a high impedance state.

The first burn-in reference voltage generating circuit 11 B is one of the circuits shown in FIGS. 12 and 13 . The first burn-in reference voltage generating circuit 11 B is activated during the burn-in acceleration test (i.e., at the high level of the burn-in control signal biz) to generate a first burn-in reference voltage Vrefbi 1 having a potential that is dependent on the potential of the external power-supply voltage Vdd. During the normal operation, the output Vout is put into a high impedance state.

The second burn-in reference voltage generating circuit 11 C is one of the circuits shown in FIGS. 12 and 13 , but the resistance ratio of the resistors is different from that of the first burn-in reference voltage generating circuit 11 B. With respect to the burn-in external power-supply voltage Vdd supplied during the burn-in acceleration test, the second burn-in reference voltage Vrefbi 2 is lower than the first burn-in reference voltage Vrefbi 1 and has a potential that is the same as or similar to the normal reference voltage Vrefnr for the normal operation.

FIG. 15 is a circuit diagram showing one example of the second burn-in reference voltage generating circuit 11 C. This circuit diagram is analogous to the circuit diagram shown in FIG. 12 , but the reference numerals of the devices are different and the resistance ratio of the resistors R 63 and R 64 or the resistance ratio of the resistors R 61 and R 62 is different from that in FIG. 12 . For example, the resistance ratio is given by R 64 /(R 63 +R 64 )<R 43 (R 43 +R 44 ), and the reference voltage is given by Vrefv ( FIG. 15 ) <Vrefv ( FIG. 12 ). Consequently, Vrefbi 1 >Vrefbi 2 =Vrefnr is given.

The second burn-in reference voltage generating circuit 11 C may be the same circuit shown in FIG. 13 . In such a case, the resistance ratio of the resistors R 51 and R 52 is different and Vrefbi 1 >Vrefbi 2 =Vrefnr is given.

FIG. 16 is a circuit diagram of the switch SW 1 . The switch SW 1 has CMOS transfer gates TG 1 and TG 2 and an inverter INV 4 . During the normal operation (i.e., at the low level of the burn-in control signal biz), the gate TG 1 is brought into conduction to connect a first input Vin 1 to an output Vout. During the normal operation, the normal reference voltage Vrefnr is input to the first input Vin. On the other hand, during the burn-in acceleration test (i.e., at the high level of the burn-in control signal biz), the gate TG 2 is brought into conduction to connect a second input Vin 2 to the output Vout. During the burn-in acceleration test, the second burn-in reference voltage Vrefbi 2 is input to the second input Vin 2 .

As described above, during the normal operation, the switch SW 1 selects the normal reference voltage Vrefnr to supply it to the Vid generating circuit 14 and the current-source-bias generating circuit 12 . On the other hand, during the burn-in acceleration test, the switch SW 1 selects the second burn-in reference voltage Vrefbi 2 to supply it to the Vid generating circuit 14 and the current-source-bias generating circuit 12 .

FIG. 17 is a graph showing relationships of the external power-supply voltage and the internal power-supply voltages during the burn-in acceleration test in the first embodiment. As described above, the first and second burn-in reference voltages Vrefbi 1 and Vrefbi 2 have potentials that are dependent on the external power-supply voltage Vdd, as described above, but the gradients of the potentials thereof are different from each other. Thus, Vrefbi 1 >Vrefbi 2 is given with respect to the burn-in external power-supply voltage Vddbi.

During the burn-in acceleration test, the external power-supply voltage Vdd is controlled so that it is higher than that for the normal operation. Thus, the first burn-in reference voltage Vrefbi 1 , which is dependent on the external power-supply voltage Vddbi, is also higher than the normal reference voltage Vrefnr applied during the normal operation. Since the first burn-in reference voltage Vrefbi 1 is input to the detection circuit 15 in the Vpp generating circuit 13 , the internal power-supply step-up voltage Vpp generated based on the reference voltage Vrefbi 1 is higher than that supplied during the normal operation.

On the other hand, the second burn-in reference voltage Vrefbi 2 is dependent on the external power-supply voltage Vddbi, and is set so that second-burn-in reference voltage Vrefbi 2 is lower than the first burn-in reference voltage Vrefbi 1 , preferably, has the same potential as the normal reference voltage Vrefnr. Thus, the internal power-supply voltage Vid and the bias voltage bias, which are generated based on the second burn-in reference voltage Vrefbi 2 , have potentials that are the same as or similar to those for the normal operation. Thus, the current values of the current sources in the detection circuit 15 and the delay circuit 18 are the same as or similar to those for the normal operation and the delay-circuit internal power-supply voltage Vid is also the same as or similar to that for the normal operation. With this arrangement, the detection circuit 15 has an operation characteristic that is the same as or similar to the operation characteristic for the normal operation and the delay circuit 18 also has a delay characteristic that is the same as or similar to the delay characteristic for the normal operation. Since the delay value of the delay circuit 18 is the same as or similar to that for the normal operation, it is possible to reproduce an internal operation that is the same as or similar to that for the normal operation, and the operation of the differential amplifier circuit in the detection circuit 15 becomes almost the same as the operation for the normal operation.

FIG. 18 is a block diagram of the internal power-supply circuit in the second embodiment. In the second embodiment, the reference-voltage generating unit 11 has a normal-reference-voltage generating circuit 11 A that is activated during both the normal operation and the burn-in acceleration test to generate a normal reference voltage Vrefnr and a burn-in reference voltage generating circuit 11 B that is activated during the burn-in acceleration test to generate a burn-in reference voltage Vrefbi that is dependent on the external power-supply voltage Vdd.

The reference-voltage generating unit 11 further has a switch SW 2 that is operated in response to the burn-in control signal biz. During the normal operation, the switch SW 2 selects the normal reference voltage Vrefnr to supply it to the detection circuit 15 in the Vpp generating circuit 13 . On the other hand, during the burn-in acceleration test, the switch SW 2 selects the burn-in reference voltage Vrefbi to supply it to the detection circuit 15 in the Vpp generating circuit 13 .

During either of the normal operation and the burn-in acceleration test, the normal reference voltage Vrefnr that is independent of the external power-supply voltage Vdd is supplied to the Vid generating circuit 14 and the current-source-bias generating circuit 12 .

During the burn-in acceleration test, the Vpp generating circuit 13 generates an internal power-supply step-up voltage Vpp that is dependent on the external power-supply voltage Vdd and is higher than that supplied during the normal operation, and the Vid generating circuit 14 generates a delay-circuit internal power-supply voltage Vid that has the same potential as that for the normal operation and the current-source-bias generating circuit 12 also generates a bias voltage bias that has the same potential as that for the normal operation. Thus, during the burn-in acceleration test, it is possible to accelerate a defective portion in the memory core and to allow the detection circuit 15 and the delay circuit 18 to operate with the same characteristics as those for the normal operation.

The normal-reference-voltage generating circuit 11 A has the same circuit configuration as the circuit shown in FIG. 11 . The burn-in control signal biz is fixed to the low level, and thus, the normal reference voltage generating circuit 11 A is always active. The burn-in reference voltage generating circuit 11 B is one of the circuits shown in FIGS. 12 and 13 and is activated when the burn-in control signal biz is at the high level.

FIG. 19 is a circuit diagram of the switch SW 2 . The switch SW 2 has CMOS transfer gates TG 11 and TG 12 and an inverter INV 5 . During the normal operation (i.e., at the low level of the burn-in control signal biz), the gate TG 11 is brought into conduction to connect a first input Vin 1 to an output Vout. During the normal operation, the normal reference voltage Vrefnr is input to the first input Vin 1 . On the other hand, during the burn-in acceleration test (i.e., at the high level of the burn-in control signal biz), the gate TG 12 is brought into conduction to connect a second input Vin 2 to the output Vout. During the burn-in acceleration test, the burn-in reference voltage Vrefbi is input to the second input Vin 2 .

As described above, during the normal operation, the switch SW 2 selects the normal reference voltage Vrefnr to supply it to the detection circuit 15 in the Vpp generating circuit 13 . On the other hand, during the burn-in acceleration test, the switch SW 2 selects the burn-in reference voltage Vrefbi 2 to supply it to the detection circuit 15 in the Vpp generating circuit 13 .

FIG. 20 is a graph showing the external power source and the external power sources during the burn-in acceleration test. During the burn-in acceleration test, the external power-supply voltage Vdd is controlled to be Vddbi that is hither than that for the normal operation, and the burn-in reference voltage Vrefbi that depends on Vddbi becomes higher than the normal reference voltage Vrefnr. On the other hand, the normal reference voltage Vrefnr has a fixed potential that does not depend on the external power-supply voltage Vdd, and the delay-circuit internal power-supply voltage Vid and the bias voltage bias generated based on the normal reference voltage Vrefnr have fixed potentials. The voltages have the same potentials as those for the normal operation. That is, the normal reference voltage Vrefnr has a potential that is the same as or similar to the second burn-in reference voltage Vrefbi 2 generated with respect to the burn-in external power-supply voltage Vddbi in the first embodiment.

The resistance values in the normal-reference-voltage generating circuit may be trimmed based on the result of an operation test. In this case, at the stage of the operation test in a burn-in acceleration test before trimming, the normal reference voltage Vrefnr is not completely the same as that for the normal operation. In view of this point, it is more advantageous to provide a second burn-in reference voltage generating circuit, as in the first embodiment, to generate a reference voltage (a design value) during the normal operation based on the burn-in external power-supply voltage Vddbi. In the burn-in acceleration test after trimming, the first and second embodiments provide similar advantages.