Signal processing method and device, and analog/digital converting device

This application is a continuing application, filed under 35 U.S.C. §111(a), of International Application PCT/JP2006/302861, filed Feb. 17, 2006.

1. Field

The embodiment relates to signal processing methods and devices and analog/digital converting devices. More particularly, the embodiment relates to signal processing method and device for processing a time-domain signal, and an analog/digital converting device for converting a time-domain signal to a digital value.

2. Description of the Related Art

Techniques such as Pulse Width Modulation (PWM) have conventionally been known whereby analog signal information is represented along the time axis of a time-domain signal such as a pulse.

Where the time axis of a time-domain signal is used to represent analog signal information, the analog signal can be processed at low voltage, compared with the case where the voltage axis is used to represent analog signal information. This kind of technique has been attracting attention as a result of the recent development of higher-speed hardware enabling improved time resolution.

As such techniques of representing analog signal information along the time axis, a method has been known wherein, for example, the pulse width or pulse interval of a time-domain signal such as a pulse signal is used to represent analog signal information.

FIG. 6 illustrates an exemplary case where the pulse width carries analog signal information.

In the illustrated example, numerical values from “0” to “8” are expressed within a unit time (full-scale time) TF that carries one item of analog signal information. In this case, if the pulse width of an input pulse signal contains, for example, five time resolutions ΔT of a signal processing circuit as shown in the figure, then the input pulse signal represents “5”.

An AD (Analog/Digital) converting device has been known as one of such signal processing circuits that utilize the pulse width of a time-domain signal as indicative of analog signal information.

FIG. 7 is a circuit diagram exemplifying a conventional AD converting device.

The AD converting device 50 includes flip-flop circuits (hereinafter abbreviated as FFs) 51 to 55 , buffers 60 to 63 , an inverter 70 , and an encoder 71 .

The FFs 51 to 55 each comprise a D flip-flop, for example, and the buffers 60 to 63 are each constituted by a two-stage inverter.

The FF 51 is input at all times with “1” at its terminal D and is also input with a time-domain signal at its terminal C. When the time-domain signal changes from “0” to “1”, “1” is captured from the terminal D, held by the FF 51 , and also output from the output terminal Q. A reset signal is input to the terminal R, and when the reset signal turns to “1”, the output at the terminal Q of the FF 51 is reset to “0”.

The output signal from the output terminal Q of the FF 51 is input to the buffer 60 . The state of a node n 10 on the input side of the buffer 60 is transmitted to a node n 11 after a delay corresponding to the delay time of the buffer 60 , transmitted to a node n 12 after a delay corresponding to the delay times of the buffers 60 and 61 , transmitted to a node n 13 after a delay corresponding to the delay times of the buffers 60 to 62 , and transmitted to a node n 14 after a delay corresponding to the delay times of the buffers 60 to 63 . The delay time provided by each of the buffers 60 to 63 determines the time resolution of the AD converting device 50 .

The terminals C of the FFs 52 to 55 are input with the inverted time-domain signal through the inverter 70 . Also, the terminals D of the FFs 52 to 55 are connected to the nodes n 11 to n 14 , respectively.

Thus, at the time the time-domain signal falls, the states of the nodes n 11 to n 14 are captured and held by the respective FFs 52 to 55 .

The reset signal is also input to the terminals R of the FFs 52 to 55 . When the reset signal turns to “1”, the FFs 52 to 55 are all reset to “0”.

Output signals P 10 to P 13 from the output terminals Q of the respective FFs 52 to 55 are input to the encoder 71 . In synchronism with the rise of a clock signal, for example, the encoder 71 captures the output signals P 10 to P 13 of the FFs 52 to 55 .

In FIG. 7 , the four buffers 60 to 63 and the FFs 52 to 55 for storing the states of the respective nodes n 11 to n 14 are illustrated for simplicity of illustration; in practice, the number of the buffers and of the FFs may be increased as desired.

Operation of the AD converting device 50 will be now described.

FIG. 8 is a timing chart exemplifying the operation of the conventional AD converting device.

The figure shows the states of individual signals in the above AD converting device 50 , wherein N 10 to N 14 indicate signals appearing at the respective nodes n 10 to n 14 shown in FIG. 7 . Also, TF indicates the full-scale time, and the pulse width of the time-domain signal within this full-scale time represents analog signal information. TD indicates the time necessary for the signal processing by the encoder 71 and the resetting of the FFs 51 to 55 .

When the reset signal is at “1”, the FFs 51 to 55 are all reset, so that the signals N 10 to N 14 and the output signals P 10 to P 13 all remain at “0”. The reset signal turns to “0” thereafter, and when the time-domain signal turns to “1”, the signal N 10 at the node n 10 changes to “1” synchronously with the rise of the time-domain signal (timing T 20 ).

The change of the signal state is propagated to the nodes n 11 to n 14 while being successively delayed for the delay time of the buffers 60 to 63 , and as a consequence, the signals N 11 to N 14 change to “1” in order. The states of the nodes n 11 to n 14 are captured by the respective FFs 52 to 55 and are output as the output signals P 10 to P 13 in synchronism with the fall to “0” of the time-domain signal. By counting at this time the number of output signals whose state is “1”, among the output signals P 10 to P 13 , it is possible to specify, as a discrete value, up to which of the buffers 60 to 63 the state “1” has propagated during the period from the rise to the fall of the time-domain signal. Thus, the pulse width of the time-domain signal is digitized using the delay time of each buffer as a unit. With the circuit exemplified in FIG. 7 , numerical values from “0” to “4” can be expressed by means of the output signals P 10 to P 13 .

The time-domain signal turns to “0” at timing T 21 within the first full-scale time TF. By this time, the signals N 11 to N 13 have changed to “1”, but the signal N 14 still remains at “0” because of the delay time. In this case, therefore, the three output signals P 10 to P 12 turn to “1” while the output signal P 13 remains at “0”. Accordingly, the pulse width of the time-domain signal represents the digital value “3”.

After a lapse of the full-scale time TF for the first pulse of the time-domain signal (timing T 22 ), the encoder 71 captures the output signals P 10 to P 13 in synchronism with the rise of the clock signal and renders the captured data in a desired format, for example, in binary code (timing T 23 ). When the reset signal turns to “1” (timing T 24 ) during the time TD, the FFs 51 to 55 are all reset, so that the signal N 10 and the output signals P 10 to P 13 all turn to “0”. The reset signal again turns to “0” thereafter, and when the time-domain signal changes to “1”, signal processing of the next full-scale time TF starts (timing T 25 ). In the second full-scale time TF, the time-domain signal changes to “0” at timing T 26 . At this time, the signals N 11 and N 14 are in the state “1” and the signals N 12 and N 13 are in the state “0”. Accordingly, the output signals P 10 and P 13 turn to “1” while the output signals P 11 and P 12 remain at “0”. After a lapse of the full-scale time TF for the second pulse of the time-domain signal (timing T 27 ), the output signals P 10 to P 13 are captured by the encoder 71 (timing T 28 ). The signal P 13 turns to “1” because the signal N 14 , which changed to “1” during the first full-scale time TF, remains in the same state and the resetting at timing T 24 is not propagated yet at timing T 26 , and not because the rise to “1” of the time-domain signal has been propagated. To enable proper signal processing in such a situation, the encoder 71 may be provided with a mechanism whereby the output signals P 10 to P 13 are checked in this order to determine whether any signal assumes the state “0” indicating that the resetting has already been propagated at timing T 26 , and if the state “0” is detected, the values of the succeeding output signals are all corrected to “0”. In the above instance, the output signal P 11 is “0”, and accordingly, the encoder 71 corrects the output signals P 12 and P 13 to “0”, whereby the digital value “1” is derived as the pulse width of the time-domain signal.

In cases where analog signal information is represented along the time axis of a time-domain signal as in the conventional method, the S/N ratio is proportional to the full-scale time and is inversely proportional to the time resolution. If the full-scale time is prolonged, however, the signal processing speed lowers, and thus the full-scale time should not be substantially prolonged. Also, the time resolution has a limit determined by the operating speed and power consumption of devices such as transistors, giving rise to a problem that the time resolution cannot be set finely as desired.

Further, where a time-domain signal generated by a signal generating circuit is processed by a signal processing circuit such as the AD converting device shown in FIG. 7 , for example, a problem also arises in that a pulse width difference occurs due to a difference between the threshold used at the signal generating side to discriminate between “1” and “0”, and the threshold used at the signal processing side.

FIG. 9 illustrates such a pulse width difference attributable to a difference between the thresholds.

If the threshold used at the signal generating side to discriminate between “1” and “0” differs from that used at the signal processing side, a difference (offset) occurs between a pulse width tw 10 detected at the signal generating side and a pulse width tw 11 detected at the signal processing side, as shown in the figure, for example. The offset is a cause of lowering in the signal processing accuracy.

Also, it is occasionally the case that a pulse width offset occurs due to a difference (skew) between the time periods needed to process the rising and falling edges, respectively, of the time-domain signal in the signal processing circuit.

In the conventional AD converting device, for example, the rise of the time-domain signal and the rise of the signal N 10 should ideally take place at the same timing, and also the fall of the time-domain signal and the change of the output signals P 10 to P 13 should ideally take place at the same timing, as shown in the timing chart of FIG. 8 . In practice, however, delay exists between the rise of the time-domain signal and the actual output of “1” from the FF 51 and also between the fall of the time-domain signal applied to the FFs 52 to 55 through the inverter 70 and the capture of the states of the nodes n 11 to n 14 by the respective FFs, and these delays are not exactly equal in length. A problem therefore arises in that the pulse width of the time-domain signal is digitized inclusive of the pulse width difference caused by the delay.

According to an aspect of the embodiments, a signal processing method of processing a time-domain signal has receiving first and second time-domain signals, obtaining a difference between first and second pulse widths of the first and second time-domain signals, respectively, within a unit time for carrying one item of analog signal information, and treating the obtained difference as positive information if the first pulse width is greater than the second pulse width, or as negative information if the first pulse width is smaller than the second pulse width.

FIG. 1 is a diagram (diagram 1) illustrating a signal processing method according to an embodiment.

FIG. 2 is a diagram (diagram 2) also illustrating the signal processing method of the embodiment.

FIG. 3 shows pulses of two time-domain signals.

FIG. 4 is a circuit diagram exemplifying an AD converting device according to an embodiment.

FIG. 5 is a timing chart exemplifying the operation of the AD converting device of the embodiment.

FIG. 6 illustrates an exemplary case where a pulse width represents analog signal information.

FIG. 7 is a circuit diagram exemplifying a conventional AD converting device.

FIG. 8 is a timing chart exemplifying the operation of the conventional AD converting device.

FIG. 9 shows a pulse width difference caused by a difference between thresholds.

The embodiments provide a signal processing method for processing a time-domain signal. The signal processing method comprises the step of receiving time-domain signals S 1 and S 2 , as shown in FIG. 1 , the step of obtaining a difference between the pulse width ta 1 , ta 2 of the time-domain signal S 1 and the pulse width tb 1 , tb 2 of the time-domain signal S 2 within a unit time (full-scale time TF) for carrying one item of analog signal information, and the step of treating the obtained difference as positive information if the pulse width ta 1 , ta 2 is greater than the pulse width tb 1 , tb 2 , or as negative information if the pulse width ta 1 , ta 2 is smaller than the pulse width tb 1 , tb 2 .

With the above method, the information contained in the full-scale time TF is represented by the difference between the pulse width ta 1 , ta 2 of the time-domain signal S 1 and the pulse width tb 1 , tb 2 of the time-domain signal S 2 , and accordingly, the individual offset components of the time-domain signals S 1 and S 2 are canceled out. Also, the obtained difference is handled distinctively as positive or negative information, and thus information −TF through information +TF can be contained in one full-scale time TF.

There is also provided a signal processing device for processing a time-domain signal, wherein the signal processing device is input with first and second time-domain signals, obtains a difference between first and second pulse widths of the first and second time-domain signals, respectively, within a unit time for carrying one item of analog signal information, and treats the obtained difference as positive information if the first pulse width is greater than the second pulse width, or as negative information if the first pulse width is smaller than the second pulse width.

With this configuration, the difference between the first and second pulse widths of the first and second time-domain signals represents information contained in the unit time, and therefore, the individual offset components of the first and second time-domain signals are canceled out. Also, the pulse width difference is treated distinctively as positive or negative information, and thus, twice as much information can be carried per unit time.

There is also provided an analog/digital converting device for converting a time-domain signal to a digital value. The analog/digital converting device comprises a digital converter for receiving first and second time-domain signals, converting a first pulse width of the first time-domain signal within a unit time for carrying one item of analog signal information, into a first digital value, and converting a second pulse width of the second time-domain signal within the unit time into a second digital value, and a subtracter for subtracting the second digital value from the first digital value and treating a result of the subtraction as a digital value contained in the unit time.

With the above configuration, the digital converter receives the first and second time-domain signals, converts the first pulse width of the first time-domain signal within a unit time for carrying one item of analog signal information, into a first digital value, and converts the second pulse width of the second time-domain signal within the unit time into a second digital value. The subtracter subtracts the second digital value from the first digital value and treats the result of the subtraction as a digital value contained in the unit time.

Embodiments will be described in detail below with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

FIGS. 1 and 2 illustrate a signal processing method according to an embodiment.

As shown in FIG. 2 , a signal processing circuit 10 used in this embodiment receives two time-domain signals S 1 and S 2 from a signal generating circuit 11 . The time-domain signals S 1 and S 2 are pulse signals, as shown in FIG. 1 .

When input with the time-domain signals S 1 and S 2 shown in FIG. 1 , the signal processing circuit 10 obtains a difference between pulse widths ta 1 and tb 1 of the two time-domain signals S 1 and S 2 during the first full-scale time TF.

Specifically, the pulse width difference is obtained as follows. The time-domain signals S 1 and S 2 received from the signal generating circuit 11 have their rise timings aligned with each other, as shown in FIG. 1 , and the pulse width difference is obtained from a difference between the fall timings of the two signals. The fall timings of the time-domain signals S 1 and S 2 may be aligned instead, and the pulse width difference may be obtained from a difference between the rise timings of the two signals. Alternatively, the pulse width difference may be obtained using both the rise and fall timings of the signals.

Also, if the pulse width ta 1 of the time-domain signal S 1 is greater than the pulse width tb 1 of the time-domain signal S 2 , the signal processing circuit 10 treats the obtained difference as positive information, and if the pulse width ta 1 of the time-domain signal S 1 is smaller than the pulse width tb 1 of the time-domain signal S 2 , the signal processing circuit 10 treats the obtained difference as negative information. In the first full-scale time TF shown in FIG. 1 , for example, the pulse width ta 1 of the time-domain signal S 1 is greater (longer in time) than the pulse width tb 1 of the time-domain signal S 2 , and accordingly, the obtained difference ta 1 −tb 1 is handled as positive information.

In the next full-scale time TF, on the other hand, the pulse width ta 2 of the time-domain signal S 1 is smaller (shorter in time) than the pulse width tb 2 of the time-domain signal S 2 , and therefore, the obtained difference ta 2 −tb 2 is treated as negative information.

Then, the signal processing circuit 10 performs signal processing by using the positive or negative difference information as information of the corresponding full-scale time TF.

With the signal processing method, information −TF through information +TF can be represented in a single full-scale time TF. Namely, twice as much information can be carried per full-scale time TF. Thus, compared with the conventional case where the time-domain signal is used in the manner shown in FIG. 6 , the signal processing speed can be doubled without degrading the S/N ratio. In addition, the advantageous effects mentioned below can be obtained.

FIG. 3 shows pulses of the two time-domain signals.

In the figure, the pulses of the two time-domain signals S 1 and S 2 in the first full-scale time TF in FIG. 1 are shown enlarged. As stated above, the signal processing method of this embodiment uses the difference ta 1 −tb 1 between the two time-domain signals S 1 and S 2 , and not the pulse widths, as information of one full-scale time TF to be handled by the signal processing circuit 10 . Thus, even if the threshold used in the signal generating circuit 11 to discriminate between “1” and “0” differs from that used in the signal processing circuit 10 , the difference ta 1 −tb 1 remains unchanged. Namely, the pulse width offset component is canceled out and causes no error.

Also, the pulse width offset component arising out of the skew in the signal processing circuit 10 is canceled out by using the difference between the pulse widths of the two time-domain signals S 1 and S 2 .

Further, external noise attributable, for example, to power supply fluctuation in the signal generating circuit 11 can also be canceled out by using the pulse width difference, since such noise is applied to both of the two time-domain signals S 1 and S 2 .

As seen from the above, with the signal processing method according to the embodiment, analog signal information represented along the time axis of the time-domain signals can be processed with high accuracy and at high speed.

An AD converting device for converting the time-domain signals to digital values will be now described as an example of the signal processing circuit 10 .

FIG. 4 is a circuit diagram exemplifying an AD converting device according to an embodiment.

The AD converting device 20 includes FFs 21 to 29 , buffers 30 to 33 , inverters 40 and 41 , and an encoder 42 .

The FFs 21 to 29 each comprise a D flip-flop, for example, and each of the buffers 30 to 33 is constituted by a two-stage inverter.

The FF 21 has the function of capturing the pulse start timing of the time-domain signals S 1 and S 2 in the full-scale time TF. The FF 21 has a terminal D input with “1” at all times, and a terminal C input with a signal Set. The signal Set is, for example, a signal that turns to “1” synchronously with the rise timing of both time-domain signals S 1 and S 2 . When the signal Set changes from “0” to “1”, “1” applied to the terminal D is captured, held by the FF 21 , and also output from the output terminal Q. The signal Set may rise at timing slightly before or after the rise timing of both time-domain signals S 1 and S 2 , or the OR of the time-domain signals S 1 and S 2 may be used as the signal Set. A reset signal RST is input to the terminal R of the FF 21 . The signal Set, reset signal RST and clock signal CK are supplied, for example, from the signal generating circuit 11 shown in FIG. 2 or from a timing control circuit for externally controlling the timing of the signal generating circuit 11 and the signal processing circuit 10 in FIG. 2 .

The output signal from the output terminal Q of the FF 21 is input to the buffer 30 . The state of a node n 0 on the input side of the buffer 30 is transferred to a node n 1 after a delay corresponding to the delay time of the buffer 30 , transferred to a node n 2 after a delay corresponding to the delay times of the buffers 30 and 31 , transferred to a node n 3 after a delay corresponding to the delay times of the buffers 30 to 32 , and transferred to a node n 4 after a delay corresponding to the delay times of the buffers 30 to 33 . Thus, the series-connected buffers 30 to 33 function as a delay circuit, and the delay time provided by each buffer determines the time resolution of the AD converting device 20 .

The FFs 22 to 25 are input, at their terminals C, with the inverted time-domain signal S 1 via the inverter 40 , and the FFs 26 to 29 are input, at their terminals C, with the inverted time-domain signal S 2 via the inverter 41 . Also, the FFs 22 and 26 have their terminals D connected to the node n 1 , the FFs 23 and 27 have their terminals D connected to the node n 2 , the FFs 24 and 28 have their terminals D connected to the node n 3 , and the FFs 25 and 29 have their terminals D connected to the node n 4 .

Accordingly, the states of the nodes n 1 to n 4 are captured and held by the respective FFs 22 to 25 synchronously with the fall timing of the time-domain signal S 1 , and also the states of the nodes n 1 to n 4 are captured and held by the respective FFs 26 to 29 synchronously with the fall timing of the time-domain signal S 2 .

The reset signal RST is also input to the terminals R of the FFs 22 to 29 . When the reset signal RST turns to “1”, the FFs 22 to 29 are all reset to “0”.

Output signals P 1 to P 8 from the output terminals Q of the respective FFs 22 to 29 are input to the encoder 42 . In synchronism with the rise of the clock signal CK, for example, the encoder 42 captures the output signals P 1 to P 8 of the FFs 22 to 29 .

In FIG. 4 , the four buffers 30 to 33 and the FFs 22 to 29 for storing the states of the nodes n 1 to n 4 are illustrated for simplicity of illustration; in practice, the number of the buffers and of the FFs may be increased as desired.

Operation of the AD converting device 20 will be now described.

FIG. 5 is a timing chart exemplifying the operation of the AD converting device of the embodiment.

The figure shows the states of individual signals in the above AD converting device 20 , wherein N 0 to N 4 indicate signals appearing at the respective nodes n 0 to n 4 shown in FIG. 4 . Also, TF indicates the full-scale time, and the pulse width difference between the time-domain signals S 1 and S 2 within the full-scale time represents analog signal information. TD indicates the time necessary for the signal processing by the encoder 42 and the resetting of the FFs 21 to 29 .

At first, the reset signal RST is at “1”, and thus the FFs 21 to 29 are all reset, so that the signals N 0 to N 4 and the output signals P 1 to P 8 are all “0”. The reset signal RST turns to “0” thereafter, and when the time-domain signals S 1 and S 2 turn to “1”, the signal Set changes to “1”. In synchronism with the rise of the signal Set, the signal N 0 at the node n 0 changes to “1” (timing T 0 ). This change of the signal state is propagated to the nodes n 1 to n 4 while being successively delayed for the delay time of the buffers 30 to 33 , and as a consequence, the signals N 1 to N 4 change to “1” in order. The states of the nodes n 1 to n 4 are captured by the FFs 22 to 25 and the FFs 26 to 29 and output as the output signals P 1 to P 8 in synchronism with the falls to “0” of the respective time-domain signals S 1 and S 2 . By counting at this time the number of signals whose state is “1”, among the output signals P 1 to P 4 , it is possible to specify, as a discrete value, up to which of the buffers 30 to 33 the state “1” has been propagated during the period from the rise to the fall of the time-domain signal S 1 . Likewise, by counting the number of signals whose state is “1”, among the output signals P 5 to P 8 , it is possible to specify, as a discrete value, up to which of the buffers 30 to 33 the state “1” has been propagated during the period from the rise to the fall of the time-domain signal S 2 . Consequently, the pulse widths of the time-domain signals S 1 and S 2 are digitized using the delay time of each buffer as a unit. With the circuit exemplified in FIG. 4 , numerical values from “0” to “4” can be expressed by each set of the output signals P 1 to P 4 and the output signals P 5 to P 8 .

In the example shown in FIG. 5 , the time-domain signal S 2 turns to “0” at timing T 1 within the first full-scale time TF. By this time, the signal N 1 has changed to “1”, but the signals N 2 to N 4 still remain at “0” because of the delay time. In this case, therefore, the output signal P 5 turns to “1” while the output signals P 6 to P 8 remain at “0”. As a result, the pulse width of the time-domain signal S 2 is converted to the digital value “1”.

On the other hand, the time-domain signal S 1 turns to “0” at timing T 2 . By this time, the signals N 1 to N 3 have changed to “1”, but the signal N 4 still remains at “0” because of the delay time. In this case, therefore, the output signals P 1 to P 3 turn to “1” while the output signal P 4 remains at “0”. Thus, the pulse width of the time-domain signal S 1 represents the digital value “3”.

After a lapse of the full-scale time TF for the first pulses of the time-domain signals S 1 and S 2 (timing T 3 ), the encoder 42 captures the output signals P 1 to P 8 in synchronism with the rise of the clock signal CK. Then, the encoder 42 subtracts the digital value “1”, which is the pulse width of the time-domain signal S 2 represented by the output signals P 5 to P 8 , from the digital value “3”, which is the pulse width of the time-domain signal S 1 represented by the output signals P 1 to P 4 , and obtains the digital value “2”. The result of the subtraction may be rendered in a desired format, for example, in binary code by the encoder 42 (timing T 4 ). When the reset signal RST turns to “1” (timing T 5 ) during the time TD, the FFs 21 to 29 are all reset, so that the signal N 0 and the output signals P 1 to P 8 all turn to “0”. The reset signal RST again turns to “0” thereafter, and when the time-domain signals S 1 and S 2 change to “1”, the signal Set rises and signal processing of the next full-scale time TF starts (timing T 6 ).

In the second full-scale time TF, the time-domain signal S 1 changes to “0” at timing T 7 . At this time, the signals N 1 and N 4 are in the state “1” and the signals N 2 and N 3 are in the state “0”. Accordingly, the output signals P 1 and P 4 turn to “1” while the output signals P 2 and P 3 remain at “0”.

On the other hand, the time-domain signal S 2 changes to “0” at timing T 8 . At this time, the signals N 1 to N 3 are in the state “1” and the signal N 4 is in the state “0”. Thus, the output signals P 5 to P 7 turn to “1” while the output signal P 8 remains at “0”.

After a lapse of the second full-scale time TF (timing T 9 ), the encoder 42 captures the output signals P 1 to P 8 in synchronism with the clock signal CK. The output signals P 1 to P 4 captured at this time show “1001”. The output signal P 4 assumes the state “1” because the signal N 4 , which changed to “1” during the first full-scale time TF, remains in the same state and the resetting at timing T 5 is not propagated yet at timing T 7 , and not because the rise to “1” of the time-domain signals S 1 and S 2 has been propagated. To process the signals properly in such a situation, the encoder 42 may be provided with a mechanism whereby the output signals P 1 to P 4 and the output signals P 5 to P 8 are checked in this order to determine whether any signal assumes the state “0” indicating that the resetting has already been transmitted at timings T 7 and T 8 , respectively, and if the state “0” is detected, the values of the succeeding output signals are all corrected to “0”. In the above instance, the output signal P 2 is “0”, and accordingly, the encoder 42 corrects the output signals P 3 and P 4 to “0”, whereby the digital value “1” is derived as the pulse width of the time-domain signal S 1 .

The encoder 42 then subtracts the digital value “3”, which is the pulse width of the time-domain signal S 2 represented by the output signals P 5 to P 8 , from the digital value “1”, which is the pulse width of the time-domain signal S 1 , and obtains the digital value “−2”. The result of the subtraction may be rendered in a desired format, for example, in binary code by the encoder 42 (timing T 10 ).

With the AD converting device 20 described above, digital values corresponding to analog information from −TF to +TF can be represented by means of a single full-scale time TF. Namely, twice as much information can be handled per full-scale time TF. Consequently, compared with the case where the time-domain signal is used in the conventional manner as shown in FIG. 6 , the signal processing speed can be doubled without degrading the S/N ratio.

Further, by using the difference between the digital values converted from the pulse widths of the two time-domain signals S 1 and S 2 , it is possible to cancel out not only the pulse width offset component attributable to the threshold difference shown in FIG. 3 , but also the pulse width offset component arising from the skew in the converting device.

Moreover, external noise attributable, for example, to power supply fluctuation in the signal generating circuit 11 shown in FIG. 2 can also be canceled out by using the difference between the digital values converted from the pulse widths of the two time-domain signals S 1 and S 2 , since such noise is applied to both time-domain signals.

The aforementioned circuit configuration of the AD converting device 20 is given by way of example only and is not particularly limited. In the foregoing description, for example, the pulse widths of the time-domain signals S 1 and S 2 are converted to digital values at the fall timings of the respective time-domain signals. The time-domain signals S 1 and S 2 may be input such that their fall timings are aligned instead, by suitably adding or removing inverters, and the pulse widths obtained based on the rise timings may be converted to digital values. Alternatively, the pulse widths may be obtained using both the rise and fall timings of the time-domain signals.

The foregoing is considered as illustrative only of the principles of the embodiment. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.

According to the embodiment, information contained in a unit time for carrying one item of analog signal information is represented by the difference (positive or negative information) between the pulse widths of two time-domain signals within the unit time, whereby the individual offset components of the two time-domain signals are canceled out, enabling high-accuracy signal processing. Also, since the pulse width difference is treated distinctively as positive or negative information, twice as much information can be carried per unit time, making it possible to improve the signal processing speed.

The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.