Method and system for routing data in a parallel turbo decoder

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Turbo codes are a class of high-performance error correction codes that were first described by Berrou, Glavieux, and Thitimajshima in their 1993 paper: “Near Shannon Limit error-correcting coding and decoding: Turbo-codes” published in the Proceedings of IEEE International Communications Conference in 1993. Turbo codes may be used to maximize the information transfer rate over a limited-bandwidth communication link in the presence of data-corrupting noise. Limitations and disadvantages of Turbo codes may include a relatively high decoding complexity and a relatively high latency.

Limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

These and other advantages and novel features of the present invention will be more fully understood from the following description.

FIG. 1 is a diagram that illustrates a system for routing data in a parallel Turbo decoder in accordance with an embodiment of the present invention;

FIG. 2 is a flow diagram that illustrates a method for routing data in a parallel Turbo decoder in accordance with an embodiment of the present invention;

FIG. 3 is a diagram that illustrates an improved system for routing data in a parallel Turbo decoder in accordance with an embodiment of the present invention; and

FIG. 4 is a flow diagram that illustrates an improved method for routing data in a parallel Turbo decoder in accordance with an embodiment of the present invention.

Turbo codes may be used to communicate data between battery powered wireless consumer devices. Wireless communication devices such as phones and PDAs may be rated by their speed, cost and battery life. Accordingly, there is a need for reducing the physical size, power consumption and latency of circuits that perform Turbo decoding within these devices. Aspects of the present invention address the need for reducing the physical circuit area, power consumption and/or latency in a parallel Turbo decoding architecture.

Address routing networks in a parallel Turbo decoder may affect the overall size, speed and power consumption of an integrated circuit that performs parallel Turbo decoding. According to certain aspects of the present invention, address routing networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.

FIG. 1 is a diagram that illustrates a system for routing data in a parallel Turbo decoder ( 100 ) in accordance with an embodiment of the present invention. The system for routing data in a parallel Turbo decoder ( 100 ) consists of N processor (P 0 , P 1 , . . . P N-1 ); M memory banks (B 0 , B 1 , . . . B M-1 ); an address routing-network ( 101 ); and a data routing-network ( 103 ). The system for routing data in a parallel Turbo decoder ( 100 ) is illustrated with N=4 and M=4.

Each of the processors (P 0 , P 1 , P 2 , P 3 ,) may decode a segment of a turbo codeword. Each of the memory banks (B 0 B 1 , B 2 , B 3 ) may store values that correspond to data items at multiple positions within the turbo codeword. These values may be used by the processors to perform turbo decoding.

The address routing-network ( 101 ) may be used by the processors to calculate memory addresses, which correspond to the memory banks. The data routing-network ( 103 ) may be used to transfer data between the processors and the memory banks.

Data routing, in FIG. 1 , may comprise the steps that are illustrated in FIG. 2 . Each processor P i may be required to operate on the data item at position k i . The index of the memory bank that comprises that data item is determined at 201 . Each of the N processors {i: 0≦i<N:P i } may compute the number of the memory bank, j=M(k i ), that contains the storage for the data item at position k i .

A processor-based address that corresponds to the data within the memory bank, B j , may be determined at 203 . Each processor P i may compute the address, A(k i ), within B j , that corresponds to the storage for the data item at position k i .

At 205 , the processor-based address may be converted to a memory-based address. The set of addresses {i: 0≦i<N: A(k i )} for the N processors may be routed to the set of addresses {j: 0≦j<M: A(m j )} for the memory banks, using the address routing-network ( 101 ). The address routing-network ( 101 ) may convert the addresses from being a function of the processor number (i) to being a function of the memory bank number (j). For example, address, A(k i ), is mapped to address, A(m j ), where j=M(k i ).

At 207 , data may be routed between the processor and the corresponding memory bank according to the memory-based address. Using the value of A(m j ) as the address, each memory bank B j may access the storage for the data item at position k i , where j=M(k i ). The set of data items {i:0≦i<N: L(k i )} for the processors may be routed back and forth as the set of data items {j: 0≦j<M: L(m j )} accessed by the memory banks, using the data routing-network ( 103 ). The data routing-network ( 103 ) may convert the data items from being a function of the memory bank number (j) to being a function of the processor number (i); or vise versa, i.e. from being a function of the processor number (i) to being a function of the memory bank number (j). For example, data item, L(k i ), is mapped to data item, L(m j ), where j=M(k i ).

FIG. 3 is a diagram that illustrates an improved system for routing data in a parallel Turbo decoder ( 300 ) in accordance with an embodiment of the present invention. The system for routing data in a parallel Turbo decoder ( 300 ) consists of N processor (P 0 , P 1 , . . . P N-1 ); M memory banks (B 0 , B 1 , . . . B M-1 ); M address generation modules (G 0 , G 1 , . . . G M-1 ); and a data routing-network ( 301 ). The improved system for routing data in a parallel Turbo decoder is illustrated with N=4 and M=4.

The system for routing data in a parallel Turbo decoder ( 300 ) of FIG. 3 may eliminate the need for the address routing-network ( 101 ) of FIG. 1 by introducing the address generation modules. Address generation module G j {j: 0≦j<M} may be dedicated to generating the address values for memory bank B j .

Data routing, in FIG. 3 , may comprise the steps that are illustrated in FIG. 4 . Each of the N processors {i: 0≦i<N: P i } operates on the data item at position k i . The index of the memory bank that comprises that data item is determined at 401 . Each processor P i may compute the number of the memory bank, j=M(k i ), that contains the storage for the data item at position k i .

A memory-based address that corresponds to the data within the memory bank, B j , may be determined at 403 . Each address generation module, G j , may compute A(m j ), the address for bank B j , such that A(m j )=A(k i ), if j=M(k i ).

At 405 , data may be routed between the processor and the corresponding memory bank according to the memory-based address. Using the value of A(m j ) as the address, each memory bank B j may access the storage for the data item at position k i , where j=M(k i ). The set of data values {i:0≦i<N: L(k i )} for the processors may be routed back and forth as the set of data values {j: 0≦j<M : L(m j )} accessed by the memory banks, using the data routing-network ( 301 ). The data routing-network ( 301 ) may convert the data items from being a function of the memory bank number (j) to being a function of the processor number (i); or vise versa, i.e. from being a function of the processor number (i) to being a function of the memory bank number (j). For example, data item, L(k i ), is mapped to data item, L(m j ), where j=M(k i ).

In FIG. 3 , each address generation module G j may compute A(m j ), such that j=M(k i ) for some k i . A(m j ) may be a function of the index of the memory bank (j) and the step number in the decoding process. The actual computation performed by G j may depend on an interleaver function of the turbo code π, the memory-mapping function M, and the address function A.

The arrangement of the input to the interleaver is considered a natural-order, and the arrangement of the output from the interleaver is considered an interleaved-order. In step t of a natural-order phase, processor P i may process the data item at position t+Wi. In step t of an interleaved-order phase, processor P i may process the data item at position π(t+Wi). Also, A N (j,t) denotes the value of A(m j ) at step t of the natural-order phase, and A I (j,t) denote the value of A(m j ) at step t of the interleaved-order phase.

The computation performed by G j depends on the interleaver function (π), the memory-mapping function (M), and the address function (A). The interleaver may be divided into sub-blocks of size W, and interleaver positions may be designated as k. In a first exemplary case, the memory-mapping function (M) is a DIV operation and the address function (A) is a MOD function as follows:

M ( k )= └k/W┘   EQ. 1

A ( k )=( k mod W )   EQ. 2

In this first exemplary case, the computations performed by G j are as follows:

A N ( j,t )= t   EQ. 3

A I ( j,t )=π( t )   EQ. 4

In a second exemplary case, the memory-mapping function (M) is a MOD operation and the address function (A) is a MOD function as follows:

M ( k )=( k mod N )   EQ. 5

A ( k )=( k mod W )   EQ. 6

A quadratic permutation polynomial (QPP) is an example of one type of interleaver function. In this second exemplary case, the following QPP interleaver function of length L=24 is used:

π( x )=( x+ 6 x 2 ) mod 24   EQ. 7

This QPP interleaver function may be associated with an interleaver that contains 3 sub-blocks of size W=8 and system parameters of N=3 and M=3. The computations performed by G j in this second exemplary case are as follows:

A N ( j,t )= t   EQ. 8

A I ( j,t )=(π((16 j+ 9 t ) mod 24) mod W )   EQ. 9

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention.

Additionally, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. For example, although the invention has been described with a particular emphasis on a hardware circuit design, the invention may also be applied to a software design in a wide variety of languages.

Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.