Apparatus and method for unity gain buffer with high switching speed and low quiescent current

The invention is related to unity gain buffers, and in particular, to an apparatus and method for a unity gain buffer that adjusts the bias current provided to base-emitter junctions in the unity gain buffer based on changes to the input voltage.

A unity gain buffer may be used to provide high current driving capability while keeping the ratio of output voltage to input voltage close to unity. Desired characteristics for a unity gain buffer design are listed below:

1. Capable of delivering high current to output load. 2. High output switching speed. 3. Output voltage to input voltage ratio close to unity. 4. Low quiescent current.

However, improving the characteristics numbered 1-3 above generally require high quiescent current, and therefore improving characteristics 1-3 above are generally done at the expense of characteristic 4 (low quiescent current) above.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings, in which:

FIG. 1 shows a block diagram of a unity gain buffer;

FIG. 2 illustrates a block diagram of an embodiment of the unity gain buffer of FIG. 1 ;

FIG. 3 shows a block diagram of an embodiment of the unity gain buffer of FIG. 2 ;

FIG. 4 illustrates a block diagram of an embodiment of the unity gain buffer of FIG. 3 ; and

FIG. 5 shows a block diagram of an embodiment of the unity gain buffer of FIG. 4 , arranged in accordance with aspects of the invention.

Various embodiments of the present invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. Similarly, the phrase “in some embodiments,” as used herein, when used multiple times, does not necessarily refer to the same embodiments, although it may. As used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based, in part, on”, “based, at least in part, on”, or “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. Where either a field effect transistor (FET) or a bipolar junction transistor (BJT) may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa.

Briefly stated, the invention is related to a unity gain buffer that includes two complementary pairs of emitter followers and two bias current sources. The top bias current source is arranged to provide a bias current so that, if the input voltage is greater than zero, the bias current provided by the top current source increases at the input voltage increases. The bottom current source is arranged to provide a bias current so that, if the input voltage is less than zero, the bias current provided by the bottom current source decreases at the input voltage decreases.

FIG. 1 shows a block diagram of unity gain buffer 100 . Unity gain buffer 100 includes bias current sources 121 and 122 , bias control circuits 131 and 132 , and translinear loops 111 and 112 . Translinear loop 111 includes translinear elements 141 and 142 . Similarly, translinear loop 112 includes translinear elements 143 and 144 .

In operation, translinear loops 111 and 112 cause output voltage Output to follow the input voltage Input so that the output voltage Output is substantially the same as the input voltage Input. Bias current source 121 is arranged to provide bias current Ibias 1 to translinear loop 111 , and bias current source 122 is arranged to provide bias current Ibias 2 to translinear loop 112 .

Further, bias currents Ibias 1 and Ibias 2 should be sufficiently strong so that the output stage (translinear elements 142 and 144 ) is capable of both sourcing (sinking) current and keeping the output voltage high enough to satisfy unity gain requirement. This is accomplished by adjusting currents Ibias 1 and Ibias 2 based on input voltage Input. Bias control circuit 131 is arranged to adjust bias current source 121 so that, if input voltage Input is greater than zero, Ibias 1 =A+B*Input, where A and B are positive constants. If input voltage Input is zero volts or less, Ibias 1 =A. This way, if input voltage Input is greater than zero, bias current Ibias 1 includes a component that is proportional to input voltage Input. Accordingly, as input voltage Input increases to higher positive values, Ibias 1 is high enough that transistor Q 2 has enough drive strength to pull up the output voltage Output to the input voltage Input without increasing the quiescent current.

Similarly, bias control circuit 132 is arranged to adjust bias current source 122 so that, if input voltage Input is less than zero, Ibias 2 =A+B*|Input|, where A and B are positive constants. If input voltage Input is zero volts or more, Ibias 2 =A. Accordingly, as input voltage Input decreases to lower negative values, Ibias 2 is high enough that transistor Q 4 has enough drive strength to pull down the output voltage Output to the input voltage Input without increasing the quiescent current. The output stage (translinear elements 142 and 144 ) can source and sink high currents as needed for the output voltage to follow the input voltage over a wide voltage swing, without increasing the quiescent current.

FIG. 2 illustrates a block diagram of an embodiment of unity gain buffer 200 driving a load represented by RLOAD. Unity gain buffer 200 may be employed as an embodiment of unity gain buffer 100 of FIG. 1 . Unity gain buffer 200 includes transistors Q 1 -Q 4 , bias current sources 121 and 122 , and bias control circuits 131 and 132 . In unity gain buffer 200 , the base-emitter junction of transistor Q 1 is an embodiment of translinear element 141 , the base-emitter junction of transistor Q 2 is an embodiment of translinear element 142 , the base-emitter junction of transistor Q 3 is an embodiment of translinear element 143 , and the base-emitter junction of transistor Q 4 is an embodiment of translinear element 144 .

Transistors Q 1 -Q 2 and Q 3 -Q 4 form two complementary pairs of emitter followers, allowing output voltage Output to follow input voltage Input and keep the output voltage magnitude close to that of the input voltage. Bias current source 221 is arranged to provide bias current Ibias 1 to Q 1 -Q 2 . Similarly, bias current source 222 is arranged to provide bias current Ibias 2 to Q 3 -Q 4 .

Although bias control circuit 231 and bias control circuit 232 are each shown as having an input that is connected the input voltage Input at node N 5 , this need not literally be the case, although it may be in some embodiments. The input is shown at node N 5 to illustrate that the output of the bias control circuit is changed based on input voltage Input. However, the input of the bias control circuit need not be directly connected to node N 5 , as long as the bias control circuit controls the bias current based on input voltage Input in the manner discussed above. For example, in one embodiment, bias control circuit 231 is arranged to detect changes in input voltage input for a positively-going input based on changes in the collector current of Q 1 and bias control circuit 232 is arranged to detect changes in input voltage Input for a negatively-going input based on changes in the collector current of Q 3 . These embodiments and others are within the scope and spirit of the invention.

FIG. 3 shows a block diagram of an embodiment of unity gain buffer 300 driving a load represented by RLOAD. Unity gain buffer 300 may be employed as an embodiment of unity gain buffer 200 of FIG. 2 . Unity gain buffer 300 further includes transistor Q 1 ′ and transistor Q 3 ′.

Transistors Q 1 ′ and Q 3 ′ are arranged to increase the magnitude of currents Ibias 1 or Ibias 2 during output switching, accordingly increasing the switching speed.

For a positively going input signal, a negative pulse is generated at node N 3 , which temporarily increases current Ibias 1 and the base current of transistor Q 2 , making Q 2 stronger. Additionally, increased current on transistor Q 3 ′ reduces the base current of transistor Q 4 , making transistor Q 4 weaker. These two mechanisms cause output voltage Output to be quickly switched from low to high. Both the negative pulse at node N 3 and the reduction in base current of transistor Q 4 are relatively brief; the duration of these temporary changes is over when the output switching is complete.

For a negatively going input signal, a positive pulse is generated at node N 4 , which temporarily increases current Ibias 2 and the base current of transistor Q 4 , making transistor Q 4 stronger. Additionally, increased current on Q 1 ′ reduces base current of transistor Q 2 , making transistor Q 2 weaker. These two mechanisms cause output voltage Output to be quickly switched from high to low.

In either case, the pulses generated on nodes N 3 and N 4 caused by transistor Q 3 ′ and Q 1 ′ last for a relatively short period of time. After switching, Q 1 ′ and Q 3 ′ no longer adjust nodes N 3 and N 4 .

In one embodiment, bias control circuits ( 331 and 332 ) are arranged to cause a delay in the change caused at their output based on changes in input voltage Input. In one embodiment, the delay is longer than the duration of the pulse caused by transistor Q 1 ′ and transistor Q 3 ′. This way, the increase to switching speed caused by transistors Q 1 ′ and Q 3 ′ are not affected by the bias controls circuits 331 and 332 .

Transistors Q 1 ′ and Q 3 ′ enable nodes N 1 and N 2 to be charged and discharged relatively quickly in order to achieve high switching speeds. Nodes N 1 and N 2 are both heavily capacitively loaded. However, transistors Q 1 ′ and Q 3 ′ enable relatively fast switching speed without increasing quiescent current.

FIG. 4 illustrates a block diagram of an embodiment of unity gain buffer 400 driving a load represented by RLOAD. Unity gain buffer 400 may be employed as an embodiment of unity gain buffer 300 of FIG. 3 . Bias control circuit 431 includes resistor R 2 , capacitor C 2 , transistor Q 9 , transistor Q 10 , and adjustable current source 423 . Similarly, bias control circuit 432 includes resistor R 1 , capacitor C 1 , transistor Q 7 , transistor Q 8 , and adjustable current source 424 .

Resistor R 1 and capacitor C 1 are arranged to operate as a low-pass filter that provides a delay, isolating the voltage at node N 7 from the voltage at node N 4 . This delay allows the changes in the voltage at node N 4 caused by transistor Q 1 ′ to not be affected by the operation of bias control circuit 432 . Transistor Q 1 ′ generates a relatively brief positive voltage pulse at node N 4 for a negatively going input signal, allowing the change in output voltage Output to occur more quickly. The low-pass filter (formed by R 1 and C 1 ) creates a delay which causes the effect of bias control circuit 432 to the change in output voltage Output to not occur until after the positive voltage pulse caused by transistor Q 1 ′ has ended.

Adjustable current source 424 is arranged to provide a voltage that is substantially constant if input voltage Input is zero or greater. If input voltage Input is less than zero, then the current provided by adjustable current source 424 is the substantially constant current plus an additional current component that is proportional to the magnitude of input voltage Input. The current provided by adjustable current source 424 is mirrored by Q 7 /Q 6 to provide current Ibias 2 , subject to the isolation and delay caused by low-pass filter R 1 /C 1 as discussed above. Transistor Q 8 biases transistor Q 7 to ensure that transistor Q 7 is on.

Bias control circuit 432 operates in a similar manner, albeit different, to that discussed above with regard to bias control circuit 431 . Resistor R 2 and capacitor C 2 form a low-pass filter that isolates node N 8 from node N 3 .

FIG. 5 shows a block diagram of an embodiment of the unity gain buffer 500 driving a load representing by RLOAD. Unity gain buffer 500 may be employed as an embodiment of unity gain buffer 400 of FIG. 3 . Bias current source 521 further includes resistor R 4 . Bias current source 522 further includes resistor R 3 . Bias control circuit 532 further includes resistors R 5 , R 6 , and R 9 ; transistor Q 12 , Q 15 , and Q 16 ; and current source 450 . Bias control circuit 531 further includes resistors R 7 , R 8 , R 10 , and R 11 ; and transistors Q 11 , Q 13 , Q 14 , and Q 17 .

For a positively going input voltage Input, when the magnitude of input voltage Input increases, the base current of transistor Q 2 increases, which causes the emitter current of transistor Q 1 to decrease, which in turn causes current I 5 to decrease, which in turn causes current I 4 to increases. Since current I 4 is mirrored to provide current Ibias 1 (subject to the delay), current Ibias 1 is increased after the delay.

For a negatively going input, when the input voltage decreases (goes to a more negative value), the base current of Q 4 increases, which causes the emitter current of transistor Q 4 to decrease, which in turn causes current I 2 to decrease, which in turn causes current I 3 to increase. Since current I 3 is mirrored to provide current Ibias 2 (subject to the delay), current Ibias 2 is increased after the delay.

Additionally, current source 450 provides a fixed current that does not change with the input voltage. The current provided by current source 450 is mirrored by current mirror Q 15 /Q 12 in bias control circuit 531 , and is mirrored by current mirror Q 15 /Q 17 in bias current circuit 532 .

As discussed above, bias control circuit 531 is arranged to adjust bias current source 521 so that, if input voltage Input is greater than zero, Ibias 1 =A+B*Input, where A and B are positive constants. If input voltage Input is zero volts or less, Ibias 1 =A. Similarly, bias control circuit 132 is arranged to adjust bias current source 122 so that, if input voltage Input is less than zero, Ibias 2 =A+B*|Input|, where A and B are positive constants. If input voltage Input is zero volts or more, Ibias 2 =A. The current “A” is determined by current source 450 and the current mirror ratios. In an embodiment in which the current mirrors are all 1:1, the current provided by current source 450 is “A”.

Unity gain buffer 500 may be used in many applications. One possible application for unity gain buffer 500 is in a class AB audio amplifier driving speaker load. Using unity gain buffer 500 in a class AB audio amplifier driving speaker load allows less quiescent current in the amplifier, so that less heating occurs in the amplifier. However, the invention is not limited to audio amplifiers, and unity gain amplifier 500 may be used in many other applications.

The above specification, examples, and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.