Enhancement-mode field effect transistor based electrostatic discharge protection circuit

This application is related to U.S. patent application Ser. No. 11/609,497 entitled ON-CHIP ESD PROTECTION CIRCUIT FOR RADIO FREQUENCY (RF) INTEGRATED CIRCUITS filed Dec. 12, 2006, the disclosure of which is hereby incorporated herein by reference in its entirety.

The present invention relates to electrostatic discharge (ESD) protection circuits, which may be used to protect other circuits from the high voltages associated with ESD events.

Electrostatic discharge (ESD), which is a large subset of electrical overstress (EOS), is a major reliability issue in integrated circuits (ICs). As semiconductor devices have scaled to smaller dimensions and ICs have become more complex, the potential for destructive ESD events has become more serious. More recently, there has been a tremendous demand for increasing the ESD robustness of Radio Frequency (RF) ICs, especially for wireless applications, such as handheld devices.

ESD protection for Silicon-based technologies, such as complementary metal oxide semiconductor (CMOS) technology, is relatively mature. However, ESD protection circuitry for newer technologies, particularly those involving compound semiconductor materials, such as Gallium Arsenide, is still in its infancy. Compound semiconductor materials are those compounds formed from multiple elements from the periodic table of the elements.

Gallium Arsenide is often used for RF power amplifiers and RF switches because of its intrinsically high low-field electron mobility and breakdown voltage. For RF low noise amplifiers, RF switches, and RF power amplifiers, Gallium Arsenide pseudomorphic high electron mobility transistor (pHEMT) technology may be used. However, ESD protection circuitry for Gallium Arsenide pHEMT technology that is currently in use provides undesirable characteristics. Gallium Arsenide pHEMT ESD protection structures may have unwanted parasitic capacitances and resistances which may adversely affect performance of RF circuits. Ideally, an ESD protection circuit must not affect an input or output signal under normal operating conditions and must not affect the normal operation of the circuit it is protecting. At RF frequencies, the parasitics associated with the ESD protection structures can lead to impedance mismatches, which may cause signal reflection that degrades the performance of the circuit that it is protecting. Thus, there is a need for an ESD protection circuit that has small parasitic capacitance, is linear over a wide frequency range, and can be integrated with other compound semiconductor-based circuits on a single-die.

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity and small size of the single FET element ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

The FET element may include a compound semiconductor material, such as Gallium Arsenide, Indium Phosphide, Gallium Nitride, various combinations of elements from columns III and V of the periodic table of the elements, or any combination thereof. Embodiments of the present invention may include compound semiconductor junction field effect transistor (JFET) elements, pseudomorphic high electron mobility transistor (pHEMT) elements, high electron mobility transistor (HEMT), modulation-doped field effect transistor (MODFET) elements, heterojunction-insulator-gate field effect transistor (HIGFET) elements, metal-semiconductor field effect transistor (MESFET) elements, or any combination thereof. These FET elements can be normally-off devices which require a positive gate bias to turn the devices on. These normally-off devices are termed enhancement-mode devices and may be configured as multiple FET elements coupled in series, multiple FET elements coupled in parallel, single-gate FET elements, multi-gate FET elements, or any combination thereof.

Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention.

FIG. 1 shows electrostatic discharge (ESD) clamp circuits coupled to an ESD protected circuit, according to one embodiment of the present invention.

FIG. 2 shows the ESD clamp circuits illustrated in FIG. 1 coupled to a direct current (DC) power supply instead of ground, according to an alternate embodiment of the present invention.

FIG. 3 shows the ESD clamp circuits illustrated in FIG. 1 coupled to a complementary metal oxide semiconductor (CMOS) power supply line, according to another embodiment of the present invention.

FIG. 4 shows the ESD clamp circuit illustrated in FIG. 1 as part of an impedance matching network, according to an additional embodiment of the present invention.

FIG. 5 shows details of the ESD clamp circuit, which includes an enhancement-mode field effect transistor (FET) element and a first resistive element coupled between a gate and a source of the enhancement-mode FET element, according to a first embodiment of the ESD clamp circuit.

FIG. 6 shows a series resistive element coupled in series with the enhancement-mode FET element illustrated in FIG. 5 , according to a second embodiment of the ESD clamp circuit.

FIG. 7 shows multiple enhancement-mode FET elements coupled in series, according to third embodiment of the ESD clamp circuit.

FIG. 8 shows the multiple enhancement-mode FET elements coupled in series with the series resistive element, according to a fourth embodiment of the ESD clamp circuit.

FIG. 9 shows a multi-gate enhancement-mode FET element according to a fifth embodiment of the ESD clamp circuit.

FIG. 10 shows the multi-gate enhancement-mode FET element coupled in series with the series resistive element, according to a sixth embodiment of the ESD clamp circuit.

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

The FET element may include a compound semiconductor material, such as Gallium Arsenide, Indium Phosphide, Gallium Nitride, various combinations of elements from columns III and V of the periodic table of the elements, or any combination thereof. The FET element may include compound semiconductor junction field effect transistor (JFET) elements, pseudomorphic high electron mobility transistor (pHEMT) elements, high electron mobility transistor (HEMT) elements, modulation-doped field effect transistor (MODFET) elements, heterojunction-insulator-gate field effect transistor (HIGFET) elements, metal-semiconductor field effect transistor (MESFET) elements, or any combination thereof. These FET elements can be normally-off devices, which require a positive gate bias to turn the devices on. These normally-off devices are termed enhancement-mode devices and can be configured as multiple FET elements coupled in series, multiple FET elements coupled in parallel, single-gate FET elements, multi-gate FET elements, or any combination thereof.

FIG. 1 shows ESD clamp circuits 10 coupled to an ESD protected circuit 12 , according to one embodiment of the present invention. Each ESD clamp circuit 10 has a first terminal FT coupled to a node to be protected, and a second terminal ST coupled to a direct current (DC) reference, such as ground. Normally, the ESD clamp circuit 10 is in a non-clamping state, such that a high impedance is presented between the first and second terminals FT, ST; however, when the voltage between the first and second terminals FT, ST exceeds an ESD trigger voltage, which may be associated with an ESD event, the ESD clamp circuit 10 transitions to a clamping state, such that a low impedance is presented between the first and second terminals FT, ST to dissipate energy associated with the ESD event to protect the ESD protected circuit 12 . The ESD trigger voltage may vary depending on a rise time of the voltage between the first and second terminals FT, ST. Additionally, the ESD trigger voltage may vary depending on whether the voltage of an ESD event at the first terminal FT is positive with respect to the voltage at the second terminal ST, or vice versa. In one embodiment of the present invention, when the voltage of an ESD event at the first terminal FT is positive with respect to the voltage at the second terminal ST, the ESD trigger voltage ranges from about 10 volts to about 20 volts. In an exemplary embodiment of the present invention, when the voltage of an ESD event at the first terminal FT is positive with respect to the voltage at the second terminal ST, the ESD trigger voltage ranges from about 14 volts to about 16 volts.

The ESD protected circuit 12 has a power supply input PSINP coupled to a DC power supply V PSUPPLY , a signal input SIGINP, which receives an input signal V INPS , and a signal output SIGOUT, which provides an output signal V OUTPS . An ESD clamp circuit 10 may be coupled to and protect the power supply input PSINP, the signal input SIGINP, the signal output SIGOUT, or any combination thereof. An ESD clamp circuit 10 may be coupled to any or all of the nodes of the ESD protected circuit 12 to provide ESD protection where needed.

FIG. 2 shows the ESD clamp circuits 10 illustrated in FIG. 1 with each second terminal ST coupled to the DC power supply V PSUPPLY instead of to ground, according to an alternate embodiment of the present invention. Such a configuration may be useful for circuits having the DC power supply V PSUPPLY distributed throughout the ESD protected circuit 12 . An ESD clamp circuit 10 may be used to protect ground from ESD events with respect to the DC power supply V PSUPPLY .

FIG. 3 shows the ESD clamp circuit 10 illustrated in FIG. 1 with each second terminal ST coupled to a complementary metal oxide semiconductor (CMOS) controller power supply V CMOSSUPPLY instead of the DC power supply V PSUPPLY , according to another embodiment of the present invention.

FIG. 4 shows the ESD clamp circuit 10 as part of an impedance matching network 14 coupled between an input of an amplifier 16 and a receiving antenna 18 , according to an additional embodiment of the present invention. The impedance matching network 14 may include a series circuit 20 coupled between the receiving antenna 18 and the input of the amplifier 16 , and a shunt circuit 22 coupled between the input of the amplifier 16 and ground.

The first terminal FT of the ESD clamp circuit 10 may be coupled to the receiving antenna 18 to protect the amplifier 16 from ESD events. The impedance of the ESD clamp circuit 10 during the non-clamping state may be combined with the impedances of the series and shunt circuits 20 , 22 to provide a proper impedance match. Alternate embodiments of the present invention may include any number of series circuits 20 , any number of shunt circuits 22 , any number of ESD clamp circuits 10 , or any combination thereof.

FIG. 5 shows details of the ESD clamp circuit 10 , which includes an enhancement-mode FET element QE 1 , according to a first embodiment of the ESD clamp circuit 10 . A drain of the enhancement-mode FET element QE 1 is coupled to the first terminal FT, and a source of the enhancement-mode FET element QE 1 is coupled to the second terminal ST. A first resistive element R 1 is coupled between a gate of the enhancement-mode FET element QE 1 and the second terminal ST. The enhancement-mode FET element QE 1 has an ON state, which corresponds with the clamping state, and an OFF state, which corresponds with the non-clamping state. The first resistive element R 1 biases the gate of the enhancement-mode FET element QE 1 such that during normal operation, the enhancement-mode FET element QE 1 is in the OFF state.

The enhancement-mode FET element QE 1 may be a JFET element, a pHEMT element, a MODFET element, a HIGFET element, a HEMT element, a MESFET element, or any combination thereof. The enhancement-mode FET element QE 1 may include compound semiconductor material such as Gallium Arsenide, Indium Phosphide, Gallium Nitride, various combinations of elements from columns III and V of the periodic table of the elements, or any combination thereof.

FIG. 6 shows details of the ESD clamp circuit 10 , which include a series resistive element RS, according to a second embodiment of the ESD clamp circuit 10 . During the ON state, the enhancement-mode FET element QE 1 may have an ON state resistance between the drain and the source, and a maximum ON state drain-to-source voltage. An ESD event may be characterized by an ESD voltage, which may be thousands of volts, fed from a capacitance, such as a human body. When the enhancement-mode FET element QE 1 is dissipating the energy from an ESD event during the clamping state, the current provided by the ESD event through an ON state resistance between the drain and the source must not cause the drain-to-source voltage to exceed a maximum ON state drain-to-source voltage, otherwise the enhancement-mode FET element QE 1 may be damaged.

The series resistive element RS is coupled between the drain of the enhancement-mode FET element QE 1 and the first terminal FT to limit the current through the enhancement-mode FET element QE 1 during an ESD event. By limiting the current, the drain-to-source voltage may be held within the maximum ON state drain-to-source voltage; however, adding resistance may reduce the effectiveness of the ESD clamp circuit 10 to protect from ESD events. Therefore, the value of the series resistive element RS may be chosen to balance the ruggedness of the ESD clamp circuit 10 and the ruggedness of the ESD protected circuit 12 . In an exemplary embodiment of the present invention, the maximum ON state drain-to-source voltage is about 12 volts. A resistance of the series resistive element RS may be less than about 20 ohms. In an exemplary embodiment of the present invention, the resistance of the series resistive element RS is about 10 ohms.

The enhancement-mode FET element QE 1 may be a JFET element, a pHEMT element, a MODFET element, a HIGFET element, a HEMT element, a MESFET element, or any combination thereof. The enhancement-mode FET element QE 1 may include compound semiconductor material such as Gallium Arsenide, Indium Phosphide, Gallium Nitride, various combinations of elements from columns III and V of the periodic table of the elements, or any combination thereof.

FIG. 7 shows multiple enhancement-mode FET elements QE 1 , QE 2 , QEX coupled in series, according to a third embodiment of the ESD clamp circuit 10 . The drain of one enhancement-mode FET element is coupled to the source of another enhancement-mode FET element. At least the second enhancement-mode FET element QE 2 is coupled between the drain of the first enhancement-mode FET element QE 1 and the first terminal FT. First, second, up to and including Xth resistive elements R 1 , R 2 , RX are coupled between the gates of each of the multiple enhancement-mode FET elements QE 1 , QE 2 , QEX and the second terminal ST. For example, an Xth resistive element RX is coupled between the gate of the Xth enhancement-mode FET element QEX and the second terminal ST. The series coupling may allow each of the multiple enhancement-mode FET elements QE 1 , QE 2 , QEX to be smaller, and may increase the maximum voltage between the first and second terminals FT, ST during the clamping state, thereby increasing the energy rating of the ESD clamp circuit 10 . Additionally, reducing the size of the multiple enhancement-mode FET elements QE 1 , QE 2 , QEX may reduce parasitic capacitances and improve linearity of the ESD clamp circuit 10 .

The multiple enhancement-mode FET elements QE 1 , QE 2 , QEX may include at least one JFET element, at least one pHEMT element, at least one MODFET element, at least one HIGFET element, at least one HEMT element, at least one MESFET element, or any combination thereof. The multiple enhancement-mode FET elements QE 1 , QE 2 , QEX may include compound semiconductor material, such as Gallium Arsenide, Indium Phosphide, Gallium Nitride, various combinations of elements from columns III and V of the periodic table of the elements, or any combination thereof.

FIG. 8 is similar to FIG. 7 and shows a series resistive element RS coupled between the drain of the Xth enhancement-mode FET element QEX and the first terminal FT, according to a fourth embodiment of the ESD clamp circuit 10 . By limiting the current, the drain-to-source voltage may be held within the maximum ON state drain-to-source voltage; however, adding resistance may reduce the effectiveness of the ESD clamp circuit 10 to protect from ESD events. Therefore, the value of the series resistive element RS may be chosen to balance the ruggedness of the ESD clamp circuit 10 and the ruggedness of the ESD protected circuit 12 .

FIG. 9 shows a multi-gate enhancement-mode FET element QME 2 , according to a fifth embodiment of the ESD clamp circuit 10 . Functionally, the multi-gate enhancement-mode FET element QME 2 may operate in a similar manner, and have the same benefits, as the combination of the multiple enhancement-mode FET elements QE 1 , QE 2 , QEX illustrated in FIG. 7 . The multi-gate enhancement-mode FET element QME 2 may be constructed with only one source and one drain metal contact.

Elimination of the metal interconnections between adjacent gates reduces the size of the multi-gate enhancement-mode FET element QME 2 when compared with the overall size of the multiple enhancement-mode FET elements QE 1 , QE 2 , QEX illustrated in FIG. 7 . The size of the multi-gate enhancement-mode FET element QME 2 may approach the size of only one or two of the multiple enhancement-mode FET elements QE 1 , QE 2 , QEX. Reducing the overall size of the FET circuitry may reduce parasitic capacitances and improve linearity of the ESD clamp circuit 10 . The multi-gate enhancement-mode FET element QME 2 may be a JFET element, a pHEMT element, or both. The multi-gate enhancement-mode FET element QME 2 may include compound semiconductor material, such as Gallium Arsenide, Indium Phosphide, Gallium Nitride, various combinations of elements from columns III and V of the periodic table of the elements, or any combination thereof.

FIG. 10 is similar to FIG. 9 and shows a series resistive element RS coupled between the drain of the multi-gate enhancement-mode FET element QME 2 and the first terminal FT, according to a sixth embodiment of the ESD clamp circuit 10 . By limiting the current, the drain-to-source voltage may be held within the maximum ON state drain-to-source voltage; however, adding resistance may reduce the effectiveness of the ESD clamp circuit 10 to protect from ESD events. Therefore, the value of the series resistive element RS may be chosen to balance the ruggedness of the ESD clamp circuit 10 and the ruggedness of the ESD protected circuit 12 .

Normally, the first terminal FT may have a positive voltage with respect to the voltage at the second terminal ST, but the first resistive element R 1 may hold the gate-to-source voltage at about zero volts, which holds the enhancement-mode FET element QE 1 in the OFF state. However, an ESD event producing a positive voltage at the first terminal FT with respect to the voltage at the second terminal ST in excess of an ESD trigger voltage will couple a voltage through the drain to the gate of the enhancement-mode FET element QE 1 to transition the enhancement-mode FET element QE 1 into its ON state, thereby transitioning the ESD clamp circuit 10 into its clamping state.

In an ESD event producing a negative voltage at the first terminal FT with respect to the voltage at the second terminal ST, the source of the enhancement-mode FET element QE 1 becomes more positive than its drain; therefore, the source and the drain effectively reverse roles with the drain functioning as a source and the source functioning as a drain. In such a situation, the first resistive element R 1 will directly apply a positive voltage to the gate, thereby transitioning the enhancement-mode FET element QE 1 into its ON state at a fairly low ESD trigger voltage.

The embodiments of the present invention illustrated in FIGS. 5 through 10 utilize enhancement-mode FET elements; however, those skilled in the art will recognize that the concepts demonstrated could be applied to circuits using normally-off FET elements and are within the scope of the present invention. Additionally, the embodiments of the present invention illustrated in FIGS. 5 through 10 function with the first terminal FT normally operating with a positive voltage with respect to the voltage at the second terminal ST; however, those skilled in the art will recognize that the concepts demonstrated could be applied to circuits that function with the first terminal FT normally operating with a negative voltage with respect to the voltage at the second terminal ST and are within the scope of the present invention.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.