Integrated circuit device and audio system

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-174413, filed on Jul. 2, 2007, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to an integrated circuit device and an audio system.

2. Background Art

In many cases, an audio system is provided with a muting circuit for muting an audio signal, and capable of switching between a sound output state and a mute state. It is known that a rasping sound referred to as “pop sound” is induced in such an audio system, when switching between the sound output state and the mute state. To reduce this pop sound, such an audio system is often provided with a time constant circuit for slowing the switching between the sound output state and the mute state.

The time constant circuit is generally configured with a resistor R and a capacitor C. A time constant around 10 to 100 msec is considered necessary to reduce the pop sound. However, it is difficult to achieve such a time constant with an IC (integrated circuit). Therefore, in the audio system, though the muting circuit is generally realized with the IC, the time constant circuit is provided out of the IC. In this case, the time constant circuit is connected to a time constant control terminal of the IC.

In recent years, attention has been attracted to multi-CH (channel) independent muting. For example, there exists such a demand that only a specific CH should be muted among six CHs of an audio system. In such a case, time constant circuits and time constant control terminals as many as CHs are required. However, as described above, since a time constant circuit is realized with elements out of an IC, it is highly costly to provide the time constant circuit. Therefore, it is disadvantageous in terms of cost to provide time constant circuits as many as CHs. Therefore, an audio system is proposed in which a single time constant circuit and a single time constant control terminal are associated with plural CHs (JP-A 2005-295011 (KOKAI) for example).

Description will now be made to an example of the audio system in which a single time constant circuit and a single time constant control terminal are associated with plural CHs.

Such an audio system includes, for example, sound output amplifiers and mute amplifiers, and a muting circuit of the audio system outputs mute control currents for controlling the sound output amplifiers and mute control currents for controlling the mute amplifiers, to mute an audio signal. The muting circuit outputs mute control currents for a first sound output amplifier and a first mute amplifier for muting a first CH, and outputs mute control currents for a second sound output amplifier and a second mute amplifier for muting a second CH. The muting circuit is connected to the time constant control terminal and the time constant circuit, both of which are common to these CHs.

An exemplary configuration of the muting circuit will be described. The muting circuit includes plural mute control current generating circuits connected to the time constant control terminal, a charging and discharging circuit configured to charge and discharge the time constant control terminal, and a control circuit configured to control the plural mute control current generating circuits and the charging and discharging circuit. Each of the mute control current generating circuits includes a V-I (voltage to current) converting circuit configured to compare a voltage of the time constant control terminal with a intermediate voltage, and generate a current I A corresponding to the voltage of the time constant control terminal and a current I B corresponding to the intermediate voltage, and a mute control current selecting and combining circuit configured to selectively combine the current I A and the current I B to generate a current I out . In a subsequent stage of each of the mute control current generating circuits, there are provided a resistor for converting the current I out to a voltage V out , and a V-I (voltage to current) converting circuit for generating mute control currents I out-A and I out-B by using the voltage V out (the V-I converting circuit is also referred to as a Gm amplifier, and hereinafter, may be expressed as a subsequent V-I converting circuit). The mute control current generating circuits are provided as many as the CHs of the audio system.

Then, an example of operations of the muting circuit will be described. Under the control by the control circuit, the charging and discharging circuit starts charging the time constant control terminal. The time constant control terminal is continued to be charged until the voltage on the time constant control terminal is changed from a first reference voltage to a second reference voltage. Since the time constant control terminal is connected to the time constant circuit, the time constant control terminal is slowly charged. It is assumed that a period for charging the time constant control terminal is t 1 . The V-I converting circuit needs to switch between a value of I A and a value of I B during t 1 , and is designed so as to carry out such a switching. Therefore, assuming that this switching period is t 2 , a relation between t 1 and t 2 becomes t 1 >t 2 . The subsequent V-I converting circuit needs to switch between a value of I out-A and a value of I out-B during t 2 , and is designed so as to carry out such a switching. Therefore, assuming that this switching period is t 3 , a relation between t 2 and t 3 becomes t 2 >t 3 .

The period t 3 corresponds to a time required for switching between the sound output state and the mute state. Therefore, a shorter period t 3 causes rapid switching between the sound output state and the mute state, so that an effect on the pop sound reduction is reduced. Accordingly, it is desirable that the period t 3 is as long as possible. However, since there exists such a restriction that a relation between t 1 , t 2 , and t 3 is t 1 >t 2 >t 3 , it is difficult to extend the period t 3 . Due to this restriction, it is necessary to extend the charging period t 1 in order to extend the period t 3 . In order to extend the charging period t 1 , it is necessary to make larger a time constant of the time constant circuit by means of a large capacity of condenser or the like. However, this results in the increased cost of the time constant circuit. As described here, it is difficult to sufficiently reduce the pop sound in the above muting circuit.

Further, the above audio system requires the mute control current I out-A for the sound output amplifier, and the mute control current I out-B for the mute amplifier. Therefore, the muting circuit requires the subsequent V-I converting circuit for generating the mute control currents I out-A and I out-B from the current I out (the voltage V out ). Therefore, the muting circuit would suffer from a problem of an increased IC chip area due to including the subsequent V-I converting circuit.

An aspect of the present invention is, for example, an n-channel integrated circuit device (n is an integer of 1 or greater) for muting an audio signal, the device including a control circuit configured to generate a control signal for controlling to switch between a sound output state and a mute state, and a delayed control signal obtained by delaying the control signal, a charging and discharging circuit configured to charge or discharge a time constant control terminal according to the control signal, to change a voltage on the time constant control terminal from a first reference voltage to a second reference voltage, and to discharge or charge the time constant control terminal according to the delayed control signal, to change the voltage on the time constant control terminal from the second reference voltage to the first reference voltage, an N-th voltage-to-current converting circuit (N is an integer from 1 to n) configured to compare the voltage on the time constant control terminal with an intermediate voltage which is between the first reference voltage and the second reference voltage, and generate a (2N−1)-th current corresponding to the voltage on the time constant control terminal and a (2N)-th current corresponding to the intermediate voltage, the N-th voltage-to-current converting circuit being configured to switch between a value of the (2N−1)-th current and a value of the (2N)-th current within a period for charging or discharging the time constant control terminal, a (2N−1)-th mirror circuit configured to copy the (2N−1)-th current to generate (4N−3)-th and (4N−2)-th intermediate currents, a (2N)-th mirror circuit configured to copy the (2N)-th current to generate (4N−1)-th and (4N)-th intermediate currents, a (2N−1)-th selecting and combining circuit configured to cut off or select the (4N−3)-th intermediate current and cut off or select the (4N−1)-th intermediate current, according to the control signal and the delayed control signal, to combine a (2N−1)-th mute control current, and a (2N)-th selecting and combining circuit configured to cut off or select the (4N−2)-th intermediate current and cut off or select the (4N)-th intermediate current, according to the control signal and the delayed control signal, to combine a (2N)-th mute control current.

Another aspect of the present invention is, for example, an integrated circuit device for muting an audio signal, the device including a control circuit configured to generate a control signal for controlling to switch between a sound output state and a mute state, and a delayed control signal obtained by delaying the control signal, a charging and discharging circuit configured to charge or discharge a time constant control terminal according to the control signal, to change a voltage on the time constant control terminal from a first reference voltage to a second reference voltage, and to discharge or charge the time constant control terminal according to the delayed control signal, to change the voltage on the time constant control terminal from the second reference voltage to the first reference voltage, an voltage-to-current converting circuit configured to compare the voltage on the time constant control terminal with an intermediate voltage which is between the first reference voltage and the second reference voltage, and generate a first current corresponding to the voltage on the time constant control terminal and a second current corresponding to the intermediate voltage, the voltage-to-current converting circuit being configured to switch between a value of the first current and a value of the second current within a period for charging or discharging the time constant control terminal, a first mirror circuit configured to copy the first current to generate first and second intermediate currents, a second mirror circuit configured to copy the second current to generate third and fourth intermediate currents, a first selecting and combining circuit configured to cut off or select the first intermediate current and cut off or select the third intermediate current, according to the control signal and the delayed control signal, to combine a first mute control current, and a second selecting and combining circuit configured to cut off or select the second intermediate current and cut off or select the fourth intermediate current, according to the control signal and the delayed control signal, to combine a second mute control current.

Another aspect of the present invention is, for example, an audio system including an n-channel integrated circuit device (n is an integer of 1 or greater) for muting an audio signal, the device including a control circuit configured to generate a control signal for controlling to switch between a sound output state and a mute state, and a delayed control signal obtained by delaying the control signal, a charging and discharging circuit configured to charge or discharge a time constant control terminal according to the control signal, to change a voltage on the time constant control terminal from a first reference voltage to a second reference voltage, and to discharge or charge the time constant control terminal according to the delayed control signal, to change the voltage on the time constant control terminal from the second reference voltage to the first reference voltage, an N-th voltage-to-current converting circuit (N is an integer from 1 to n) configured to compare the voltage on the time constant control terminal with an intermediate voltage which is between the first reference voltage and the second reference voltage, and generate a (2N−1)-th current corresponding to the voltage on the time constant control terminal and a (2N)-th current corresponding to the intermediate voltage, the N-th voltage-to-current converting circuit being configured to switch between a value of the (2N−1)-th current and a value of the (2N)-th current within a period for charging or discharging the time constant control terminal, a (2N−1)-th mirror circuit configured to copy the (2N−1)-th current to generate (4N−3)-th and (4N−2)-th intermediate currents, a (2N)-th mirror circuit configured to copy the (2N)-th current to generate (4N−1)-th and (4N)-th intermediate currents, a (2N−1)-th selecting and combining circuit configured to cut off or select the (4N−3)-th intermediate current and cut off or select the (4N−1)-th intermediate current, according to the control signal and the delayed control signal, to combine a (2N−1)-th mute control current, and a (2N)-th selecting and combining circuit configured to cut off or select the (4N−2)-th intermediate current and cut off or select the (4N)-th intermediate current, according to the control signal and the delayed control signal, to combine a (2N)-th mute control current, an N-th sound output amplifier configured to be controlled by the (2N−1)-th mute control current, an N-th mute amplifier configured to be controlled by the (2N)-th mute control current, and an N-th speaker connected to the N-th sound output amplifier and the N-th mute amplifier.

FIG. 1 shows a system configuration of an audio system according to an embodiment;

FIG. 2 shows a system configuration of an audio system according to a modified embodiment;

FIG. 3 is a block diagram of an integrated circuit device according to the embodiment;

FIG. 4 is a block diagram of an integrated circuit device according to the modified embodiment;

FIG. 5A is a waveform chart for describing an example of operations of the integrated circuit device in FIG. 3 ;

FIG. 5B is a waveform chart in which an area X of the waveform chart in FIG. 5A is expanded;

FIG. 6 is a block diagram of an integrated circuit device according to a comparative example;

FIG. 7A is a waveform chart for describing an example of operations of the integrated circuit device in FIG. 6 ;

FIG. 7B is a waveform chart in which an area X of the waveform chart in FIG. 7A is expanded;

FIG. 8A shows a first example of a circuit configuration of the integrated circuit device;

FIG. 8B shows a variation of a circuit configuration of a first V-I converting circuit;

FIG. 8C shows a variation of the circuit configuration of FIG. 8A ;

FIG. 8D shows another variation of the circuit configuration of FIG. 8A ;

FIG. 8E shows another variation of the circuit configuration of FIG. 8A ;

FIG. 9A shows a second example of a circuit configuration of the integrated circuit device;

FIG. 9B shows a variation of a circuit configuration of the first V-I converting circuit;

FIG. 9C shows a variation of the circuit configuration of FIG. 9A ;

FIG. 9D shows another variation of the circuit configuration of FIG. 9A ; and

FIG. 9E shows another variation of the circuit configuration of FIG. 9A .

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a system diagram of an audio system 101 according to an embodiment. The audio system 101 of FIG. 1 includes an integrated circuit device 111 according to the present embodiment, a first power amplifier 112 1 , a second power amplifier 112 2 , a first speaker 113 1 , and a second speaker 113 2 . The first power amplifier 112 1 includes a first sound output amplifier 121 A1 , and a first mute amplifier 121 B1 . The second power amplifier 112 2 includes a second sound output amplifier 121 A2 , and a second mute amplifier 121 B2 .

The integrated circuit device 111 includes a muting circuit for muting an audio signal. The integrated circuit device 111 outputs mute control currents I out-A1 and I out-B1 as mute control currents for a first CH. The mute control currents I out-A1 and I out-B1 are supplied for controlling the first sound output amplifier 121 A1 and the first mute amplifier 121 B1 respectively. The integrated circuit device 111 outputs mute control currents I out-A2 and I out-B2 as mute control signals for a second CH. The mute control currents I out-A2 and I out-B2 are supplied for controlling the second sound output amplifier 121 A2 and the second mute amplifier 121 B2 respectively.

The first power amplifier 112 1 and the first speaker 113 1 are provided as a power amplifier and a speaker for the first CH. The first sound output amplifier 121 A1 is provided for causing the first CH to be in the sound output state, and is controlled by the mute control current I out-A1 . As shown in FIG. 1 , the audio signal is inputted to an input of the first sound output amplifier 121 A1 . The first mute amplifier 121 B1 is provided for causing the first CH to be in the mute state, and is controlled by the mute control current I out-B1 . An input of the first mute amplifier 121 B1 is grounded as shown in FIG. 1 . The first speaker 113 1 is connected to the first sound output amplifier 121 A1 and the first mute amplifier 121 B1 . The audio system 101 of FIG. 1 may be provided with one speaker, or two or more speakers, as a speaker for the first CH, that is, the first speaker 113 1 .

The circuit configuration regarding the first power amplifier 112 1 and the first speaker 113 1 will be described.

The first sound output amplifier 121 A1 includes an input terminal α A1 , an input terminal β A1 , and an output terminal γ A1 . In this embodiment, while the α A1 is a plus terminal and the β A1 is a minus terminal, the α A1 may be a minus terminal and the β B1 may be a plus terminal. The first mute amplifier 121 B1 includes an input terminal α B1 , an input terminal β B1 , and an output terminal γ B1 . In this embodiment, while the α B1 is a plus terminal and the β B1 is a minus terminal, the α B1 may be a minus terminal and the β B1 may be a plus terminal.

In this embodiment, the input terminal α A1 of the first sound output amplifier 121 A1 is connected to an audio signal line L. The input terminal α B1 of the first mute amplifier 121 B1 is connected to the ground. The output terminal γ A1 of the first sound output amplifier 121 A1 and the output terminal γ B1 of the first mute amplifier 121 B1 are connected to the first speaker 113 1 . The input terminal β A1 of the first sound output amplifier 121 A1 and the input terminal β B1 of the first mute amplifier 121 B1 are connected to the output terminal γ A1 of the first sound output amplifier 121 A1 and the output terminal γ B1 of the first mute amplifier 121 B1 through an R A1 (a first resistor), and are connected to the ground through an R B1 (a second register). The first sound output amplifier 121 A1 , the first mute amplifier 121 B1 , and the R A1 are mutually connected in parallel. The first resistor is an example of a first feedback circuit. The first feedback circuit in this embodiment is a resistor feedback, but may be a full feedback. The first feedback circuit may be configured with a component other than the register.

The second power amplifier 112 2 and the second speaker 113 2 are provided as a power amplifier and a speaker for the second CH. The second sound output amplifier 121 A2 is provided for causing the second CH to be in the sound output state, and is controlled by the mute control current I out-A2 . As shown in FIG. 1 , the audio signal is inputted to an input of the second sound output amplifier 121 A2 . The second mute amplifier 121 B2 is provided for causing the second CH to be in the mute state, and is controlled by the mute control current I out-B2 . An input of the second mute amplifier 121 B2 is grounded as shown in FIG. 1 . The second speaker 113 2 is connected to the second sound output amplifier 121 A2 and the second mute amplifier 121 B2 . The audio system 101 of FIG. 1 may be provided with one speaker, or two or more speakers, as a speaker for the second CH, that is, the second speaker 113 2 .

The circuit configuration regarding the second power amplifier 112 2 and the second speaker 113 2 will be described.

The second sound output amplifier 121 A2 includes an input terminal α A2 , an input terminal β A2 , and an output terminal γ A2 . In this embodiment, while the α A2 is the plus terminal and the β A2 is the minus terminal, the α A2 may be a minus terminal and the β A2 may be a plus terminal. The second mute amplifier 121 B2 includes an input terminal α B2 , an input terminal β B2 , and an output terminal γ B2 . In this embodiment, while the α B2 is the plus terminal and the β B2 is the minus terminal, the α B2 may be a minus terminal and the β B2 may be a plus terminal.

In this embodiment, the input terminal α A2 of the second sound output amplifier 121 A2 is connected to the audio signal line L. The input terminal α B2 of the second mute amplifier 121 B2 is connected to the ground. The output terminal γ A2 of the second sound output amplifier 121 A2 and the output terminal γ B2 of the second mute amplifier 121 B2 are connected to the second speaker 113 2 . The input terminal β A2 of the second sound output amplifier 121 A2 and the input terminal β B2 of the second mute amplifier 121 B2 are connected to the output terminal γ A2 of the second sound output amplifier 121 A2 and the output terminal γ B2 of the second mute amplifier 121 B2 through an R A2 (a third resistor), and are connected to the ground through an R B2 (a fourth register). The second sound output amplifier 121 A2 , the second mute amplifier 121 B2 , and R A2 are mutually connected in parallel. The third resistor is an example of a second feedback circuit. The second feedback circuit in this embodiment is a resistor feedback, but may be a full feedback. The second feedback circuit may be configured with a component other than the register.

The audio system 101 in this embodiment may have two channels (CHs) as illustrated in FIG. 1 , or may have three or more channels as illustrated in FIG. 2 . It is assumed here that a structure and operations of each channel of FIG. 2 are the same as those of each channel of FIG. 1 . Hereinafter, the integrated circuit device 111 included in the audio system 101 of FIG. 1 will be described. However, the following description can also be applied to the integrated circuit device 111 included in the audio system 101 of FIG. 2 . It is assumed that “N” in FIG. 2 is an integer of 3 or greater. A power amplifier 112 N is an N-th power amplifier, a speaker 113 N is an N-th speaker, a sound output amplifier 121 AN is an N-th sound output amplifier, and a mute amplifier 121 BN is an N-th mute amplifier. Further, an R AN is a (2N−1)-th resistor, an R BN is a (2N)-th resistor. The (2N−1)-th resistor is an example of an N-th feedback circuit.

FIG. 3 is a block diagram of the integrated circuit device 111 according to this embodiment. The integrated circuit device 111 of FIG. 3 corresponds to the integrated circuit device 111 of FIG. 1 . The integrated circuit device 111 of FIG. 3 includes a control circuit 201 , a charging and discharging circuit 202 , a first mute control current generating circuit 203 1 , and a second mute control current generating circuit 203 2 . Hereinafter, the first and second mute control current generating circuits 203 1 and 203 2 are referred to as first and second control current generating circuits 203 1 and 203 2 respectively. The integrated circuit device 111 of FIG. 3 further includes a time constant control terminal 141 connected to a time constant circuit 131 . The time constant circuit 131 and the time constant control terminal 141 are common to the first and second CHs.

The control circuit 201 is configured to control the charging and discharging circuit 202 , the first control current generating circuit 203 1 , and the second control current generating circuit 203 2 . The control circuit 201 generates a first mute signal (control signal) M 1 and a first delayed mute signal (delayed control signal) DM 1 as signals for the first CH, and generates a second mute signal (control signal) M 2 and a second delayed mute signal (delayed control signal) DM 2 as signals for the second CH. The first and second mute signals M 1 and M 2 are supplied for controlling the switching between the sound output state and the mute state for the first and second CHs respectively. The first and second delayed mute signals DM 1 and DM 2 are delayed signals of the first and second mute signals M 1 and M 2 .

The charging and discharging circuit 202 is configured to charge and discharge the time constant control terminal 141 . The charging and discharging circuit 202 charges the time constant control terminal 141 according to the first or second mute signal M 1 or M 2 , to change a voltage on the time constant control terminal 141 from a first reference voltage V 1 to a second reference voltage V 2 . The charging and discharging circuit 202 further discharges the time constant control terminal 141 according to the first or second delayed mute signals DM 1 and DM 2 , to change the voltage on the time constant control terminal 141 from the second reference voltage V 2 to the first reference voltage V 1 . In this embodiment, it is assumed that V 1 <V 2 , the time constant control terminal 141 is charged in response to M 1 or M 2 , and the time constant control terminal 141 is discharged in response to DM 1 or DM 2 . However, it may alternatively be assumed that V 1 >V 2 , the time constant control terminal 141 may be discharged in response to M 1 or M 2 , and the time constant control terminal 141 may be charged in response to DM 1 or DM 2 .

The first and second control current generating circuits 203 1 and 203 2 are connected to the time constant control terminal 141 . The first control current generating circuit 203 1 includes a first V-I (voltage to current) converting circuit 211 1 , first and second current mirror circuits 212 A1 and 212 B1 , and first and second mute control current selecting and combining circuits 213 A1 and 213 B1 . The second control current generating circuit 203 2 includes a second V-I (voltage to current) converting circuit 211 2 , third and fourth current mirror circuits 212 A2 and 212 B2 , and third and fourth mute control current selecting and combining circuits 213 A2 and 213 B2 . Hereinafter, the first to fourth current mirror circuits are referred to as first to fourth mirror circuits respectively, and the first to fourth mute control current selecting and combining circuits are referred to as first to fourth selecting and combining circuits respectively. It is assumed here that a configuration and operations of the second control current generating circuit 203 2 are the same as those of the first control current generating circuit 203 1 . Hereinafter, while each block of the first control current generating circuit 203 1 will be described, the following description can also be applied to each block of the second control current generating circuit 203 2 .

The first V-I converting circuit 211 1 is configured to compare a voltage V A of the time constant control terminal 141 with an intermediate voltage V B1 which is between the first reference voltage V 1 and the second reference voltage V 2 , and generate a first current I A1 corresponding to the voltage V A on the time constant control terminal 141 and a second current I B1 corresponding to the intermediate voltage V B1 . Further, the first V-I converting circuit 211 1 is designed so as to switch between a value of the first current I A1 and a value of the second current I B1 within a period for charging the time constant control terminal 141 . Further, the first V-I converting circuit 211 1 is designed so as to, after starting discharging the time constant control terminal 141 , return back the value of the first current I A1 and the value of the second current I B1 to values before starting charging the time constant control terminal 141 . When it is assumed that a relation between V 1 and V 2 is not V 1 <V 2 but V 1 >V 2 , the above “within a period for charging”, “after starting discharging”, and “before starting charging” are replaced by “within a period for discharging”, “after starting charging”, and “before starting discharging” respectively. When the description of the present paragraph is applied to the second V-I converting circuit 211 2 , the intermediate voltage V B1 will be renamed to an intermediate voltage V B2 , and the first and second currents I A1 and I B1 will be renamed to a third and fourth currents I A2 and I B2 respectively. The intermediate voltage V B2 may be the same value as the intermediate voltage V B1 , or may be a different value from the intermediate voltage V B1 .

The first mirror circuit 212 A1 is configured to copy the first current I A1 , to generate first and second intermediate currents I AA1 and I AB1 . Since I AA1 and I AB1 are currents generated by copying I A1 , there is a relation of I A1 =I AA1 =I AB1 . The second mirror circuit 212 B1 is configured to copy the second current I B1 , to generate third and fourth intermediate currents I BA1 and I BB1 . Since I BA1 and I BB1 are currents generated by copying the I B1 , there is a relation of I B1 =I BA1 =I BB1 . When the description of the present paragraph is applied to the third and fourth mirror circuits 212 A2 and 212 B2 , the first and second currents I A1 and I B1 will be renamed to the third and fourth currents I A2 and I B2 respectively, and the first to fourth intermediate currents I AA1 to I BB1 will be renamed to fifth to eighth intermediate currents I AA2 to I BB2 respectively.

The first selecting and combining circuit 213 A1 is configured to selectively combine the first intermediate current I AA1 and the third intermediate current I BA1 , to generate a first mute control current I out-A1 . As exemplified below, the first selecting and combining circuit 213 A1 cuts off or selects the first intermediate current I AA1 and cuts off or selects the third intermediate current I BA1 , according to the first mute signal M 1 and the first delayed mute signal DM 1 , to combine the first mute control current I out-A1 . The second selecting and combining circuits 213 B1 is configured to selectively combine the second intermediate current I AB1 and the fourth intermediate current I BB1 , to generate a second mute control current I out-B1 . As exemplified below, the second selecting and combining circuits 213 B1 cuts off or selects the second intermediate current I AB1 and cuts off or selects the fourth intermediate current I BB1 , according to the first mute signal M 1 and the first delayed mute signal DM 1 , to combine the second mute control current I out-B1 .

The first selecting and combining circuit 213 A1 operates as follows.

When the first mute signal M 1 and the first delayed mute signal DM 1 are low levels, the first selecting and combining circuit 213 A1 cuts off the first and third intermediate currents I AA1 and I BA1 .

When the first mute signal M 1 and the first delayed mute signal DM 1 are a high level and a low level respectively, the first selecting and combining circuit 213 A1 selects and cuts off the first and third intermediate currents I AA1 and I BA1 respectively.

When the first mute signal M 1 and the first delayed mute signal DM 1 are high levels, the first selecting and combining circuit 213 A1 selects the first and third intermediate currents I AA1 and I BA1 .

When the first mute signal M 1 and the first delayed mute signal DM 1 are a low level and a high level respectively, the first selecting and combining circuit 213 A1 cuts off and selects the first and third intermediate currents I AA1 and I BA1 respectively.

Subsequently, the first selecting and combining circuit 213 A1 combines the first mute control current I out-A1 using the selected intermediate current. When I AA1 or I BA1 is selected, I AA1 or I BA1 itself becomes I out-A1 . When I AA1 and I BA1 are selected, a current obtained by adding I AA1 and I BA1 becomes I out-A1 . When I AA1 and I BA1 are cut off, I out-A1 becomes “0”. As described above, the first mute control current I out-A1 is generated from the first and second currents I A1 and I B1 through the first and third intermediate currents I AA1 and I BA1 .

The second selecting and combining circuits 213 B1 operates as follows.

When the first mute signal M 1 and the first delayed mute signal DM 1 are low levels, the second selecting and combining circuit 213 B1 selects the second and fourth intermediate currents I AB1 and I BB1 .

When the first mute signal M 1 and the first delayed mute signal DM 1 are a high level and a low level respectively, the second selecting and combining circuit 213 B1 cuts off and selects the second and fourth intermediate currents I AB1 and I BB1 respectively.

When the first mute signal M 1 and the first delayed mute signal DM 1 are high levels, the second selecting and combining circuit 213 B1 cuts off the second and fourth intermediate currents I AB1 and I BB1 .

When the first mute signal M 1 and the first delayed mute signal DM 1 are a low level and a high level respectively, the second selecting and combining circuit 213 B1 selects and cuts off the second and fourth intermediate currents I AB1 and I BB1 respectively.

Subsequently, the second selecting and combining circuit 213 B1 combines the second mute control current I out-B1 using the selected intermediate current. When I AB1 or I BB1 is selected, I AB1 or I BB1 itself becomes I out-B1 . When I AB1 and I BB1 are selected, a current obtained by adding I AB1 and I BB1 becomes I out-B1 . When I AB1 and I BB1 are cut off, I out-B1 becomes “0”. As described above, the second mute control current I out-B1 is generated from the first and second currents I A1 and I B1 through the second and fourth intermediate currents I AB1 and I BB1 .

From the above description, it can be understood that, when the first intermediate current I AA1 is selected, the second intermediate current I AB1 is cut off, and when the first intermediate current I AA1 is cut off, the second intermediate current I AB1 is selected. It can be understood likely that, when the third intermediate current I BA1 is selected, the fourth intermediate current I BB1 is cut off, and when the third intermediate current I BA1 is cut off, the fourth intermediate current I BB1 is selected. Therefore, the first mute control current I out-A1 and the second mute control current I out-B1 have the same amplitude and different polarities.

When the above description for the first and second selecting and combining circuits 213 A1 and 213 B1 is applied to the third and fourth selecting and combining circuits 213 A2 and 213 B2 , the first mute signal M 1 will be renamed to the second mute signal M 2 , the first delayed mute signal DM 1 will be renamed to the second delayed mute signal DM 2 , and the first to fourth intermediate currents I AA1 and I BB1 will be renamed to the fifth to eighth intermediate currents I AA2 to I BB2 respectively.

The integrated circuit device 111 in this embodiment may be configured for an audio system 101 having two channels as illustrated in FIG. 3 , or may be configured for an audio system 101 having three or more channels as illustrated in FIG. 4 . It is assumed here that a structure and operations of each channel of FIG. 4 are the same as those of each channel of FIG. 3 . Hereinafter, while the structure and the operations of the integrated circuit device 111 of FIG. 3 will be described, the following description can also be applied to the integrated circuit device 111 of FIG. 4 . It is assumed that “N” in FIG. 4 is an integer of 3 or greater. Names of each block and each signal of FIG. 4 are shown in FIG. 4 .

FIG. 5A is a waveform chart for describing an example of operations of the integrated circuit device 111 in FIG. 3 . FIG. 5B is a waveform chart in which an area X of the waveform chart in FIG. 5A is expanded.

The switching from the mute state to the sound output state will be described. When the first CH is in the mute state, both of M 1 and DM 1 are “L” levels.

First, the control circuit 201 switches M 1 from “L” level to “H” level. In response to the switching of M 1 , the charging and discharging circuit 202 starts charging the time constant control terminal 141 . The time constant control terminal 141 is continued to be charged until the voltage V A on the time constant control terminal 141 is changed from the first reference voltage V 1 to the second reference voltage V 2 . Since the time constant control terminal 141 is connected to the time constant circuit 131 , the voltage V A on the time constant control terminal 141 is slowly increased.

Before the voltage V A is changed from V 1 to V 2 , the first V-I converting circuit 211 1 switches between a value of I A1 and a value of I B1 . Thereby, as illustrated in FIGS. 5A and 5B , a value of I AA1 and a value of I BA1 are switched, and a value of I AB1 and a value of I BB1 are switched. When the voltage V A on the time constant control terminal 141 becomes equal to the intermediate voltage V B1 , a relation between I A1 and I B1 becomes I A1 =I B1 (I AA1 =I BA1 , I AB1 =I BB1 ).

On the other hand, in response to the switching of M 1 , the first selecting and combining circuit 213 A1 operates to select and cut off I AA1 and I BA1 respectively, and the second selecting and combining circuit 213 B1 operates to cut off and select I AB1 and I BB1 respectively. Thereby, as illustrated in FIGS. 5A and 5B , I out-A1 becomes I AA1 , and I out-B1 becomes I BB1 .

Next, the control circuit 201 switches DM 1 from “L” level to “H” level, triggered by a fact that the VA has reached V 2 . As illustrated in FIG. 5B , it is assumed that a period from the switching of M 1 to the switching of DM 1 is t 1 . As described later, the time t 1 corresponds to a period from the time when the time constant control terminal 141 is started to be charged to the time when the time constant control terminal 141 is started to be discharged, that is, corresponds to a period for charging the time constant control terminal 141 .

As described above, the first V-I converting circuit 211 1 switches between the value of I A1 and the value of I B1 , before the V A is changed from V 1 to V 2 . That is, the first V-I converting circuit 211 1 switches between the value of I A1 and the value of I B1 within the time t 1 . As described here, the first V-I converting circuit 211 1 needs to switch between the value of I A1 and the value of I B1 within the time t 1 , and is designed so as to carry out such a switching. Therefore, assuming that this switching period is t 2 , a relation between t 1 and t 2 becomes t 1 >t 2 . Therefore, DM 1 is switched after the completion of switching between the value of I A1 and the value of I B1 .

Furthermore, as described above, in response to the switching of M 1 , the first selecting and combining circuit 213 A1 operates to select and cut off I AA1 and I BA1 respectively, and the second selecting and combining circuit 213 B1 operates to cut off and select I AB1 and I BB1 respectively. Therefore, assuming that a period for switching between a value of I out-A1 and a value of I out-B1 is t 3 ′, this switching time t 3 ′ also becomes t 2 (that is, t 3 ′=t 2 ) as illustrated in FIG. 5B .

Hereinafter, an operation after DM 1 is switched will be described.

In response to the switching of DM 1 , the charging and discharging circuit 202 starts discharging the time constant control terminal 141 . The time constant control terminal 141 is continued to be discharged until the voltage V A on the time constant control terminal 141 is changed from the second reference voltage V 2 to the first reference voltage V 1 . Since the time constant control terminal 141 is connected to the time constant circuit 131 , the voltage V A on the time constant control terminal 141 is slowly decreased.

On the other hand, in response to the switching of DM 1 , the first selecting and combining circuit 213 A1 operates to select both of I AA1 and I BA1 , and the second selecting and combining circuit 213 B1 operates to cut off both of I AB1 and I BB1 . Thereby, as illustrated in FIGS. 5A and 5B , I out-A1 becomes I AA1 +I BA1 , and I out-B1 becomes “0”.

As described above, the first CH is switched from the mute state to the sound output state. A period before the time t 2 corresponds to a period in the mute state, a period after the time t 2 corresponds to a period in the sound output state, and the time t 2 corresponds to a period for switching from the mute state to the sound output state. The above description can also be applied to the second CH.

The switching from the sound output state to the mute state will be described. When the first CH is in the sound output state, both of M 1 and DM 1 are “H” levels.

First, the control circuit 201 switches M 1 from “H” level to “L” level. In response to the switching of M 1 , the charging and discharging circuit 202 starts charging the time constant control terminal 141 . The time constant control terminal 141 is continued to be charged until the voltage V A on the time constant control terminal 141 is changed from the first reference voltage V 1 to the second reference voltage V 2 . Since the time constant control terminal 141 is connected to the time constant circuit 131 , the voltage V A on the time constant control terminal 141 is slowly increased.

Before the voltage V A is changed from V 1 to V 2 , the first V-I converting circuit 211 1 switches between the value of I A1 and the value of I B1 . Thereby, as illustrated in FIG. 5A , the value of I AA1 and the value of I BA1 are switched, and the value of I AB1 and the value of I BB1 are switched. When the voltage V A on the time constant control terminal 141 becomes equal to the intermediate voltage V B1 , a relation between I A1 and I B1 becomes I A1 =I B1 (I AA1 =I BA1 , I AB1 =I BB1 .

On the other hand, in response to the switching of M 1 , the first selecting and combining circuit 213 A1 operates to cut off and select I AA1 and I BA1 respectively, and the second selecting and combining circuit 213 B1 operates to select and cut off I AB1 and I BB1 respectively. Thereby, as illustrated in FIG. 5A , I out-A1 becomes I BA1 , and I out-B1 becomes I AB1 .

Next, the control circuit 201 switches DM 1 from “H” level to “L” level, triggered by a fact that the V A has reached V 2 . It is assumed that a period from the switching of M 1 to the switching of DM 1 is t 1 . The time t 1 corresponds to a period from the time when the time constant control terminal 141 is started to be charged to the time when the time constant control terminal 141 is started to be discharged, that is, corresponds to a period for charging the time constant control terminal 141 .

As described above, the first V-I converting circuit 211 1 switches between the value of I A1 and the value of I B1 , before the voltage V A is changed from V 1 to V 2 . That is, the first V-I converting circuit 211 1 switches between the value of I A1 and the value of I B1 within the time t 1 . As described here, the first V-I converting circuit 211 1 needs to switch between the value of I A1 and the value of I B1 within the time t 1 , and is designed so as to carry out such switching. Therefore, assuming that this switching period is t 2 , a relation between t 1 and t 2 becomes t 1 >t 2 . Therefore, DM 1 is switched after the completion of switching between the value of I A1 and the value of I B1 .

Furthermore, as described above, in response to the switching of M 1 , the first selecting and combining circuit 213 A1 operates to cut off and select I AA1 and I BA1 respectively, and the second selecting and combining circuit 213 B1 operates to select and cut off I AB1 and I BB1 respectively. Therefore, assuming that a period for switching between the value of I out-A1 and the value of I out-B1 is t 3 ′, this switching time t 3 ′ also becomes t 2 (that is, t 3 ′=t 2 ).

Hereinafter, an operation after DM 1 is switched will be described.

In response to the switching of DM 1 , the charging and discharging circuit 202 starts discharging the time constant control terminal 141 . The time constant control terminal 141 is continued to be discharged until the voltage V A on the time constant control terminal 141 is changed from the second reference voltage V 2 to the first reference voltage V 1 . Since the time constant control terminal 141 is connected to the time constant circuit 131 , the voltage V A on the time constant control terminal 141 is slowly decreased.

On the other hand, in response to the switching of DM 1 , the first selecting and combining circuit 213 A1 operates to cut off both of I AA1 and I BA1 , and the second selecting and combining circuit 213 B1 operates to select both of I AB1 and I BB1 . Thereby, as illustrated in FIG. 5A , I out-A1 becomes “0”, and I out-B1 becomes I AB1 +I BB1 .

As described above, the first CH is switched from the sound output state to the mute state. A period before the time t 2 corresponds to a period in the sound output state, a period after the time t 2 corresponds to a period in the mute state, and the time t 2 ″ corresponds to a period for switching from the sound output state to the mute state. The above description can also be applied to the second CH.

Here, the integrated circuit device 111 of a comparative example will be exemplified.

FIG. 6 is a block diagram of the integrated circuit device 111 of the comparative example. FIG. 7A is a waveform chart for describing an example of operations of the integrated circuit device 111 in FIG. 6 . FIG. 7B is a waveform chart in which an area X of the waveform chart in FIG. 7A is expanded.

The integrated circuit device 111 of FIG. 6 includes first and second selecting and combining circuits 213 1 and 213 2 , first and second resistors 301 1 and 301 2 , and first and second V-I converting circuits (Gm amplifiers) 302 1 and 302 2 , instead of the first to fourth mirror circuits 212 A1 to 212 B2 , and the first to fourth selecting and combining circuits 213 A1 to 213 B2 .

The first V-I converting circuit 211 1 of FIG. 6 generates the currents I A1 and I B1 , similar to the first V-I converting circuit 211 1 of FIG. 3 . The first selecting and combining circuit 213 1 of FIG. 6 selectively combines the current I A1 and the current I B1 to generate a current I out-1 . As illustrated in FIGS. 7A and B, a waveform of the current I out-1 in the comparative example is the same as that of the current I out-A1 in this embodiment. The first resistor 301 1 converts the current I out-1 to a voltage V out-1 . The first V-I converting circuit 302 1 generates the mute control currents I out-A1 and I out-B1 using the voltage V out-1

FIG. 7B illustrates the times t 1 , t 2 , and t 3 . The time t 1 is a period for charging the time constant control terminal 141 . The time constant control terminal 141 is charged by the charging and discharging circuit 202 . The time t 2 is a period for switching between the value of I A1 and the value of I B1 . The values of I A1 and I B1 are switched by the first V-I converting circuit 211 1 . Since it is necessary to switch between the values of I A1 and I B1 within the time t 1 , a relation between t 1 and t 2 becomes t 1 >t 2 . The time t 3 is a period for switching between the value of I out-A1 and the value of I out-B1 . The values of I out-A1 and I out-B1 are switched by the first V-I converting circuit 302 1 . Since it is necessary to switch between the values of I out-A1 and I out-B1 within the time t 2 , a relation between t 2 and t 3 becomes t 2 >t 3 . Therefore, the relation t 1 >t 2 >t 3 is true as a relation between t 1 , t 2 , and t 3 .

Here, the embodiment of FIG. 3 and the comparative example of FIG. 6 will be compared.

In the comparative example of FIG. 6 , time required for switching between the sound output state and the mute state is t 3 . In the comparative example, t 3 is restricted by the relation t 1 >t 2 >t 3 . On the other hand, in the embodiment of FIG. 3 , time required for switching between the sound output state and the mute state is t 2 . In the embodiment, t 2 is restricted by the relation t 1 >t 2 . It is noted that t 1 is a time required for charging, and t 2 is a time required for selecting and combining, in both cases.

It is desirable that a time required for switching between the sound output state and the mute state is as long as possible. This is because the shorter switching time causes rapid switching between the sound output state and the mute state, so that the effect on the pop sound reduction is decreased. From such a viewpoint, the embodiment of FIG. 3 may be superior to the comparative example of FIG. 6 . This is because the above restriction for the switching time of the embodiment of FIG. 3 is smaller than that of the comparative example of FIG. 6 , as described above.

As described above, in the embodiment of FIG. 3 , the mute control currents I out-A1 and I out-B1 whose polarities are different from each other are generated. Since the polarities of I out-A1 and I out-B1 are different from each other, such a feature is realized that the sound output state and the mute state of the first CH do not appear at the same time. This is also the same in the mute control currents I out-A2 and I out-B2 .

On the other hand, such a feature is also realized in the comparative example of FIG. 6 . However, in the comparative example of FIG. 6 , it is necessary to provide the integrated circuit device 111 with the first and second V-I converting circuits 302 1 and 302 2 , in order to realize such a feature. Therefore, in the comparative example of FIG. 6 , such V-I converting circuits 302 1 and 302 2 result in increasing an IC chip area. On the other hand, in the embodiment of FIG. 3 , it is not necessary to provide the integrated circuit device 111 with such a V-I converting circuit. Therefore, in the embodiment of FIG. 3 , it is possible to prevent the IC chip area from being increased, and it is possible to accelerate the pop sound to be reduced.

In this embodiment, regarding M 1 and DM 1 , while the low level and the high level are designated to be a first logical level and a second logical level respectively, the high level and the low level may be designated to be the first logical level and the second logical level respectively. This is the same for M 2 and DM 2 .

This embodiment can be applied not only to the audio system and the integrated circuit device having two or more channels, but also to an audio system and an integrated circuit device having one channel. In the audio system and the integrated circuit device having two or more channels, the time constant circuit 131 and the time constant control terminal 141 can advantageously be shared.

(First Example of Circuit Configuration)

FIG. 8A shows a first example of the circuit configuration of the integrated circuit device 111 in FIG. 3 . FIG. 8A shows the control circuit 201 , the charging and discharging circuit 202 , the first control current generating circuit 203 1 , and the second control current generating circuit 203 2 . FIG. 8A further shows the time constant circuit 131 and the time constant control terminal 141 .

While it is assumed here that the time constant circuit 131 is connected externally to the integrated circuit device 111 , the time constant circuit 131 may be incorporated in the integrated circuit device 111 in some cases. When the time constant circuit 131 is externally connected, it is configured, for example, with a resistor element, a capacitor, and the like. It is assumed here that a time constant of the time constant circuit 131 is 10 to 100 msec. While the charging and discharging circuit 202 is not operating, the time constant control terminal 141 is provided with a voltage which is not detected by the first and second control current generating circuits 203 1 and 203 2 .

FIG. 8A further illustrates a circuit configuration of the first control current generating circuit 203 1 . The first control current generating circuit 203 1 includes the first V-I converting circuit 211 1 , the first and second mirror circuits 212 A1 and 212 B1 , and the first and second selecting and combining circuits 213 A1 and 213 B1 .

The first V-I converting circuit 211 1 includes a first current source C 1 , a first transistor T 1 , and a second transistor T 2 . The transistor T 1 is connected to the current source C 1 , the transistor T 2 , and the time constant control terminal 141 , and outputs the current I A1 . The transistor T 2 is connected to the current source C 1 , the transistor T 1 , and a terminal of the intermediate voltage V B1 , and outputs the current I B1 . FIG. 8B shows a variation of the circuit configuration of the first V-I converting circuit 211 1 . In FIG. 8B , a first resistor element R 1 is connected between an emitter of the transistor T 1 and the current source C 1 . In FIG. 8B , a second resistor element R 2 is further connected between an emitter of the transistor T 2 and the current source C 1 .

The first mirror circuit 212 A1 includes a third transistor T 3 , a fourth transistor T 4 , and a fifth transistor T 5 . The transistor T 3 is connected to the transistor T 1 , and is provided with the current I A1 from the transistor T 1 . The transistor T 4 outputs the intermediate current I AA1 . The transistor T 5 outputs the intermediate current I AB1 . Third, fourth, and fifth resistor elements R 3 , R 4 , and R 5 are connected to the emitters of the transistors T 3 , T 4 , and T 5 respectively.

The second mirror circuit 212 B1 includes a sixth transistor T 6 , a seventh transistor T 7 , and an eighth transistor T 8 . The transistor T 6 is connected to the transistor T 2 , and is provided with the current I B1 from the transistor T 2 . The transistor T 7 outputs the intermediate current I BA1 . The transistor T 8 outputs the intermediate current I BB1 . Sixth, seventh, and eighth resistor elements R 6 , R 7 , and R 8 are connected to the emitters of the transistors T 6 , T 7 , and T 8 respectively.

The first selecting and combining circuit 213 A1 includes a first switch S 1 and a second switch S 2 . The switch S 1 is provided for selecting or cutting off the intermediate current I AA1 . The switch S 2 is provided for selecting or cutting off the intermediate current I BA1 . The switches S 1 and S 2 are controlled by the control circuit 201 .

The second selecting and combining circuit 213 B1 includes a third switch S 3 and a fourth switch S 4 . The switch S 3 is provided for selecting or cutting off the intermediate current I AB1 . The switch S 4 is provided for selecting or cutting off the intermediate current I BB1 . The switches S 3 and S 4 are controlled by the control circuit 201 .

Each of the first to eighth transistors T 1 to T 8 is a bipolar transistor. In this example, the first and second transistors T 1 and T 2 are NPN-type transistors, and the third to eighth transistors T 3 to T 8 are PNP-type transistors.

FIG. 8C shows a variation of the circuit configuration of FIG. 8A . In FIG. 8C , each of the first to eighth transistors T 1 to T 8 is a field-effect transistor. In FIG. 8C , the first and second transistors T 1 and T 2 are nMOS transistors, and the third to eighth transistors T 3 to T 8 are pMOS transistors. The connections of gates, sources, and drains of the first to eighth transistors T 1 to T 8 of FIG. 8C are the same as those of the first to eighth transistors T 1 to T 8 of FIG. 8A respectively.

FIG. 8D shows another variation of the circuit configuration of FIG. 8A . In FIG. 8D , each of the first and second transistors T 1 and T 2 is a bipolar transistor, and each of the third to eighth transistors T 3 to T 8 is a field-effect transistor. In FIG. 8D , the first and second transistors T 1 and T 2 are the NPN-type transistors, and the third to eighth transistors T 3 to T 8 are the pMOS transistors. The connections of the gates, the sources, and the drains of the third to eighth transistors T 3 to T 8 of FIG. 8D are the same as those of the third to eighth transistors T 3 to T 8 of FIG. 8A respectively.

FIG. 8E shows another variation of the circuit configuration of FIG. 8A . In FIG. 8E , each of the first and second transistors T 1 and T 2 is a field-effect transistor, and each of the third to eighth transistors T 3 and T 8 is a bipolar transistor. In FIG. 8E , the first and second transistors T 1 to T 2 are the nMOS transistors, and the third to eighth transistors T 3 to T 8 are the PNP-type transistors. The connections of the gates, the sources, and the drains of the first and second transistors T 1 to T 2 of FIG. 8E are the same as those of the first and second transistors T 1 to T 2 of FIG. 8A respectively.

As described above, each of the first to eighth transistors T 1 to T 8 may be a bipolar transistor or a field-effect transistor. Combination of these transistors is not limited to the combinations of FIG. 8A , FIG. 8C , FIG. 8D , and FIG. 8E .

The above description can also be applied to the second control current generating circuit 203 2 . The second control current generating circuit 203 2 includes a second current source C 2 , ninth to sixteenth transistors T 9 to T 16 , ninth to sixteenth resistor elements R 9 to R 16 , and fifth to eighth switches S 5 to S 8 . These circuit elements correspond to the first current source C 1 , the first to eighth transistors T 1 to T 8 , the first to eighth resistor elements R 1 to R 8 , and the first to fourth switches S 1 to S 4 respectively.

Furthermore, the above description can also be applied to the N-th control current generating circuit 203 N . The N-th control current generating circuit 203 N includes an N-th current source C N , (8N−7)-th to (8N)-th transistors T 8N−7 to T 8N , (8N−7)-th to (8N)-th resistor elements R 8N−7 to R 8N , and (4N−3)-th to (4N)-th switches S 4N−3 to S 4N . These circuit elements correspond to the first current source C 1 , the first to eighth transistors T 1 to T 8 , the first to eighth resistor elements R 1 to R 8 , and the first to fourth switches S 1 to S 4 respectively.

(Second Example of Circuit Configuration)

FIG. 9A shows a second example of the circuit configuration of the integrated circuit device 111 in FIG. 3 . FIG. 9A shows the control circuit 201 , the charging and discharging circuit 202 , the first control current generating circuit 203 1 , and the second control current generating circuit 203 2 . FIG. 9A further shows the time constant circuit 131 and the time constant control terminal 141 . The circuit configuration of FIG. 9A is a variation of that of FIG. 8A , and it will be described as focusing on differences from that of FIG. 8 A.

FIG. 9A further illustrates the circuit configuration of the first control current generating circuit 203 1 . The first control current generating circuit 203 1 includes the first V-I converting circuit 211 1 , the first and second mirror circuits 212 A1 and 212 B1 , and the first and second selecting and combining circuits 213 A1 and 213 B1 .

The first V-I converting circuit 211 1 includes the first current source C 1 , the first transistor T 1 , and the second transistor T 2 . FIG. 9B shows a variation of the circuit configuration of the first V-I converting circuit 211 1 . In FIG. 9B , the first resistor element R 1 is connected between the emitter of the transistor T 1 and the current source C 1 . In FIG. 9B , the second resistor element R 2 is connected between the emitter of the transistor T 2 and the current source C 1 .

The first mirror circuit 212 A1 includes the third transistor T 3 , the fourth transistor T 4 , and the fifth transistor T 5 . The third, fourth, and fifth resistor elements R 3 , R 4 , and R 5 are connected to the emitters of the transistors T 3 , T 4 , and T 5 respectively.

The second mirror circuit 212 B1 includes the sixth transistor T 6 , the seventh transistor T 7 , and the eighth transistor T 8 . The sixth, seventh, and eighth resistor elements R 6 , R 7 , and R 8 are connected to the emitters of the transistors T 6 , T 7 , and T 8 respectively.

The first selecting and combining circuit 213 A1 includes the first switch S 1 , and the second switch S 2 .

The second selecting and combining circuit 213 B1 includes the third switch S 3 , and the fourth switch S 4 .

Each of the first to eighth transistors T 1 to T 8 is a bipolar transistor. In this example, the first and second transistors T 1 and T 2 are PNP-type transistors, and the third to eighth transistors T 3 to T 8 are NPN-type transistors.

FIG. 9C shows a variation of the circuit configuration in FIG. 9A . In FIG. 9C , each of the first to eighth transistors T 1 to T 8 is a field-effect transistor. In FIG. 9C , the first and second transistors T 1 and T 2 are PMOS transistors, and the third to eighth transistors T 3 to T 8 are nMOS transistors. The connections of gates, sources, and drains of the first to eighth transistors T 1 to T 8 of FIG. 9C are the same as those of the first to eighth transistors T 1 to T 8 of FIG. 9A respectively.

FIG. 9D shows another variation of the circuit configuration of FIG. 9A . In FIG. 9D , each of the first and second transistors T 1 and T 2 is a bipolar transistor, and each of the third to eighth transistors T 3 to T 8 is a field-effect transistor. In FIG. 9D , the first and second transistors T 1 and T 2 are PNP-type transistors, and the third to eighth transistors T 3 to T 8 are nMOS transistors. The connections of gates, sources, and drains of the third to eighth transistors T 3 to T 8 of FIG. 9D are the same as those of the third to eighth transistors T 3 to T 8 of FIG. 9A respectively.

FIG. 9E shows another variation of the circuit configuration of FIG. 9A . In FIG. 9E , each of the first and second transistors T 1 and T 2 is a field-effect transistor, and each of the third to eighth transistors T 3 to T 8 is a bipolar transistor. In FIG. 9E , the first and second transistors T 1 and T 2 are pMOS transistors, and the third to eighth transistors T 3 to T 8 are NPN-type transistors. The connections of gates, sources, and drains of the first and second transistors T 1 and T 2 of FIG. 9E are the same as those of the first and second transistors T 1 and T 2 of FIG. 9A respectively.

As described above, each of the first to eighth transistors T 1 to T 8 is a bipolar transistor and a field-effect transistor. Combination of these transistors is not limited to the combinations of FIG. 9A , FIG. 9C , FIG. 9D , and FIG. 9E .

The above description can also be applied to the second control current generating circuit 203 2 . The second control current generating circuit 203 2 includes the second current source C 2 , the ninth to sixteenth transistors T 9 to T 16 , the ninth to sixteenth resistor elements R 9 to R 16 , and the fifth to eighth switches S 5 to S 8 . These circuit elements correspond to the first current source C 1 , the first to eighth transistors T 1 to T 8 , the first to eighth resistor elements R 1 to R 8 , and the first to fourth switches S 1 to S 4 respectively.

The above description can also be applied to the N-th control current generating circuit 203 N . The N-th control current generating circuit 203 N includes the N-th current source C N , the (8N−7)-th to (8N)-th transistors T 8N−7 to T 8N , the (8N−7)-th to (8N)-th resistor elements R 8N−7 to R 8N , and the (4N−3)-th to (4N)-th switches S 4N−3 to S 4N . These circuit elements correspond to the first current source C 1 , the first to eighth transistors T 1 to T 8 , the first to eighth resistor elements R 1 to R 8 , and the first to fourth switches S 1 to S 4 respectively.

As described above, embodiments of the present invention can provide a preferred integrated circuit device for muting an audio signal.