Comparator circuit

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-171821, filed on Jun. 29, 2007 and the prior Japanese Patent Application No. 2008-94599, filed on Apr. 1, 2008, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a comparator circuit, for example, a comparator circuit for an FSK (frequency shift keying) demodulation circuit, and a comparator circuit suited to binarizing an ASK (amplitude shift keying) signal demodulated using an RSSI (received signal strength indicator).

2. Background Art

In demodulating an FSK signal, it is common practice to remove a signal component included in the FSK signal to extract a DC component, deal with the extracted component as an average voltage of the FSK signal, and compare this voltage as a threshold voltage with the FSK signal, to generate binarized data.

In general, the average voltage is obtained using a primary low-pass filter including a resistor and a capacitor. The cut-off frequency of the low-pass filter is required to be sufficiently lower than the frequency of the signal component included in the FSK signal. For this reason, the capacitance of the capacitor becomes large, time for charging and discharging becomes long, the rise of the average voltage becomes slow, and hence it takes a long time to obtain the binarized data. Therefore, when the input signal voltage Vin varies, the average voltage Vref cannot adapt to it rapidly, due to the time constant of the primary low-pass filter including the resistor and the capacitor.

Particularly in a system which operates on battery, shortening the rise time is important for extending battery life, and therefore a charge/discharge circuit that rapidly charges and discharges the capacitor is required. To realize this, there has been used a technique that involves charging and discharging the capacitor by use of a diode.

However, with this arrangement, the signal voltage applied during charging or discharging the capacitor is constrained to the forward voltage VF of the diode. That is, in a case where Vin−Vref, which is obtained by subtracting the average voltage Vref from the input signal voltage Vin, is a positive value, the capacitor is charged when this value becomes larger than the forward voltage VF, whereas in a case where Vin−Vref is a negative value, the capacitor is discharged when this value becomes smaller than the forward voltage −VF. However, it is impossible to set arbitrarily a voltage at which charging/discharging is started, and therefore this voltage is fixed at ±VF.

Further, the forward voltage VF of a diode is about as large as 0.6 V, and it has been difficult to adapt to the reduction of the signal amplitude resulting from the recent trend toward low power-supply voltages. In addition, the forward voltage VF depends on temperature (−2 mV/° C.), and it has been difficult to obtain high reliability.

JP-A H5-252009 (KOKAI) describes an example of a slice level generating circuit including first and second operational amplifiers and first and second diodes.

Further, in demodulating an FSK signal or an AKS signal, it is common practice to generate an average voltage of the FSK signal or the AKS signal as a threshold, and compare the FSK signal or the AKS signal with the threshold, to binarize the FSK signal or the AKS signal.

In generating the average voltage, there is available a method that involves using a primary low-pass filter including a resistor and a capacitor. In this method that involves using the primary low-pass filter, if the cut-off frequency is set at a value sufficiently lower than the signal frequency to prevent the attenuation of the FSK signal or the ASK signal, the rise of the average voltage becomes slow and it takes a long time before the binarization is completed.

For this reason, when the method is applied to a system that operates on battery, the consumption of the battery becomes severe, the battery needs to be replaced frequently, and hence the usability of the system becomes poor.

An aspect of the present invention is, for example, a comparator circuit including a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.

FIG. 1 is a block diagram showing the configuration of an FSK receiving circuit to which a comparator circuit of a first embodiment can be applied;

FIG. 2 is a block diagram showing the configuration of the comparator circuit according to the first embodiment;

FIG. 3 is a graph showing the charge/discharge start voltage in the comparator circuit shown in FIG. 2 ;

FIG. 4 is a circuit diagram showing the configuration of a comparator circuit of a comparative example;

FIG. 5 is a graph showing the temperature dependence caused by a diode in the comparator circuit shown in FIG. 4 ;

FIG. 6 is a block diagram showing the configuration of a comparator circuit in a second embodiment;

FIGS. 7( a ) and 7 ( b ) are graphs showing the input signal voltage Vin=0.4 Vp-p, average voltage, and comparator output voltage in a comparator circuit having no charge/discharge circuit;

FIGS. 8( a ) and 8 ( b ) are graphs showing the input signal voltage Vin=0.4 Vp-p, average voltage, and comparator output voltage in the comparator according to the second embodiment;

FIGS. 9( a ) and 9 ( b ) are graphs showing the input signal voltage Vin=0.2 Vp-p, average voltage, and comparator output voltage in the comparator according to the second embodiment;

FIGS. 10( a ) and 10 ( b ) are graphs showing the input signal voltage Vin=0.6 Vp-p, average voltage, and comparator output voltage in the comparator according to the second embodiment;

FIG. 11 is a block diagram showing the configuration of a comparator according to a third embodiment;

FIG. 12 is a block diagram showing the configuration of a comparator according to a fourth embodiment;

FIG. 13 is a circuit diagram showing the configuration of a current output amplifier in the comparator shown in FIG. 12 ;

FIG. 14 is a graph showing the charge/discharge start voltage in the comparator shown in FIG. 12 ;

FIG. 15 is a block diagram showing a schematic configuration of a receiving circuit to which a charge/discharge circuit of a fifth embodiment is applied;

FIG. 16 is a diagram showing the RSSI characteristics of a RSSI detector in FIG. 15 ;

FIG. 17 is a block diagram showing a schematic configuration of a comparator circuit in FIG. 15 ;

FIG. 18 is a circuit diagram showing a schematic configuration of a charge/discharge section in FIG. 17 ;

FIG. 19-1 is a diagram showing the RSSI waveform during a weak input before clipping in the charge/discharge circuit of FIG. 15 ;

FIG. 19-2 is a diagram showing the RSSI waveform during a weak input after clipping in the charge/discharge circuit of FIG. 15 ;

FIG. 20-1 is a diagram showing the RSSI waveform during a strong input before clipping in the charge/discharge circuit of FIG. 15 ;

FIG. 20-2 is a diagram showing the RSSI waveform during a strong input after clipping in the charge/discharge circuit of FIG. 15 ;

FIG. 21-1 is a circuit diagram showing a schematic configuration of a peak hold circuit which is applied to a charge/discharge circuit of a sixth embodiment;

FIG. 21-2 is a circuit diagram showing a schematic configuration of a peak hold circuit which is applied to a charge/discharge circuit of a seventh embodiment;

FIG. 22 is a circuit diagram showing a schematic configuration of a peak hold circuit which is applied to a charge/discharge circuit of an eighth embodiment;

FIG. 23-1 is a circuit diagram showing a schematic configuration of a clipping circuit which is applied to a charge/discharge circuit of a ninth embodiment;

FIG. 23-2 is a circuit diagram showing a schematic configuration of a clipping circuit which is applied to a charge/discharge circuit of a tenth embodiment;

FIG. 24 is a circuit diagram showing a schematic configuration of a clipping circuit which is applied to a charge/discharge circuit of an eleventh embodiment;

FIG. 25 is a block diagram showing a schematic configuration of a comparator circuit to which a charge/discharge circuit of a twelfth embodiment is applied;

FIG. 26 is a diagram showing an example of the clipping level variable characteristics of the charge/discharge circuit in FIG. 25 ;

FIG. 27-1 is a diagram showing the RSSI waveform during a weak input after clipping in the charge/discharge circuit of FIG. 25 ;

FIG. 27-2 is a diagram showing the RSSI waveform during a strong input after clipping in the charge/discharge circuit of FIG. 25 ;

FIG. 28-1 is a circuit diagram showing a schematic configuration of a charge/discharge section which is applied to a charge/discharge circuit of a thirteenth embodiment;

FIG. 28-2 is a circuit diagram showing a schematic configuration of a charge/discharge section which is applied to a charge/discharge circuit of a fourteenth embodiment;

FIG. 29 is a circuit diagram showing a schematic configuration of a charge/discharge section which is applied to a charge/discharge circuit of a fifteenth embodiment;

FIG. 30 is a circuit diagram showing a schematic configuration of a threshold variable circuit which is applied to a charge/discharge circuit of a sixteenth embodiment; and

FIG. 31 is a block diagram showing a schematic configuration of a comparator circuit to which a charge/discharge circuit of a seventeenth embodiment is applied.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, a description will be given regarding the configuration of an FSK receiving circuit including a comparator circuit of an embodiment of the present invention, with reference to FIG. 1 .

A signal received by an antenna (ANT) 101 is amplified by a low-noise amplifier (LNA) 102 . Then, the frequency of the received signal is lowered by a mixer (MIX) 103 . Then, components except an intermediate frequency (IF) are removed from the received signal by an IF filter (IFF) 104 .

After that, the received signal is amplified by an IF amplifier (IF_AMP) 105 , and detected by an FM detector (DET) 106 . Then, only necessary low-frequency components of the received signal pass through a low-pass filter (LPF) 107 . Furthermore, the voltage of the filtered signal is compared, by a comparator (COMP) circuit 108 , with an average voltage which is obtained by removing signal components from the filtered signal, and a signal is outputted.

A description will be given regarding a comparator circuit of a first embodiment, which is applied to the comparator circuit 108 in the above FSK receiving circuit.

First Embodiment

FIG. 2 shows the configuration of a comparator circuit in the first embodiment.

In the FM detection by the above FSK receiving circuit, the DC voltage of a detection output varies in proportion to the input frequency. Therefore, the DC voltage varies when there happens a change from a no-signal condition to a condition in which a signal is present, and the comparator circuit 108 is required to adapt to this change rapidly.

This comparator circuit 108 has a comparator COM whose first and second input terminals are connected to resistors R 1 and R 2 respectively, and an input signal voltage Vin is input to the first and second input terminals via an input terminal IN.

A capacitor C is connected between the second input terminal and a ground terminal. An average voltage Vref which is used for comparison is generated in the second input terminal by a low-pass filter including the resistor R 2 and the capacitor C. A charge/discharge circuit CDC 1 is provided to rapidly charge and discharge the capacitor C.

The charge/discharge circuit CDC 1 is provided with an operational amplifier OP 1 , a voltage V 1 , and a diode D 1 for discharging, and provided with an operational amplifier OP 2 , a voltage V 2 , and a diode D 2 for charging, between the input terminal IN and the second terminal of the comparator COM.

The operational amplifier OP 1 has a non-inverting input terminal to which the input signal voltage Vin+V 1 is input, and an inverting input terminal to which the average voltage Vref is input. When Vin+V 1 <Vref, a current flows from the capacitor C to the diode D 1 , and flows from an output terminal of the operational amplifier OP 1 to the ground terminal, thereby the capacitor C is discharged.

On the other hand, the operational amplifier OP 2 has a non-inverting input terminal to which the input signal voltage Vin−V 2 is input, and an inverting input terminal to which the average voltage Vref is input. When Vin−V 2 >Vref, a current flows from a power-source terminal to an output terminal of the operational amplifier OP 2 , to the diode D 2 , and to the capacitor C, thereby the capacitor C is charged.

As described above, a discharge start voltage is set by the voltage V 1 connected to the non-inverting input terminal of the operational amplifier OP 1 , and a charge start voltage is set by the voltage V 2 connected to the non-inverting input terminal of the operational amplifier OP 2 . When the input signal voltage Vin becomes lower from the average voltage Vref by more than V 1 , the operational amplifier OP 1 works to discharge the capacitor C. When the input signal voltage Vin becomes higher from the average voltage Vref by more than V 2 , the operational amplifier OP 2 works to charge the capacitor C.

Therefore, according to the first embodiment, it is possible to set each of the charge and discharge start voltages at any value.

The voltages V 1 and V 2 may be set at the same level, or may be set at different values. When variations due to temperature do not occur in the voltages V 1 and V 2 , variations due to temperature do not occur in the circuit. However, when variations due to temperature occur in the detection output level, temperature corrections can be performed by changing the voltages V 1 and V 2 according to variations due to temperature in the detection output level.

FIG. 3 shows the relationship between the voltage Vin−Vref and the current I which charges and discharges the capacitor C in a circuit of the first embodiment. When the voltage Vin−Vref becomes larger than the voltage V 2 (Vin−Vef>V 2 , i.e., Vin−V 2 >Vref), the capacitor C is charged. When the voltage Vin−Vref becomes smaller than the voltage −V 1 (Vin−Vref<−V 1 , i.e., Vin+V 1 <Vref), the capacitor C is discharged.

When the operational amplifiers OP 1 and OP 2 have input DC offset voltages VOFF 1 and VOFF 2 respectively, they are taken into consideration in this embodiment. In this case, when the voltage Vin−Vref becomes larger than the voltage V 2 −VOFF 2 (Vin−Vref>V 2 −VOFF 2 , i.e., Vin−(V 2 −VOFF 2 )>Vref), the capacitor C is charged. Further, when the voltage Vin−Vref becomes smaller than the voltage −V 1 −VOFF 1 (Vin−Vref<−V 1 −VOFF 1 , i.e., Vin+(V 1 +VOFF 1 )<Vref), the capacitor is discharged. The charge and discharge start voltages when such input DC offset voltages are considered, apply also to the second to fourth embodiments below. There are offset voltages that are parasitic on a circuit, and offset voltages that are intentionally set for circuit design.

As described above, according to the first embodiment, it is possible to set the charge/discharge start voltage at any value by setting the voltage V 1 , V 2 at any value. When there is no variation due to temperature in the voltage V 1 , V 2 , it is possible to improve the circuit characteristics without being affected by temperature variation regarding the circuit operation.

Comparative Example

FIG. 4 shows the configuration of a comparator circuit in a comparative example. In this circuit, diodes D 101 and D 102 are provided in parallel on both ends of a resistor R 2 , as a charge/discharge circuit CDC 101 that charges and discharges a capacitor C.

When a voltage difference between the input signal voltage Vin and the average voltage Vref exceeds a forward voltage VF of the diode (Vin−Vref>VF), the capacitor C is charged. When a voltage difference between the input signal voltage Vin and the average voltage Vref becomes lower than a negative value of the forward voltage VF of the diode (Vin−Vref<−VF), the capacitor is discharged.

The relationship between the voltage (Vin−Vref) and the charge/discharge current I in this case is shown in FIG. 5 . The charge/discharge start voltage at which charging/discharging to the capacitor C is started, is determined by the forward voltage ±VF of the diodes D 101 , D 102 . When the temperature is 25° C., this charge/discharge start voltage becomes approximately ±0.6 V.

This value is considerably high in spite of recent requirements for low power-supply voltages, and cannot be set at any value. Furthermore, as shown in FIG. 5 , since the forward voltage of a diode varies depending on temperature, the charge/discharge start voltage also varies, which causes deterioration in the circuit characteristics.

If the input signal voltage is denoted by Vin (p-p), the relationship expressed by 2×VF≧Vin (p-p)>VF must be satisfied to raise the charge/discharge speed. In particular, when 2×VF=Vin (p-p), the charge/discharge speed becomes fastest, and it is possible to make fast the rise of the average voltage Vref.

However, because the forward voltage VF varies greatly due to temperature as described, it is difficult to set the voltage so that the relationship is satisfied.

When 2×VF>Vin (p-p)>VF, the rise of the average voltage Vref becomes late and it takes a long time before the average voltage Vref reaches the level of the input signal voltage Vin. For this reason, the comparator COM starts working fast, although the duty ratio reaches 50% late.

When the relationship 2×VF<Vin (p-p) holds, the average voltage Vref fluctuates greatly, and regarding a modulated wave, the duty ratio deviates from 50%, so that errors become apt to occur in output data from the comparator COM. Furthermore, because noise occurs in the average voltage Vref, the S/N ratio deteriorates and sensitivity worsens.

When Vin (p-p)<VF, the comparator COM starts working late.

The temperature characteristics of the forward voltage VF of the diode is −2 mV/° C. Here, it is assumed VF=0.6 V at 25° C. When the temperature ±65° C. is considered on the basis of 25° C., VF=0.73 V at −40° C. and VF=0.47 V at +90° C. Therefore, a variation of 0.26 V occurs. For this reason, it is difficult to set the forward voltage VF so that the relationship 2×VF=Vin (p-p) is satisfied.

As described above, in the comparative example, the characteristics of the charge/discharge circuit are greatly influenced by the temperature characteristics of the forward voltage VF of the diode, and a large amplitude is required for the input signal voltage Vin due to the large voltage VF. Therefore, the comparator circuit cannot be used at low power-supply voltages.

Second Embodiment

A comparator circuit in the second embodiment will be described with reference to FIG. 6 showing the configuration of the comparator circuit.

The second embodiment differs from the above-described first embodiment in that a gain-variable type operational amplifier OP 3 is connected in series between the input terminal IN, and the connection point of the resistors R 1 and R 2 in the first embodiment.

The level of an input signal voltage Vin 1 input from the input terminal IN is changed by the gain-variable type operational amplifier OP 3 , and the input signal voltage Vin 1 is output to the succeeding stage as an input signal Vin 2 .

According to the second embodiment, even in a case where an input signal voltage Vin 1 given by the low-pass filter 107 in the preceding stage shown in FIG. 1 fluctuates and varies, an adjustment is made so that the relationship 2×V 1 (or V 2 )=Vin 2 (p-p) holds by changing the level by use of the gain-variable type operational amplifier OP 3 , thereby it is possible to make fast the rise of the average voltage Vref.

Other elements that are the same as in the above-described first embodiment are identified by the same reference numerals as in the first embodiment, and the descriptions of these elements are omitted.

Subsequently, a comparator circuit not provided with a charge/discharge circuit and the comparator circuit in the above-described second embodiment will be described by making a comparison with reference to graphs showing the characteristics of the comparator circuits.

It is assumed that the comparator circuits work sufficiently even when the power source voltage is as low as 3 V. The average voltage Vref in the input signal voltage Vin is set at 1.0 V, and the charge/discharge start voltage is set at 0.2 V.

The input signal voltage Vin (=0.4 V p-p) and the waveform of the generated average voltage Vref in the comparator circuit not provided with a charge/discharge circuit are shown in FIG. 7( a ), and the output voltage waveform from the comparator circuit is shown in FIG. 7( b ).

In the comparator circuit not provided with a charge/discharge circuit, the average voltage Vref rises late and as a result of this, it takes time before an output is obtained from the comparator circuit.

The input signal voltage Vin (=0.4 V p-p) and the waveform of the generated average voltage Vref in the comparator circuit in the second embodiment are shown in FIG. 8( a ), and the output voltage waveform from the comparator circuit is shown in FIG. 8( b ).

In this case, the average voltage Vref rises fast and a duty ratio of 50% is reached in a short time.

In the comparator circuit of the second embodiment, the waveform of the average voltage Vref in a case where the input signal voltage Vin is 0.2 V p-p is shown in FIG. 9( a ), and the output voltage waveform from the comparator circuit is shown in FIG. 9( b ).

In this case, although the average voltage Vref rises fast, a longer time is required until the duty ratio reaches 50% than in the case where the input signal voltage Vin is 0.4 V p-p.

Furthermore, in the comparator circuit of the second embodiment, the waveform of the average voltage Vref in a case where the input signal voltage Vin is 0.6 V p-p is shown in FIG. 10( a ), and the output voltage waveform from the comparator circuit is shown in FIG. 10( b ).

In this case, the relationship Vin−Vref (=0.6 V p-p)>2×V (=0.2 V) holds. Although the rise of the average voltage Vref is fast and the output waveform rises in a short time, the average voltage Vref is not composed of DC components alone and includes AC components and the level varies. Therefore, this lowers the sensitivity regarding the output characteristics from the comparator circuit.

As described above, the relationship between the input signal voltage Vin and the charge/discharge start voltages V 1 , V 2 is important, and it is preferred that the relationship 2×V 1 (or V 2 )=Vin (p-p) hold as far as possible.

According to the second embodiment, it is possible to set the charge/discharge start voltages V 1 , V 2 at any value, and therefore it is possible to perform charging/discharging at a high speed even when the amplitude of the input signal voltage Vin is reduced due to low power-supply voltages.

Third Embodiment

The configuration of a comparator according to the third embodiment is shown in FIG. 11 . In the above-described second embodiment, the level of the input signal voltage Vin is made variable, thereby an adjustment is made so that the relationship 2×V 1 (or V 2 )=Vin 2 (p-p) holds.

In contrast to this, in the third embodiment, the charge/discharge start voltage is made variable in the stage when the charge/discharge start voltage is input to the operational amplifiers OP 1 , OP 2 in a charge/discharge circuit CDC 3 , thereby voltages V 1 a , V 1 b are adjusted as variable voltages so that the relationship 2×V 1 a (or V 1 b )=Vin 2 (p-p) holds.

Other elements that are the same as in the above-described first embodiment are identified by the same reference numerals as in the first embodiment, and the descriptions of these elements are omitted.

Fourth Embodiment

FIG. 12 shows the configuration of a comparator according to the fourth embodiment.

In all of the first to third embodiments of the present invention, the operational amplifiers OP 1 , OP 2 are used, and it is necessary to set the direction of charging or discharging by connecting the diodes D 1 , D 2 to the output terminal.

For this reason, the output voltage drops due to the presence of the diodes D 1 , D 2 by the same amount as the forward voltage VF, and the dynamic range of charge/discharge operation becomes narrow. For example, if the power-supply voltage VCC is 3 V and the forward voltage VF is 0.6 V, operations are performed in the range of 0.6 V to 2.4 V.

On the other hand, in the fourth embodiment, current output amplifiers OP 11 , OP 12 are used. Because no diode is connected to the output terminals of the current output amplifiers OP 11 , OP 12 , the dynamic range does not become narrow and in the above-described example operations can be performed in the range of 0 V to 3 V.

In FIG. 12 , current sources are shown at the output terminals of the current output amplifiers OP 11 , OP 12 . However, the current sources are not actually connected; they schematically show that the current output amplifiers OP 11 , OP 12 are the current output type.

In the first to third embodiments, the diodes D 1 , D 2 are used, and therefore the dynamic range becomes narrow. Unlike the above comparative example, however, the use of the diodes D 1 , D 2 has no effect on the charge/discharge start voltages V 1 , V 2 , and the temperature characteristics of the diodes do not exert an influence on the charge/discharge start voltages V 1 , V 2 , either.

In the fourth embodiment, other elements that are the same as in the first embodiment are identified by the same reference numerals as in the first embodiment, and the descriptions of these elements are omitted.

FIG. 13 shows a detailed circuit configuration of a charge/discharge circuit CDC 4 in the fourth embodiment.

A current source 11 and a resistor R 21 are connected between a power-supply terminal and an input terminal IN, and a voltage V 1 is generated at the connection point. A current source 12 and a resistor 22 are connected between the input terminal IN and a ground terminal, and a voltage V 2 is generated at the connection point.

The current output amplifier OP 11 includes PNP type bipolar transistors T 1 and T 2 , and NPN type bipolar transistors T 3 to T 6 . A voltage V 1 is input to the current output amplifier OP 11 . The current output amplifier OP 12 includes PNP type bipolar transistors T 11 , T 12 , T 17 , and T 18 , and NPN type bipolar transistors T 13 to T 16 . A voltage V 2 is input to the current output amplifier OP 12 . Output terminals of the current output amplifier OP 11 and the current output amplifier OP 12 are connected to a second input terminal of a comparator COM.

FIG. 13 shows a first current mirror including T 1 and T 2 , a second current mirror including T 3 and T 4 , and a third current mirror including T 5 and T 6 , which are included in the current output amplifier OP 11 . Further, FIG. 13 shows a first current mirror including T 11 and T 12 , a second current mirror including T 13 and T 14 , and a third current mirror including T 15 and T 16 , which are included in the current output amplifier OP 12 . Bases, emitters, and collectors of the transistors T 1 to T 16 are shown in FIG. 13 , and are connected each other or to other elements as shown in FIG. 13 .

For the voltage V 1 , the relationship V 1 =11×R 21 holds between a current I 1 flowing through a current source CS 21 and a resistance value R 21 of the resistor R 21 . For a voltage V 2 , the relationship V 2 =12×R 22 holds between a current I 2 flowing through a current source CS 22 and a resistance value R 22 of the resistor R 22 . Therefore, by providing the current sources CS 21 , CS 22 as variable current sources and changing the currents I 1 , I 2 , it is possible to set the charge/discharge start voltage of the current output amplifiers OP 11 , OP 12 at a desired value.

FIG. 14 shows the voltage-current characteristics between the input signal voltage Vin−average voltage Vref and the charge/discharge current I in a comparator according to the fourth embodiment.

The capacitor C is charged when the voltage Vi−Vref exceeds V 2 , and the capacitor C is discharged when the voltage Vi−Vref becomes lower than −V 1 . In FIG. 14 , the current necessary for charging/discharging is ±I 1 , and it is preferred that the current be set so that operations are performed within a range in which the relationship between the voltage Vi−Vref and the current I is linear. As a result of this, unlike in a range in which the relationship between the voltage Vi−Vref and the current I is not linear, a high response speed is obtained.

The comparator circuits in the above-described first to fourth embodiments can also be used as an FSK receiving circuit by being applied to the comparator circuit 108 shown in FIG. 1 .

For example, an FSK receiving circuit of an aspect of the present invention includes: an antenna configured to receive a signal; a low-noise amplifier configured to amplify the signal received by the antenna; a mixer configured to reduce the frequency of a signal output from the low-noise amplifier; an intermediate frequency filter configured to remove components except an intermediate frequency from a signal output from the mixer; an intermediate frequency amplifier configured to amplify a signal output from the intermediate frequency filter; a detector configured to detect a signal output from the intermediate frequency amplifier, a low-pass filter configured to cause low-frequency components of a signal detected by the detector to pass; and a comparator circuit configured to output a result of a comparison between the voltage of a signal output from the low-pass filter and the average voltage of this signal. In this FSK receiving circuit, the comparator circuit includes: a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal voltage by use of a resistor and a capacitor, and output a result of the comparison; a discharge circuit configured to compare a first addition signal which is obtained by adding a first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference signal; and a charge circuit configured to compare a second addition signal which is obtained by adding a second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.

Fifth Embodiment

FIG. 15 is a block diagram showing a schematic configuration of a receiving circuit to which a charge/discharge circuit of a fifth embodiment is applied.

In FIG. 15 , the receiving circuit is provided with an antenna 11 that receives a radio wave, a low-noise amplifier 12 that amplifies a signal received by the antenna 11 , a mixer 13 that downconverts the carrier frequency of the received signal amplified by the low-noise amplifier 12 to an intermediate frequency, an intermediate frequency filter 14 that removes unnecessary band components from the intermediate frequency signal downconverted by the mixer 13 , a limiter amplifier 15 that amplifies the intermediate frequency signal passing through the intermediate frequency filter 14 , an FM detector 16 that FM-demodulates an FSK signal amplified by the limiter amplifier 15 , an RSSI detector 17 that AM-demodulates an ASK signal amplified by the limiter amplifier 15 , and a comparator circuit (binarization circuit) 18 that binarizes the FSK signal and ASK signal demodulated by the FM detector 16 and the RSSI detector 17 respectively.

When an FSK signal is received by the antenna 11 , the FSK signal is amplified by the low-noise amplifier 12 , downconverted by the mixer 13 to an intermediate frequency, and input to the intermediate frequency filter 14 . Subsequently, unnecessary band components of the FSK signal is removed by the intermediate frequency filter 14 , and then the FSK signal is amplified by the limiter amplifier 15 , FM-demodulated by the FM detector 16 , and input to the comparator circuit 18 . In the comparator circuit 18 , the FSK signal output from the FM detector 16 is smoothed to generate a reference voltage Vref of the FSK signal. Further, the FSK signal is binarized by comparing this reference voltage Vref with the FSK signal, and outputted as binarized data.

On the other hand, when an ASK signal is received by the antenna 11 , the ASK signal is amplified by the low-noise amplifier 12 , downconverted by the mixer 13 to an intermediate frequency, and input to the intermediate frequency filter 14 . Subsequently, unnecessary band components of the ASK signal is removed by the intermediate frequency filter 14 , and then the ASK signal is amplified by the limiter amplifier 15 , AM-demodulated by the RSSI detector 17 , and input to the comparator circuit 18 . In the comparator circuit 18 , the ASK signal output from the RSSI detector 17 is smoothed to generate a reference voltage Vref of the ASK signal. Further, the ASK signal is binarized by comparing this reference voltage Vref with the ASK signal, and is outputted as binarized data.

FIG. 16 is a diagram showing the RSSI characteristics of the RSSI detector in FIG. 15 .

As shown in FIG. 16 , in the RSSI detector 17 , the RSSI level increases with increasing input level. For this reason, the level of a demodulated signal input to the comparator circuit 18 varies depending on the input level of a received signal.

In the comparator circuit 18 , it is possible to pass an FSK signal and an ASK signal through a low-pass filter including a resistor and a capacitor, to generate the reference voltage Vref of the FSK signal and the reference voltage Vref of the ASK signal. A capacitor voltage generated when the capacitor is charged/discharged can be used as the reference voltage Vref. In this case, in order to make fast the rise of the reference voltage Vref, the capacitor that generates the reference voltage Vref can be rapidly charged and discharged, and in order to rapidly charge/discharge the capacitor, it is possible to charge/discharge the capacitor while bypassing the resistor constituting the low-pass filter. As a method of charging/discharging the capacitor while bypassing the resistor constituting this low-pass filter, it is possible to use a method that involves connecting a bidirectional diode characteristic circuit to the resistor.

FIG. 17 is a block diagram showing a schematic configuration of the comparator circuit in FIG. 15 .

In FIG. 17 , the comparator circuit 18 is provided with a comparator 27 that generates binarized date by comparing an input signal with the reference voltage Vref. One input terminal of the comparator 27 is connected to the output side of a low-pass filter 26 via a resistor R 1 , and the other input terminal of the comparator 27 is connected to the output side of the low-pass filter 26 via a resistor R 2 and also to a capacitor C 2 . The resistor R 2 and the capacitor C 2 can constitute a smoothing circuit including a low-pass filter, and the capacitor C 2 can generate the reference voltage Vref used as a threshold of the comparator 27 .

The comparator circuit 18 is also provided with a charge/discharge circuit 21 that rapidly charges and discharges the capacitor C 2 , and the charge/discharge circuit 21 is provided with a clipping circuit 22 , a peak hold circuit 23 , and a charge/discharge section 24 . The charge/discharge section 24 can charge and discharge the capacitor C 2 by bypassing the resistor R 2 , which constitutes a smoothing circuit with the capacitor C 2 . The charge/discharge section 24 in FIG. 17 corresponds to the charge/discharge circuit CDC 1 in FIG. 2 .

The peak hold circuit 23 can detect a peak value of an input signal input to the charge/discharge section 24 , and is connected to a capacitor C 1 that holds this peak value of the input signal. The clipping circuit 22 can clip a level lower than a given value, from the peak value of the input signal.

One input side of a switch 25 is connected to the output side of the FM detector 16 of FIG. 15 , the other input side of the switch 25 is connected to the output side of the RSSI detector 17 of FIG. 15 via the clipping circuit 22 , and the output side of the switch 25 is connected to the input side of the low-pass filter 26 .

FIG. 18 is a circuit diagram showing a schematic configuration of the charge/discharge section in FIG. 17 .

In FIG. 18 , the charge/discharge section 24 is provided with diodes D 1 , D 2 . The diodes D 1 , D 2 are connected parallel to a resistor R 2 so that the directions of the diodes D 1 , D 2 become reversed to each other.

In FIG. 17 , when an FSK signal is received by the antenna 11 , the switch 25 is changed over to the FM detector 16 side. After the removal of unnecessary high-frequency components by the low-pass filter 26 , an FSK signal demodulated by the FM detector 16 is input to one input terminal of the comparator 27 via the resistor R 1 , and input to the charge/discharge section 24 . In the charge/discharge section 24 , in a case where the amplitude of the FSK signal is larger than the reference voltage Vref, a current is caused to flow into the capacitor C 2 via the diode D 1 of FIG. 18 , thereby the reference voltage Vref is raised, whereas in a case where the amplitude of the FSK signal is smaller than the reference voltage Vref, a current is caused to flow from the capacitor C 2 via the diode D 2 of FIG. 18 , thereby the reference voltage Vref is lowered. In this manner, a reference voltage Vref which is obtained by smoothing the FSK signal is generated in the capacitor C 2 .

The reference voltage Vref generated by the capacitor C 2 is input to the other input terminal of the comparator 27 , and compared with the FSK signal input via the resistor R 1 , thereby binarized data is generated.

On the other hand, when an ASK signal is received by the antenna 11 , the switch 25 is changed to the clipping circuit 22 side. After the removal of unnecessary high-frequency components by the low-pass filter 26 , an ASK signal output via the clipping circuit 22 is input to one input terminal of the comparator 27 via the resistor R 1 and input to the peak hold circuit 23 and the charge/discharge section 24 .

When the ASK signal is input to the peak hold circuit 23 , a peak value of the ASK signal is detected and output to the clipping circuit 22 . In the clipping circuit 22 , a signal lower than the clipping level is clipped from the peak value of the ASK signal, thereby the amplitude of the ASK signal is equalized, and the ASK signal is input to the charge/discharge section 24 via the low-pass filter 26 .

In the charge/discharge section 24 , in a case where the amplitude of the ASK signal is larger than the reference voltage Vref, a current is caused to flow into the capacitor C 2 via the diode D 1 of FIG. 18 , thereby the reference voltage Vref is raised, whereas in a case where the amplitude of the ASK signal is smaller than the reference voltage Vref, a current is caused to flow from the capacitor C 2 via the diode D 2 of FIG. 18 , thereby the reference voltage Vref is lowered. In this manner, a reference voltage Vref which is obtained by smoothing the ASK signal is generated in the capacitor C 2 .

The reference voltage Vref generated in the capacitor C 2 is input to the other input terminal of the comparator 27 and compared with the ASK signal input via the resistor R 1 , thereby binarized data is generated.

By equalizing the amplitude of the ASK signal in the clipping circuit 22 , it is possible to keep constant the amplitude of an input signal which is to be compared with the reference voltage Vref, even in demodulating the ASK signal using the RSSI. For this reason, even when the charging/discharging of the capacitor C 2 is performed via the charge/discharge section 24 , it is possible to keep the average voltage Vref stable, and even in demodulating the ASK signal using the RSSI, the rise of the average voltage Vref can be made fast, and therefore it is possible to reduce the consumption of a battery in a system that operates on the battery.

FIG. 19-1 is a diagram showing the RSSI waveform during a weak input before clipping in the charge/discharge circuit of FIG. 15 . FIG. 19-2 is a diagram showing the RSSI waveform during a weak input after clipping in the charge/discharge circuit of FIG. 15 . FIG. 20-1 is a diagram showing the RSSI waveform during a strong input before clipping in the charge/discharge circuit of FIG. 15 . FIG. 20-2 is a diagram showing the RSSI waveform during a strong input after clipping in the charge/discharge circuit of FIG. 15 .

In FIGS. 19-1 and 20 - 1 , the amplitude of an ASK signal demodulated by using RSSI changes depending on the level of a received signal. By setting the clipping level of the clipping circuit 22 so that levels lower than a given value are clipped from the peak value of the ASK signal as shown in FIGS. 19-2 and 20 - 2 , even in demodulating the ASK signal using the RSSI, it is possible to keep constant the amplitude of an input signal input to the charge/discharge section 24 , and it is possible to rapidly charge and discharge the capacitor C 2 via the charge/discharge section 24 .

By clipping levels lower than a given value from the peak value of the ASK signal, the bit information of a base band (0, 1) is caused to correspond to the binary amplitude of a carrier wave (Levels L and H), which is OOK (on off keying). Even when Level L comes to a no-signal condition, it is possible to remove noise that is generated in a no-signal condition, and noise resistance can be improved. The clipping circuit 22 may configured to clip a level equal to a given value, from the peak value of the input signal, or may be configured not to clip a level equal to a given value, from the peak value of the input signal.

Sixth Embodiment

FIG. 21-1 is a circuit diagram showing a schematic configuration of a peak hold circuit which is applied to a charge/discharge circuit of a sixth embodiment.

In FIG. 21-1 , an output terminal of an operational amplifier 31 is connected to a non-inverting input terminal of the operational amplifier 31 via a diode D 11 and a resistor R 11 in sequence and connected to an inverting input terminal of the operational amplifier 31 via the diode D 11 . A cathode terminal of the diode D 11 is connected to a capacitor C 1 and a buffer 32 respectively.

When the input voltage Vin is input to the non-inverting input terminal of the operational amplifier 31 , the input voltage Vin is compared with the capacitor voltage Vpeak of the capacitor C 1 . When the input voltage Vin is larger than the capacitor voltage Vpeak, a voltage is applied to the capacitor C 1 via the diode D 11 , and the capacitor C 1 is charged until the capacitor voltage Vpeak becomes equal to a peak value of the input voltage Vin, thereby the peak value of the input voltage Vin is held in the capacitor C 1 .

Seventh Embodiment

FIG. 21-2 is a circuit diagram showing a schematic configuration of a peak hold circuit which is applied to a charge/discharge circuit of a seventh embodiment.

In the peak hold circuit diagram of FIG. 21-2 , a current supply circuit I 11 is provided in place of the diode D 11 of FIG. 21-1 . When the input voltage Vin is larger than the capacitor voltage Vpeak, a current is supplied to the capacitor C 1 via the current supply circuit I 11 and the capacitor C 1 is charged until the capacitor voltage Vpeak becomes equal to a peak value of the input voltage Vin, thereby the peak value of the input voltage Vin is held in the capacitor C 1 .

Eighth Embodiment

FIG. 22 is a circuit diagram showing a schematic configuration of a peak hold circuit which is applied to a charge/discharge circuit of an eighth embodiment.

In FIG. 22 , bipolar transistors M 11 , M 12 constitute a differential amplifier, and a current source I 21 is connected to collectors of the bipolar transistors M 11 , M 12 as a common current source. Bipolar transistors M 13 , M 14 constitute a current mirror for a current flowing through the bipolar transistor M 11 , bipolar transistors M 15 , M 16 constitute a current mirror for a current flowing through the bipolar transistor M 12 , and bipolar transistors M 17 , M 18 constitute a current mirror for a current flowing through the bipolar transistor M 16 .

Incidentally, the PNP type can be used for the bipolar transistors M 11 , M 12 , M 17 , M 18 , and the NPN type can be used for the bipolar transistors M 13 , M 14 , M 15 , M 16 .

When the input voltage Vin is input to a base of the bipolar transistor M 11 , the input voltage Vin is compared with the capacitor voltage Vpeak of a capacitor C 1 . In a case where the input voltage Vin is larger than the capacitor voltage Vpeak, the bipolar transistor M 12 becomes on, thereby a current flows through the bipolar transistor M 12 . When a current flows through the bipolar transistor M 12 , a current flows through the bipolar transistor M 16 due to the current mirror operation of the bipolar transistors M 15 , M 16 . When a current flows through the bipolar transistor M 16 , a current flows through the bipolar transistor M 18 due to the current mirror operation of the bipolar transistors M 17 , M 18 . When a current flows through the bipolar transistor M 18 , a current is supplied to the capacitor C 1 and the capacitor C 1 is charged until the capacitor voltage Vpeak becomes equal to a peak value of the input voltage Vin, thereby the peak value of the input voltage Vin is held in the capacitor C 1 .

Ninth Embodiment

FIG. 23-1 is a circuit diagram showing a schematic configuration of a clipping circuit which is applied to a charge/discharge circuit of a ninth embodiment.

In FIG. 23-1 , an output terminal of an operational amplifier 41 is connected to an inverting input terminal of the operational amplifier 41 via a diode D 21 , and a variable voltage source VR 1 is connected to a non-inverting input terminal of the operational amplifier 41 . A cathode terminal of the diode D 21 is connected to a resistor 21 and a buffer 42 respectively.

After the capacitor voltage Vpeak of a capacitor C 1 is caused to drop by a voltage corresponding to a voltage set in the variable voltage source VR 1 , the capacitor voltage Vpeak is input to the non-inverting input terminal of the operational amplifier 41 . When the input voltage Vin is input to the non-inverting input terminal of the operational amplifier 41 via the resistor R 21 , the output voltage Vout is compared with the voltage caused to drop from the capacitor voltage Vpeak by a voltage corresponding to a voltage set in the variable voltage source VR 1 . When the output voltage Vout is lower than the voltage caused to drop from the capacitor voltage Vpeak by a voltage corresponding to a voltage set in the variable voltage source VR 1 , the operational amplifier 41 adjusts the voltage output so that the output voltage Vout becomes equal to the voltage caused to drop from the capacitor voltage Vpeak by a voltage corresponding to a voltage set in the variable voltage source VR 1 , thereby Level L of the output voltage Vout is clipped so that the amplitude of the output voltage Vout becomes constant.

Tenth Embodiment

FIG. 23-2 is a circuit diagram showing a schematic configuration of a clipping circuit which is applied to a charge/discharge circuit of a tenth embodiment.

In the clipping circuit of FIG. 23-2 , a current supply circuit I 31 is provided in place of the diode D 21 of FIG. 23-1 . When the output voltage Vout is lower than the voltage caused to drop from the capacitor voltage Vpeak by a voltage corresponding to a voltage set in the variable voltage source VR 1 , an operational amplifier 41 adjusts the current output so that the output voltage Vout becomes equal to the voltage caused to drop from the capacitor voltage Vpeak by a voltage corresponding to a voltage set in the variable voltage source VR 1 , thereby Level L of the output voltage Vout is clipped so that the amplitude of the output voltage Vout becomes constant.

Eleventh Embodiment

FIG. 24 is a circuit diagram showing a schematic configuration of a clipping circuit which is applied to a charge/discharge circuit of an eleventh embodiment.

In FIG. 24 , bipolar transistors M 31 , M 32 constitute a differential amplifier, and a current source I 41 is connected to collectors of the bipolar transistors M 31 , M 32 as a common current source. Bipolar transistors M 33 , M 34 constitute a current mirror for a current flowing through the bipolar transistor M 31 , bipolar transistors M 35 , M 36 constitute a current mirror for a current flowing through the bipolar transistor M 32 , and bipolar transistors M 37 , M 38 constitute a current mirror for a current flowing through the bipolar transistor M 36 . A current source I 1 is connected to a resistor R 31 , and a base of the bipolar transistor M 31 is connected to a connection point between the resistor R 31 and the current source I 1 .

Incidentally, the PNP type can be used for the bipolar transistors M 31 , M 32 , M 37 , M 38 , and the NPN type can be used for the bipolar transistors M 33 , M 34 , M 35 , M 36 .

The capacitor voltage Vpeak is input to a base of the bipolar transistor M 31 via the resistor R 31 . When the input voltage Vin is input to a base of the bipolar transistor M 32 , the input voltage Vin is compared with a voltage obtained by subtracting a voltage corresponding to a voltage drop caused by the resistor R 31 from the capacitor voltage Vpeak. In a case where the input voltage Vin is smaller than the voltage obtained by subtracting a voltage corresponding to a voltage drop caused by the resistor R 31 from the capacitor voltage Vpeak, the bipolar transistor M 32 becomes on, thereby a current flows through the bipolar transistor M 32 . When a current flows through the bipolar transistor M 32 , a current flows through the bipolar transistor M 36 due to the current mirror operation of the bipolar transistors M 35 , M 36 . When a current flows through the bipolar transistor M 36 , a current flows through the bipolar transistor M 38 due to the current mirror operation of the bipolar transistors M 37 , M 38 . When a current flows through the bipolar transistor M 38 , the bipolar transistors M 31 , M 32 operate in such a manner that the input voltage Vin becomes equal to the voltage obtained by subtracting a voltage corresponding to a voltage drop caused by the resistor R 31 from the capacitor voltage Vpeak, thereby Level L of the input voltage Vin is clipped so that the amplitude of the input voltage Vin comes constant.

On the other hand, in a case where the input voltage Vin is larger than a voltage obtained by subtracting a voltage corresponding to a voltage drop caused by the resistor R 31 from the capacitor voltage Vpeak, the bipolar transistor M 31 becomes off, thereby a current flowing through the bipolar transistor M 38 is cut off and the input voltage Vin is output as it is.

Twelfth Embodiment

FIG. 25 is a block diagram showing a schematic configuration of a comparator circuit to which a charge/discharge circuit of a twelfth embodiment is applied.

In FIG. 25 , this comparator circuit is provided with a charge/discharge circuit 121 in place of the charge/discharge circuit 21 of FIG. 17 , and the charge/discharge circuit 121 is provided with a clipping circuit 122 , a peak hold circuit 123 , a charge/discharge section 124 , and an AM threshold variable circuit 125 . The charge/discharge section 124 can charge/discharge a capacitor C 2 on the basis of a driving voltage or a driving current generated according to results of a comparison between an input signal input to the charge/discharge section 124 and the reference voltage Vref. The peak hold circuit 123 can detect a peak value of the input signal input to the charge/discharge section 124 and is connected to the capacitor C 1 that holds the peak value of the input signal. The clipping circuit 122 can clip a level lower than a given value, from the peak value of the input signal input to the charge/discharge section 124 . The AM threshold variable circuit 125 can change the clipping level of the clipping circuit 122 on the basis of a peak value of an input signal detected by the peak hold circuit 123 .

FIG. 26 is a diagram showing an example of the clipping level variable characteristics of the charge/discharge circuit by the AM threshold variable circuit 125 shown in FIG. 25 .

In FIG. 26 , the AM threshold variable circuit 125 can change the clipping level so that the signal amplitude increases with increasing peak value of an input signal.

When an FSK signal is received by the antenna 11 of FIG. 15 , the switch 25 is changed over to the FM detector 16 side. After the removal of unnecessary high-frequency components in the low-pass filter 26 , the FSK signal demodulated by the FM detector 16 is input to one input terminal of the comparator 27 via the resistor R 1 and is input to the charge/discharge section 124 . In the charge/discharge section 124 , a comparison is made between the FSK signal and the reference voltage Vref, and a driving voltage or a driving current corresponding to results of the comparison is generated. The charge/discharge section 124 performs the charging/discharging of the capacitor C 2 using the driving voltage or the driving current, thereby the charge/discharge section 124 causes a reference voltage Vref in which the FSK signal is smoothed to be generated in the capacitor C 2 .

The reference voltage Vref generated in the capacitor C 2 is input to the other input terminal of the comparator 27 and compared with the FSK signal input via the resistor R 1 , thereby binarized data is generated.

On the other hand, when an ASK signal is received by the antenna 11 , the switch 25 is changed over to the clipping circuit 122 side. After the removal of unnecessary high-frequency components in the low-pass filter 26 , the ASK signal output via the clipping circuit 122 is input to one input terminal of the comparator 27 via the resistor R 1 and is input to the peak hold circuit 123 and the charge/discharge section 124 .

When the ASK signal is input to the peak hold circuit 123 , a peak value of the ASK signal is detected and output to the clipping circuit 122 and the AM threshold variable circuit 125 . The AM threshold variable circuit 125 adjusts the clipping level of the clipping circuit 122 on the basis of the peak value of the ASK signal and adjusts the level of the ASK signal input to the charge/discharge section 124 .

Signals lower than the clipping level are clipped from the peak value of the ASK signal in the clipping circuit 122 , thereby the amplitude of the ASK signal is equalized, and the ASK signal is input to the charge/discharge section 124 of the low-pass filter 26 .

After the adjustment of the input level of the ASK signal in the charge/discharge section 124 , a comparison with the reference voltage Vref is made, and a driving voltage or a driving current corresponding to results of the comparison is generated. The charge/discharge section 124 performs the charging/discharging of the capacitor C 2 using the driving voltage or the driving current, thereby the charge/discharge section 124 causes a reference voltage Vref in which the ASK signal is smoothed to be generated in the capacitor C 2 .

The reference voltage Vref generated in the capacitor C 2 is input to the other input terminal of the comparator 27 and compared with the ASK signal input via the resistor R 1 , thereby binarized data is generated.

FIG. 27-1 is a diagram showing the RSSI waveform during a weak input after clipping in the charge/discharge circuit of FIG. 25 . FIG. 27-2 is a diagram showing the RSSI waveform during a strong input after clipping in the charge/discharge circuit of FIG. 25 .

As shown in FIG. 27-1 , it is possible to ensure the amplitude of an input signal input to the charge/discharge section 124 by reducing the clipping level when the receiving level of an ASK signal is small, and when the receiving level of an ASK signal is large, it is possible to efficiently remove noise while permitting the enlargement of the amplitude of an input signal input to the charge/discharge section 124 by enlarging the clipping level.

Thirteenth Embodiment

FIG. 28-1 is a circuit diagram showing a schematic configuration of a charge/discharge section which is applied to a charge/discharge circuit of a thirteenth embodiment.

In FIG. 28-1 , the comparator circuit of FIG. 25 is provided with a charge/discharge section 124 a as the charge/discharge section 124 . In the charge/discharge section 124 a , a non-inverting input terminal of an operational amplifier 51 is connected to a positive side terminal of a variable voltage source VR 51 , and an inverting input terminal of the operational amplifier 51 is connected to an anode terminal of a diode D 51 and the capacitor C 2 , and an output terminal of the operation amplifier 51 is connected to a cathode terminal of the diode D 51 . A non-inverting terminal of an operational amplifier 52 is connected to a negative side terminal of a variable voltage source VR 52 , an inverting input terminal of the operational amplifier 52 is connected to a cathode terminal of a diode D 52 and the capacitor C 2 , and an output terminal of the operational amplifier 51 is connected to an anode terminal of the diode D 52 . The negative side terminal of the variable voltage source VR 51 and the positive side terminal of the variable voltage source VR 52 are connected to a connection point between resistors R 1 and R 2 .

After being raised by a voltage corresponding to a voltage change caused by the variable voltage source VR 51 , the input voltage Vin is input to the non-inverting terminal of the operational amplifier 51 and lowered by a voltage corresponding to a voltage change caused by the variable voltage source VR 52 . After that, the input voltage Vin is input to the non-inverting terminal of the operational amplifier 52 . In the operational amplifier 51 , a value obtained after raising the input voltage Vin by a voltage change caused by the variable voltage source VR 51 is compared with the reference voltage Vref. When the value obtained after raising the input voltage Vin by a voltage change caused by the variable voltage source VR 51 is smaller than the reference voltage Vref, the voltage output of the operational amplifier 51 is adjusted and a current is caused to flow from the capacitor C 2 via the diode D 51 , thereby the reference voltage Vref is caused to drop.

On the other hand, in the operational amplifier 52 , a value obtained after lowering the input voltage Vin by a voltage change caused by the variable voltage source VR 52 is compared with the reference voltage Vref. When the value obtained after lowering the input voltage Vin by a voltage change caused by the variable voltage source VR 52 is larger than the reference voltage Vref, the voltage output of the operational amplifier 52 is adjusted and a current is caused to flow into the capacitor C 2 via the diode D 52 , thereby the reference voltage Vref is caused to rise.

When the AM threshold variable circuit 125 of FIG. 25 changes the clipping level of the clipping circuit 122 , the AM threshold variable circuit 125 changes the voltage of the variable voltage sources VR 51 , VR 52 according to a change in the clipping level, and can change the level of the input voltage Vin in this manner.

Fourteenth Embodiment

FIG. 28-2 is a circuit diagram showing a schematic configuration of a charge/discharge section which is applied to a charge/discharge circuit of a fourteenth embodiment.

In FIG. 28-2 , the comparator circuit of FIG. 25 is provided with a charge/discharge section 124 b as the charge/discharge section 124 . The charge/discharge section 124 b is provided with current supply circuits I 51 , I 52 in place of the diodes D 51 , D 52 , respectively, of FIG. 28-1 .

After being raised by a voltage corresponding to a voltage change caused by the variable voltage source VR 51 , the input voltage Vin is input to the non-inverting terminal of the operational amplifier 51 and lowered by a voltage corresponding to a voltage change caused by the variable voltage source VR 52 . After that, the input voltage Vin is input to the non-inverting terminal of the operational amplifier 52 . In the operational amplifier 51 , a value obtained after raising the input voltage Vin by a voltage change caused by the variable voltage source VR 51 is compared with the reference voltage Vref. When the value obtained after raising the input voltage Vin by a voltage change caused by the variable voltage source VR 51 is smaller than the reference voltage Vref, the current output of the operational amplifier 51 is adjusted and a current is caused to flow from the capacitor C 2 via the current supply circuit I 51 , thereby the reference voltage Vref is caused to drop.

On the other hand, in the operational amplifier 52 , a value obtained after lowering the input voltage Vin by a voltage change caused by the variable voltage source VR 52 is compared with the reference voltage Vref. When the value obtained after lowering the input voltage Vin by a voltage change caused by the variable voltage source VR 52 is larger than the reference voltage Vref, the current output of the operational amplifier 52 is adjusted and a current is caused to flow into the capacitor C 2 via the current supply circuit I 52 , thereby the reference voltage Vref is caused to rise.

Fifteenth Embodiment

FIG. 29 is a circuit diagram showing a schematic configuration of a charge/discharge section which is applied to a charge/discharge circuit of a fifteenth embodiment.

In FIG. 29 , bipolar transistors M 61 , M 62 constitute a differential amplifier, and a current source I 61 is connected to collectors of the bipolar transistors M 61 , M 62 as a common current source Bipolar transistors M 63 , M 64 constitute a current mirror for a current flowing through the bipolar transistor M 62 , and bipolar transistors M 65 , M 66 constitute a current mirror for a current flowing through the bipolar transistor M 61 .

Bipolar transistors M 71 , M 72 constitute a differential amplifier, and a current source I 71 is connected to collectors of the bipolar transistors M 71 , M 72 as a common current source. Bipolar transistors M 73 , M 74 constitute a current mirror for a current flowing through the bipolar transistor M 71 , bipolar transistors M 75 , M 76 constitute a current mirror for a current flowing through the bipolar transistor M 72 , and bipolar transistors M 77 , M 78 constitute a current mirror for a current flowing through the bipolar transistor M 76 .

A current source I 2 , resistors R 61 , R 71 and a current source I 3 are sequentially connected in series, a base of the bipolar transistor M 61 is connected to a connection point between the current source I 2 and the resistor R 61 , and a base of the bipolar transistor M 71 is connected to a connection point between the current source I 3 and the resistor 71 .

Incidentally, the PNP type can be used for the bipolar transistors M 61 , M 62 , M 71 , M 72 , M 77 , M 78 and the NPN type can be used for the bipolar transistors M 63 , M 64 , M 65 , M 66 , M 73 , M 74 , M 75 , M 76 .

When the input voltage Vin is input to bases of the bipolar transistors M 61 , M 71 via the resistors R 61 , R 71 , respectively, a voltage caused to rise from the input voltage Vin by a voltage corresponding to a voltage drop caused by the resistors R 61 is input to the base of the bipolar resistor M 61 , and a voltage caused to drop from the input voltage Vin by a voltage corresponding to a voltage drop caused by the resistors R 71 is input to the base of the bipolar resistor M 71 . The reference voltage Vref is input to bases of the bipolar transistors M 62 , M 72 .

When a voltage caused to rise from the input voltage Vin by a voltage corresponding to a voltage drop caused by the resistors R 61 is input to the base of the bipolar resistor M 61 , this voltage is compared with the reference voltage Vref in the bipolar transistors M 61 , M 62 . When the voltage caused to rise from the input voltage Vin by a voltage corresponding to a voltage drop caused by the resistors R 61 is smaller than the reference voltage Vref, the bipolar transistor M 61 becomes on, thereby a current flows through the bipolar transistor M 61 . When a current flows through the bipolar transistor M 61 , a current flows through the bipolar transistor M 66 by the current mirror operation of the bipolar transistors M 65 , M 66 . When a current flows through the bipolar transistor M 66 , a current is drawn form the capacitor C 2 of FIG. 25 and this causes the reference voltage Vref to drop.

On the other hand, when a voltage caused to drop from the input voltage Vin by a voltage corresponding to a voltage drop caused by the resistors R 71 is input to the base of the bipolar resistor M 71 , this voltage is compared with the reference voltage Vref in the bipolar transistors M 71 , M 72 . When the voltage caused to drop from the input voltage Vin by a voltage corresponding to a voltage drop caused by the resistors R 71 is larger than the reference voltage Vref, the bipolar transistor M 72 becomes on, thereby a current flows through the bipolar transistor M 72 . When a current flows through the bipolar transistor M 72 , a current flows through the bipolar transistor M 76 by the current mirror operation of the bipolar transistors M 75 , M 76 . When a current flows through the bipolar transistor M 76 , a current flows through the bipolar transistor M 78 by the current mirror operation of the bipolar transistors M 77 , M 78 . When a current flows through the bipolar transistor M 78 , a current is supplied to the capacitor C 2 of FIG. 25 and this causes the reference voltage to rise.

When the AM threshold variable circuit 125 of FIG. 25 changes the clipping level of the clipping circuit 122 , the AM threshold variable circuit 125 changes the currents of the current sources I 2 , I 3 respectively according to a change in the clipping level, thereby the threshold variable circuit 125 changes voltages corresponding to voltage drops caused by the resistors R 61 , R 71 and can change the level of the input voltage Vin in this manner.

Sixteenth Embodiment

FIG. 30 is a circuit diagram showing a schematic configuration of a threshold variable circuit which is applied to a charge/discharge circuit of a sixteenth embodiment.

In FIG. 30 , bipolar transistors M 81 , M 82 constitute a differential amplifier, a current source Ia is connected to a collector of the bipolar transistor M 81 , and a current source Ib is connected to a collector of the bipolar transistor M 82 . A resistor R 81 is connected to between the collectors of the bipolar transistors M 81 , M 82 .

Bipolar transistors M 83 , M 84 constitute a current mirror for a current flowing through the bipolar transistor M 81 , bipolar transistors M 85 , M 86 constitute a current mirror for a current flowing through the bipolar transistor M 82 , bipolar transistors M 90 to M 92 constitute a current mirror for a current flowing through the bipolar transistor M 86 , and bipolar transistors M 87 to M 89 constitute a current mirror for a current flowing through the bipolar transistor M 91 .

A voltage source Vinb is connected to a base of the bipolar transistor M 82 , and a current source Ic is connected to a collector of the bipolar transistor M 90 . A collector terminal of the bipolar transistor M 89 can be used as the current source I 1 of FIG. 24 , a collector terminal of the bipolar transistor M 92 can be used as the current source I 2 of FIG. 29 , and a collector terminal of the bipolar transistor M 88 can be used as the current source I 3 of FIG. 29 .

Incidentally, the PNP type can be used for the bipolar transistors M 81 , M 82 , M 90 to M 92 , and the NPN type can be used for the bipolar transistors M 83 to M 89 .

When the input voltage Vina is input to a base of the bipolar transistor M 81 , the input voltage Vina is compared with the voltage of the voltage source Vinb. Incidentally, the output of the peak hold circuit 123 of FIG. 25 can be used as the input voltage Vina. When the input voltage Vina is larger than the voltage of the voltage source Vinb, the bipolar transistor M 82 becomes on, thereby a current flows through the bipolar transistor M 82 . When a current flows through the bipolar transistor M 82 , a current flows through the bipolar transistor M 86 by the current mirror operation of the bipolar transistors M 85 , M 86 . When a current flows through the bipolar transistor M 86 , a current flows through the bipolar transistors M 91 , M 92 by the current mirror operation of the bipolar transistors M 90 to M 92 . When a current flows through the bipolar transistor M 91 , a current flows through the bipolar transistors M 88 , M 89 by the current mirror operation of the bipolar transistors M 87 to M 89 .

When a current flows through the bipolar transistor M 89 , a current flows through the current source I 1 of FIG. 24 and a voltage drop by the resistor R 31 increases, thereby the clipping level lowers and it is possible to increase the amplitude of the input voltage Vin.

When a current flows through the bipolar transistor M 92 , a current flows through the current source I 2 of FIG. 29 and the voltage drop by the resistor R 61 increases, thereby it is possible to lower the level of the input voltage Vin when a current is drawn from the capacitor C 2 of FIG. 25 .

When a current flows through the bipolar transistor M 88 , a current flows through the current source I 3 of FIG. 29 and the voltage drop by the resistor R 71 increases, thereby it is possible to raise the level of the input voltage Vin when a current is caused to flow into the capacitor C 2 of FIG. 25 .

Seventeenth Embodiment

FIG. 31 is a block diagram showing a schematic configuration of a comparator circuit to which a charge/discharge circuit of a seventeenth embodiment is applied.

In FIG. 31 , this comparator circuit is provided with a charge/discharge section 224 and an FM threshold variable circuit 225 in place of the charge/discharge section 124 and the AM threshold variable circuit 125 . The charge/discharge section 224 can charge/discharge the capacitor C 2 on the basis of a driving voltage or a driving current generated according to results of a comparison between an input signal input to the charge/discharge section 224 and the reference voltage Vref. The FM threshold variable circuit 225 can change a threshold that causes the charge/discharge section 224 to start the charging/discharging of the capacitor C 2 .

When an FSK signal is received by the antenna 11 of FIG. 15 , a switch 25 is changed over to the FM detector 16 side. After the removal of unnecessary high-frequency components in the low-pass filter 26 , an FSK signal demodulated in the FM detector 16 is input to one input terminal of a comparator 27 via a resistor R 1 and input to the charge/discharge section 224 . In the charge/discharge section 224 , an amount corresponding to a threshold set in the FM threshold variable circuit 225 is added to an FSK signal or deducted from the FSK signal, and a comparison is made between an FSK signal to which the amount corresponding to a threshold is added or from which the amount corresponding to a threshold is deducted and the reference voltage Vref, thereby a driving voltage or a driving current is generated according to results of the comparison. The charge/discharge section 224 performs the charging/discharging of the capacitor C 2 using the driving voltage or the driving current, thereby charge/discharge section 224 causes the capacitor C 2 to generate a reference voltage Vref in which the FSK signal is smoothed.

The reference voltage Vref generated in the capacitor C 2 is input to the other input terminal of the comparator 27 and compared with the FSK signal input via the resistor R 1 , thereby binarized data is generated.

The above-described embodiments are all illustrative only, do not restrict the present invention, and may be modified within the technical scope of the present invention in various forms.