Voice coil motor control system and method

This claims the benefit of copending U.S. Provisional Patent Application No. 60/943,134, filed Jun. 11, 2007, which is hereby incorporated by reference herein in its entirety.

This disclosure relates to a system and method for controlling the speed of an electric motor, and more particularly to a system and method for controlling the speed of a voice coil motor that moves the head of a disk drive.

In the event of a disk drive power failure, it is typical to use reserve power to retract the read/write head to prevent it from striking and damaging the platter surface. This function is known as “emergency retract” and can be performed as “blind retract” or “velocity-controlled retract.” Velocity-controlled retract is preferable, because controlling the speed at which the voice coil motor (VCM) retracts the head prevents or at least minimizes damage to the head as a result of hitting the ramp stop too hard (if it is retracted too quickly). At the same time, the available power for performing the retract operation is limited, so a trade-off between velocity regulation and power consumption has to be made.

One known method for controlling the speed of the VCM uses pulse width modulation (PWM), applying power to the VCM in pulses to conserve power. The speed of the motor is controlled by the width or duration of the pulses. The speed may be determined by detecting the back-electromotive force (back-EMF, or BEMF) generated when current passes through the motor. Comparison of the actual speed, as represented by the actual BEMF, to a target speed, as represented by a target BEMF, can be used to control the pulse width. The BEMF profile may be divided into regions using an analog-to-digital converter (ADC), and decoded to the pulse width of the subsequent PWM drive.

In order to improve VCM speed control, it is desirable to increase the number of regions into which the BEMF profile is divided to provide finer adjustment of the pulse width. However, using a higher-resolution ADC during an emergency retract consumes more power at a time when power is at a premium. In addition, it may be desirable to make the pulse width programmable to accommodate different models of disk drive, or even differences among drives of the same model.

Instead of using a high-resolution ADC to provide finer control of the pulse width used to control the speed of the VCM, analog voltage-to-time conversion may be used. If an analog signal is provided, the need for a digital speed decoder to allow a digital control signal to control the motor speed also may be eliminated. The direct analog method of voltage-to-time conversion may be implemented using a “constant-current-charging-capacitor” configuration where the time needed to charge the capacitor is directly related to how far the actual motor speed is from the target speed. Although the invention will be described hereafter in terms of the constant-current-charging-capacitor configuration, it may be possible to implement the invention with other configurations of analog electrical energy storage elements.

In accordance with embodiments of the invention, the BEMF voltage (V BEMF ), which is indicative of motor speed, is sampled, and then stored in a storage capacitor (C BEMF ). The C BEMF storage capacitor is then allowed to charge or discharge, as the case may be, to a target voltage level (BEMF THRES ). The C BEMF storage capacitor exhibits a linear voltage/time relationship, meaning that the time duration required to charge or discharge the capacitor to the target voltage level is directly proportional to the difference between the BEMF voltage (V BEMF ) and the target voltage. Therefore, that time duration may be used to derive the pulse width (i.e., the charging time) in the PWM velocity control system. The derivation may be a simple arithmetic manipulation, such as multiplying or dividing the duration by an integer, and indeed the duration may be used directly as the pulse width.

As the detected BEMF voltage V BEMF approaches the target voltage BEMF THRES , the pulse width/charging time (T c ) gradually decreases. This is consistent with the motor speed requirements—as the speed (reflected by V BEMF ) approaches the target speed (reflected by BEMF THRES ) the required acceleration to be applied by the PWM velocity control system also decreases.

Once the target speed has been achieved (as indicated by V BEMF being at or near BEMF THRES ), the PWM velocity control system may enter a TRISTATE state. The TRISTATE state may be maintained as long as V BEMF remains within a target range of BEMF THRES . In such a case, the system will continue to monitor V BEMF and will return to the charging state if V BEMF goes out of the target range.

In cases where the system configuration is such that longer pulse widths are required, a larger capacitor may be needed to provide the longer charging times corresponding to the longer pulse widths. As an alternative, a pulse multiplier circuit can be added to the analog voltage-to-time converter of an embodiment of the invention. The pulse multiplier circuit, if provided, allows charging/discharging of the sampled V BEMF to the target BEMF THRES to be repeated by a number, N, of times for each sampled V BEMF , instead of increasing the pulse width. An additional buffer may be included in this embodiment to store the V BEMF value to allow repetition of the charging/discharging cycle. Because the capacitance of a capacitor is directly proportional to its area, use of the pulse multiplier circuit to multiply the number of pulses by N also decreases by a factor of N the area of the capacitor needed for the motor speed control circuit. This can be important in integrated circuit embodiments where die area may be at a premium.

Therefore, in accordance with embodiments of the present invention, there is provided a method for deriving control pulse width for pulse width modulation motor speed control. The method includes sampling back-EMF in a motor to be controlled, charging an analog electrical energy storage element to the sampled back-EMF, comparing the sampled back-EMF as stored on the analog electrical energy storage element to a target back-EMF, applying current to bring the back-EMF as stored on the analog electrical energy storage element to the target back-EMF, and setting the pulse width based on time required to bring the back-EMF as stored on the analog electrical energy storage element to the target back-EMF.

Apparatus for carrying out the method is also provided.

Further features of the invention, its nature and various advantages, will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 is a schematic diagram of a first embodiment of a pulse width modulation velocity control circuit for a voice coil motor;

FIG. 2 is a flow chart showing the operation of the circuit of FIG. 1 ;

FIG. 3 shows representative signal waveforms during operation of the circuit of FIG. 1 ;

FIG. 4 is a schematic diagram of a first embodiment of a pulse width modulation velocity control circuit for a voice coil motor, including an embodiment of a pulse multiplier circuit;

FIG. 5 shows representative signal waveforms during operation of the circuit of FIG. 4 ;

FIG. 6 is a block diagram of an exemplary hard disk drive that can employ the disclosed technology; and

FIG. 7 is a block diagram of an exemplary digital versatile disk drive that can employ the disclosed technology;

FIG. 8 is a block diagram of an exemplary high definition television that can employ the disclosed technology;

FIG. 9 is a block diagram of an exemplary vehicle that can employ the disclosed technology;

FIG. 10 is a block diagram of an exemplary cellular telephone that can employ the disclosed technology;

FIG. 11 is a block diagram of an exemplary set top box that can employ the disclosed technology; and

FIG. 12 is a block diagram of an exemplary media player that can employ the disclosed technology.

As discussed above, analog voltage-to-time conversion may used to obtain fine control of VCM speed without the need for a high-resolution ADC or a digital speed decoder. The direct analog voltage-to-time conversion may be implemented using a “constant-current-charging-capacitor” configuration where the time needed to charge the capacitor (C BEMF ) is directly related to the BEMF detected. As the detected BEMF approaches a predetermined threshold (BEMF THRES ), the pulse width/charging time (T c ) gradually becomes smaller. Assuming a constant current, this voltage and time relationship may be expressed as follows:

In the pulse width modulation velocity control circuit 100 of FIG. 1 , BEMF extraction circuitry 101 outputs at 102 V BEMF captured from motor 10 and level shifted to V REF to satisfy the common mode input range of the circuit. V REF normally is chosen at the middle point between supply and ground voltages.

Sample-and-hold circuitry 110 of circuitry 100 samples V BEMF by closing sampling switch 111 at the beginning of the retract sequence and periodically thereafter when in the tristate period, after the motor current decays to zero, which holds V BEMF on C BEMF capacitor 112 . The circuit will continue to cycle though the charge, discharge and tristate phases as long as V BEMF is out of the target velocity band. If the motor is within the target velocity band, as indicasted by V BEMF then the circuit will stay in the tristate phase.

T c , the duration of the charging phase, is determined in voltage-to-time converter circuitry 120 as follows. If the magnitude of the sampled voltage, as determined prior to the charging phase, is less than BEMF THRES , then SRC switch 121 is closed throughout the charging phase so that current is sourced from I SRC current source 122 to charge capacitor 112 . If the magnitude of the sampled voltage is greater than BEMF THRES , then SNK switch 123 is closed throughout the charging phase so that current is sunk to I SINK current sink 124 to discharge capacitor 112 . During the charging phase, comparator 125 compares the voltage on capacitor 112 to BEMF THRES . When comparator 125 trips, TC_END signal—output by multiplexer 126 , which is controlled by the value of SRC so that it goes high when comparator 125 changes state—goes high, ending the charging phase.

As shown in FIG. 2 , circuit 100 functions like a state machine 200 with four states—namely STANDBY, TRISTATE, CHARGE and DISCHARGE. The system remains in STANDBY (state 201 ) until the velocity-controlled retract process is activated (test 202 ), whereupon the system cycles through the TRISTATE, CHARGE and DISCHARGE states 203 , 208 , 210 in a sequential manner to perform the retract function.

Specifically, the system starts the retract process in TRISTATE state 203 and remains there until a predetermined waiting period has elapsed (test 204 ). The waiting period is user programmable based on the time constant of the motor, to allow for the motor current to settle properly before sampling of the back-EMF. After the waiting period has elapsed, the system determines whether the retract process has been completed (velocity control disable test 205 ) and if so returns to STANDBY state 201 . Otherwise, the system tests at 206 whether the target speed has been achieved (as represented by BEMF THRES ). If so, the system returns to TRISTATE state 203 .

If, at test 206 , it is determined that the target speed has not been achieved, then at test 207 the system determines whether the speed is too fast (speed too fast?=YES, meaning |V BEMF |>|BEMF THRES |) or too slow (speed too fast?=NO, meaning |V BEMF |<|BEMF THRES |). If the speed is too fast, the system sets SRC=0 and SNK=1 and enters CHARGE state 208 . If the speed is too slow, the system sets SRC=1 and SNK=0 and enters CHARGE state 208 .

The system remains in CHARGE state 208 until T c has elapsed as determined (test 209 ) by TC_END signal 126 . The system then enters discharge state 210 where it remains until it detects a TD_END signal (test 211 ), whereupon it returns to TRISTATE state 203 . The TD_END signal may be generated by a zero-current-sensing comparator (not shown) such as the one described in copending, commonly-assigned U.S. patent application Ser. No. 11/871,110, filed Oct. 11, 2007. The system will remain in TRISTATE state 203 as long as the target speed is maintained.

FIG. 3 shows the control signals and output signal waveforms of an embodiment of the pulse width modulation velocity control circuit 100 . Signal 300 represents the state of the system—STANDBY (STDBY), TRISTATE (TRI), CHARGING (C) and DISCHARGING (D). Signal 301 is an enable signal representing the outcome of test 202 (above), which is low in the STANDBY state and otherwise high. Signal 302 is a sample signal, which goes high after the programmed predetermined waiting period has elapsed (test 204 ) from entry into the TRISTATE state. Signal 302 stays high for a minimum duration, but can remain high as long as V BEMF signal 303 as measured on capacitor 112 remains within a target range of BEMF THRES level 304 , as indicated by FWD and REV threshold levels 305 , 306 .

As can be seen at points 310 , 311 , if the sampled V BEMF signal 303 as measured on capacitor 112 is below BEMF THRES level 304 , then a charging period is entered during which a positive current I MOTOR 307 is developed until TC_END signal 308 goes high, whereupon a discharge period is entered during which the motor current I MOTOR 307 is discharged until TD_END signal 309 goes high, based on detection of I MOTOR 307 returning to zero.

As shown in the drawing, charging period TC 2 , beginning at point 311 is shorter than charging period TC 1 , beginning at point 310 , because the detected value of V BEMF signal 303 at point 311 is closer to BEMF THRES than the detected value of V BEMF signal 303 at point 310 .

Charging period TC 3 is even shorter than either period TC 1 or TC 2 as the BEMF detected is even closer to BEMF THRES . However, during period TC 3 , V BEMF is discharged down, rather than charged up, because the detected V BEMF , while closer to BEMF THRES , is higher than BEMF THRES rather than lower than BEMF THRES .

As seen from the extended TRISTATE period between periods TC 2 and TC 3 , the TRISTATE state can be prolonged indefinitely as long as the detected V BEMF remains within the BEMF target range.

FIG. 4 shows a pulse width modulation velocity control circuit 400 , similar to circuit 100 (BEMF extraction circuitry not shown), but modified with pulse multiplier circuitry to provide a plurality of capacitor charging/discharging cycles to minimize the size of the required capacitor as discussed above.

In circuit 400 , sample-and-hold circuitry 410 includes switch 111 and capacitor 112 as in sample-and-hold circuitry 110 . However, unlike in sample-and-hold circuitry 110 , in sample-and-hold circuitry 410 , sample signal 113 is passed on as well to voltage-to-time converter circuitry 420 . In voltage-to-time converter circuitry 420 , the detected V BEMF on capacitor 112 is stored in buffer 421 , which is sampled by C MULTIPLIER capacitor 422 , which takes over the role of C BEMF capacitor 112 in determining the pulse width/charging time (T c ). Comparator 125 , source 122 and sink 124 operate as they do in FIG. 1 , except that they operate on the voltage stored on capacitor 422 instead of the voltage on capacitor 112 . However, when comparator 125 trips in this case and multiplexer 126 goes high, instead of triggering a TC_END signal, a rising edge counter 423 increments and does not output a high TC_END until the count reaches a preset value N. The tripping of comparator 125 also triggers pulse generator 424 to output SWI_RESET pulse 423 which, through OR-gate 425 , closes switch 426 which reads out the voltage in buffer 421 onto capacitor 422 (this switch also is closed, along with switch 111 , by SAMPLE signal 113 ).

Thus, circuit 400 does not output a high TC_END until comparator 125 has been tripped N times. This is equivalent to increasing the capacitance of capacitor 112 of circuit 100 by a factor of N. Circuit 400 therefore saves that additional area. Because additional capacitor 422 , as well as additional elements 423 , 424 , 425 and 426 are necessary, there may be no net savings unless N≧3.

The case of N=3 is shown in FIG. 5 . This case is similar to FIG. 3 , except that while each SWI_RESET pulse 501 resets the voltage 503 on capacitor 422 , because TC_END is not asserted until N SWI_RESET pulses occur, I MOTOR continues to increase (in TC 1 and TC 2 ) or decrease (in TC 3 ) after each SWI_RESET pulse, until the Nth SWI_RESET pulse when TC_END also is asserted. As discussed above, this allows wider pulses without increasing the size of capacitor 112 , or alternatively allows pulses of the same width with reduced capacitor size.

It will be appreciated that V REF , BEMF THRES , and the FWD and REV threshold levels (in all embodiments), as well as the value of N (in an embodiment such as that of FIGS. 4 and 5 ), may be treated as parameters and selected to account for characteristics of the VCM being controlled. These parameters ordinarily would not be changeable “on the fly” or in the field by an end user, but may be changeable at the time of disk drive assembly to account for characteristics of the particular disk drive model, or even of the individual drive.

Thus it is seen that a method and apparatus for controlling voice coil motor speed more accurately has been provided.

Referring now to FIGS. 6-12 , exemplary implementations of embodiments of the present invention are shown.

Referring now to FIG. 6 , an embodiment of the present invention can be implemented in a hard disk drive 600 . The present invention may be implement in signal processing and/or control circuits, which are generally identified in FIG. 6 at 602 . In some implementations, the signal processing and/or control circuit 602 and/or other circuits (not shown) in the HDD 600 may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a magnetic storage medium 606 .

The HDD 600 may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular telephones, media or MP3 players and the like, and/or other devices, via one or more wired or wireless communication links 608 . The HDD 600 may be connected to memory 609 such as random access memory (RAM), low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.

Referring now to FIG. 7 , an embodiment of the present invention can be implemented in a digital versatile disk (DVD) drive 700 . The present invention may be implemented in either or both signal processing and/or control circuits, which are generally identified in FIG. 7 at 702 , and/or mass data storage of the DVD drive 700 . The signal processing and/or control circuit 702 and/or other circuits (not shown) in the DVD drive 700 may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium 706 . In some implementations, the signal processing and/or control circuit 702 and/or other circuits (not shown) in the DVD drive 700 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.

DVD drive 700 may communicate with an output device (not shown) such as a computer, television or other device, via one or more wired or wireless communication links 707 . The DVD drive 700 may communicate with mass data storage 708 that stores data in a nonvolatile manner. The mass data storage 708 may include a hard disk drive (HDD). The HDD may have the configuration shown in FIG. 6 . The HDD may be a mini-HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The DVD drive 700 may be connected to memory 709 such as RAM, ROM, low-latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.

Referring now to FIG. 8 , an embodiment of the present invention can be implemented in a high definition television (HDTV) 800 . The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 8 at 822 , a WLAN interface and/or mass data storage of the HDTV 800 . The HDTV 800 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 826 . In some implementations, signal processing circuit and/or control circuit 822 and/or other circuits (not shown) of the HDTV 800 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

The HDTV 800 may communicate with mass data storage 827 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in FIG. 76 and/or at least one DVD drive may have the configuration shown in FIG. 7 . The HDD may be a mini-HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The HDTV 800 may be connected to memory 828 such as RAM, ROM, low-latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The HDTV 800 also may support connections with a WLAN via a WLAN network interface 829 .

Referring now to FIG. 9 , an embodiment of the present invention implements a control system of a vehicle 900 , a WLAN interface and/or mass data storage of the vehicle control system. In some implementations, the present invention may implement a powertrain control system 932 that receives inputs from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals.

An embodiment of the present invention may also be implemented in other control systems 940 of the vehicle 900 . The control system 940 may likewise receive signals from input sensors 942 and/or output control signals to one or more output devices 944 . In some implementations, the control system 940 may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated.

The powertrain control system 932 may communicate with mass data storage 946 that stores data in a nonvolatile manner. The mass data storage 946 may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 6 and/or at least one DVD drive may have the configuration shown in FIG. 7 . The HDD may be a mini-HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The powertrain control system 932 may be connected to memory 947 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The powertrain control system 932 also may support connections with a WLAN via a WLAN network interface 948 . The control system 940 may also include mass data storage, memory and/or a WLAN interface (none shown).

Referring now to FIG. 10 , an embodiment of the present invention can be implemented in a cellular telephone 1000 that may include a cellular antenna 1051 . The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 10 at 1052 , a WLAN interface and/or mass data storage of the cellular phone 1000 . In some implementations, the cellular telephone 1000 includes a microphone 1056 , an audio output 1058 such as a speaker and/or audio output jack, a display 1060 and/or an input device 1062 such as a keypad, pointing device, voice actuation and/or other input device. The signal processing and/or control circuits 1052 and/or other circuits (not shown) in the cellular telephone 1000 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular telephone functions.

The cellular telephone 1000 may communicate with mass data storage 1064 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices—for example hard disk drives (HDDs) and/or DVDs. At least one HDD may have the configuration shown in FIG. 6 and/or at least one DVD drive may have the configuration shown in FIG. 7 . The HDD may be a mini-HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. The cellular telephone 1000 may be connected to memory 1066 such as RAM, ROM, low-latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The cellular telephone 1000 also may support connections with a WLAN via a WLAN network interface 1068 .

Referring now to FIG. 11 , an embodiment of the present invention can be implemented in a set top box 1100 . The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 11 at 1184 , a WLAN interface and/or mass data storage of the set top box 1100 . Set top box 1100 receives signals from a source 1182 such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 1188 such as a television and/or monitor and/or other video and/or audio output devices. The signal processing and/or control circuits 1184 and/or other circuits (not shown) of the set top box 1100 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

Set top box 1100 may communicate with mass data storage 1190 that stores data in a nonvolatile manner. The mass data storage 1190 may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 6 and/or at least one DVD drive may have the configuration shown in FIG. 7 . The HDD may be a mini-HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. Set top box 1100 may be connected to memory 1194 such as RAM, ROM, low-latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. Set top box 1100 also may support connections with a WLAN via a WLAN network interface 1196 .

Referring now to FIG. 12 , an embodiment of the present invention can be implemented in a media player 1200 . The present invention may implement either or both signal processing and/or control circuits, which are generally identified in FIG. 12 at 1204 , a WLAN interface and/or mass data storage of the media player 1200 . In some implementations, the media player 1200 includes a display 1207 and/or a user input 1208 such as a keypad, touchpad and the like. In some implementations, the media player 1200 may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via the display 1207 and/or user input 1208 . Media player 1200 further includes an audio output 1209 such as a speaker and/or audio output jack. The signal processing and/or control circuits 1204 and/or other circuits (not shown) of media player 1200 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

Media player 1200 may communicate with mass data storage 1210 that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 6 and/or at least one DVD drive may have the configuration shown in FIG. 7 . The HDD may be a mini-HDD that includes one or more platters having a diameter that is smaller than approximately 1.8″. Media player 1200 may be connected to memory 1214 such as RAM, ROM, low-latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. Media player 1200 also may support connections with a WLAN via a WLAN network interface 1216 . Still other implementations in addition to those described above are contemplated.

It will be understood that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation.