High frequency circuit, semiconductor device, and high frequency power amplification device

1. Field of Invention

The present invention relates to technology for a high frequency circuit that is used in mobile communication devices, for example, and to a high frequency power amplification device that uses the high frequency circuit, and relates more particularly to a high frequency circuit, to a semiconductor device, and to a high frequency power amplification device.

2. Description of Related Art

High frequency power amplifiers used in cell phones, for example, have an amplification device such as a transistor, an input matching circuit for efficiently inputting high frequency signals to the amplification device, and an output matching circuit for efficiently outputting high frequency signals from the amplification device. The matching circuits are composed of capacitors, inductors, microstrip lines, or other high frequency matching device, and are usually mounted on a circuit board as a semiconductor chip package. A semiconductor chip containing the high frequency power amplification device is also mounted on the same circuit board, rendering a high frequency power amplifier module.

As cell phones have become more functional, demand for multiband cell phones capable of transmitting various different signals and multimode cell phones capable of handling different modulation signals has risen. As known from the literature, input and output impedance matching under various frequency, output, and other conditions is necessary in order to optimize the efficiency of the high frequency power amplifier. A plurality of high frequency power amplifiers each having a matching circuit with optimized impedance is required for multiband and multimode compatibility.

One possible solution is a high frequency power amplifier that has a plurality of output pins and switches for selecting the appropriate output as described in the literature.

FIG. 18 shows an example of the related art taught in U.S. Pat. No. 5,774,017 (corresponding to Japanese Laid-open Patent Publication No. 10-65466). A single-pole, double-throw (SPDT) switch 265 is disposed to the output of the last amplification device 246 . The output matching circuits 264 , 266 are designed for matching signals of the two different frequencies that are amplified by the amplifier 240 . The single-pole, double-throw switch 265 switches to pass the output of the amplification device 246 to the appropriate output matching circuit 264 , 266 .

FIG. 19 shows an example of the related art taught in Japanese Laid-open Patent Publication No. 2005-86738. A double-pole, double-throw (DPDT) switch 14 is connected to the outputs of the final amplification device 31 and the preceding amplification device. The output matching circuits 56 , 56 ′ are designed for matching signals of the two different frequencies that are amplified by the amplifier 50 . The double-pole, double-throw switch 14 can switch the two inputs to the appropriate output matching circuits 56 , 56 ′.

A problem with the related art thus described is that because a switching device must be connected before or after the final amplification stage, the switching device increases the output loss of the amplification device.

A first aspect of the invention is a multifunctional, compact, high performance high frequency circuit that reduces loss caused by a switching device disposed to the output side of the amplifier, enables easily switching the impedance and output path, and is multiband and multimode compatible.

A high frequency circuit according to a preferred aspect of the invention has a final stage amplification unit that power amplifies an input signal and outputs an amplified signal; a first matching circuit that impedance converts the amplified signal input thereto at a first input impedance, and outputs a first impedance-converted signal at a first output impedance; and a switch unit that switches passing the first impedance-converted signal on/off, and when on state passes the first impedance-converted signal at an on impedance and outputs the pass signal to an antenna.

Preferably, the high frequency circuit also has a control unit that generates a control signal denoting signal path selection information, and the switch unit selects one of at least two signal paths based on the control signal, and turns passing the first impedance-converted signal through the selected path on.

Further preferably, the high frequency circuit also has a second matching circuit that impedance converts a pass signal input thereto at a second input impedance, and outputs a second impedance-converted signal at a second output impedance to the antenna.

A semiconductor device according to another aspect of the invention includes at least a part of the first matching circuit and the first switch unit of the high frequency circuit described above on a first semiconductor chip.

Another aspect of the invention is a high frequency power amplification device having mounted on a single circuit board at least part of the first matching circuit and second matching circuit of the high frequency circuit described above, and the foregoing semiconductor device.

The high frequency circuit, semiconductor device, and high frequency power amplifier according to the present invention can reduce loss imposed by the switch unit by setting the output impedance of the matching circuit higher than the on impedance of the switch unit disposed downstream from the matching circuit. Furthermore, by using a switch unit from which loss is thus reduced, the input/output impedance of a matching circuit disposed downstream from the switch unit can be separately optimized for the frequency or power. Independently optimized matching circuits can therefore be appropriately applied in a multiband or multimode cell phone if the frequency band that is used changes or the communication mode changes. The matching circuit can therefore be reduced in size while transmission power efficiency and waveform precision are improved. Cell phone coverage can also be increased while power consumption is reduced. The invention thus affords a small, high performance, multifunctional high frequency circuit, semiconductor device, and high frequency power amplifier.

Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a high frequency circuit used to describe the principle of the invention.

FIG. 2 is a block diagram of a high frequency circuit according to a first embodiment of the invention.

FIG. 3 is a circuit diagram showing the switch unit in the first embodiment of the invention.

FIG. 4A describes the operation of the high frequency circuit according to the first embodiment of the invention.

FIG. 4B describes the operation of the high frequency circuit according to the first embodiment of the invention.

FIG. 4C describes the operation of the high frequency circuit according to the first embodiment of the invention.

FIG. 4D describes the operation of the high frequency circuit according to the first embodiment of the invention.

FIG. 5 is a block diagram of a high frequency circuit according to a second embodiment of the invention.

FIG. 6 is a circuit diagram showing an example of the matching circuit in a third embodiment of the invention.

FIG. 7A describes the operation of the high frequency circuit according to the third embodiment of the invention.

FIG. 7B describes the operation of the high frequency circuit according to the third embodiment of the invention.

FIG. 7C describes the operation of the high frequency circuit according to the third embodiment of the invention.

FIG. 8 is a circuit diagram showing an example of the matching circuit according to a fourth embodiment of the invention.

FIG. 9A describes the operation of the high frequency circuit according to the fourth embodiment of the invention.

FIG. 9B describes the operation of the high frequency circuit according to the fourth embodiment of the invention.

FIG. 10A is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 10B is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 10C is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 10D is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 10E is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 10F is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 10G is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 10H is a circuit diagram showing an example of the matching circuit according to the third and fourth embodiments of the invention.

FIG. 11 is a circuit diagram of a matching circuit according to a fifth embodiment of the invention.

FIG. 12A is a block diagram of a high frequency circuit according to the fifth embodiment of the invention.

FIG. 12B s a circuit diagram of a matching circuit according to a fifth embodiment of the invention.

FIG. 12C describes the operation of the high frequency circuit according to the fifth embodiment of the invention.

FIG. 12D describes the operation of the high frequency circuit according to the fifth embodiment of the invention.

FIG. 13A is a waveform diagram showing the operating signal of the high frequency circuit according to a sixth embodiment of the invention.

FIG. 13B is a waveform diagram showing the operating signal of the high frequency circuit according to a sixth embodiment of the invention.

FIG. 14A is a graph showing the operating characteristic of the high frequency circuit according to a sixth embodiment of the invention.

FIG. 14B is a graph showing the operating characteristic of the high frequency circuit according to a sixth embodiment of the invention.

FIG. 14C is a graph showing the operating characteristic of the high frequency circuit according to a sixth embodiment of the invention.

FIG. 15 is a block diagram of a high frequency circuit according to a seventh embodiment of the invention.

FIG. 16 is a circuit diagram of a high frequency circuit according to a ninth embodiment of the invention.

FIG. 17A describes the operation of the high frequency circuit according to a ninth embodiment of the invention.

FIG. 17B describes the operation of the high frequency circuit according to a ninth embodiment of the invention.

FIG. 18 is a block diagram of a high frequency power amplifier according to the related art.

FIG. 19 is a block diagram of a high frequency power amplifier according to the related art.

Preferred embodiments of the present invention are described below with reference to the accompanying figures. Note that parts with the same arrangement, operation, and effect are denoted by the same reference numerals in the accompanying figures. The numbers used below and in the figures are also merely to describe a specific embodiment of the invention, and the invention is not limited to the cited numbers. In addition, logic levels denoted high and low are also only used by way of example to describe a specific embodiment of the invention, and it will be obvious that the same effect can be achieved using different combinations of the exemplary logic levels. Furthermore, the connections between particular parts described below are also used to describe a specific embodiment of the invention, and the connections achieving the function of the invention are not limited to those described below. The following embodiments are also rendering using hardware and/or software elements, but the hardware arrangements described below can also be achieved using software, and the software constructions described below can also be achieved using hardware.

Operating Principle

The operating principle of the invention is described first below. FIG. 1 is a block diagram of a high frequency circuit used to describe the principle of the invention. The high frequency circuit used to describe this principle has an input pin 150 , final stage amplification unit 100 , matching circuit 102 , switch unit 101 , matching circuit 103 , output pin 151 , and control unit 170 .

The final stage amplification unit 100 is an amplifier circuit including the last amplification device that outputs to an antenna (not shown in the figure), for example. The final stage amplification unit 100 amplifies the power of the input signal S 150 input to the input pin 150 , and outputs the amplified signal S 100 at output impedance 160 . The output impedance 160 is normally less than 50Ω. If the output of the final stage amplification unit 100 is high, such as when a 1-W input is boosted to several watts as in a cell phone, the output impedance 160 is generally approximately 3 to 8Ω.

The amplified signal S 100 is input to the matching circuit 102 at an input impedance 161 substantially equal to a complex conjugate of the output impedance 160 . More specifically, the matching circuit 102 extracts the maximum power from the final stage amplification unit 100 by impedance matching the output impedance 160 . Similarly to the output impedance 160 , the input impedance 161 is typically 3-8Ω. The matching circuit 102 impedance converts the amplified signal S 100 , and outputs an impedance-converted signal S 102 at output impedance 162 .

The control unit 170 generates a control signal S 170 denoting signal path selection information applied to the switch unit 101 . The matching circuit 102 controls the output impedance 162 based on control signal S 170 . Also based on the control signal S 170 , the switch unit 101 switches the impedance-converted signal S 102 on/off, and passes and outputs the impedance-converted signal S 102 as pass signal S 101 at on impedance 163 if the switch is on.

The pass signal S 101 is input to the matching circuit 103 at an input impedance 164 substantially equal to a complex conjugate of a complex sum of the output impedance 162 and the on impedance 163 . That is, the matching circuit 103 extracts the maximum power from the matching circuit 102 by impedance matching the output impedance 162 and on impedance 163 . In addition, the matching circuit 103 impedance converts the pass signal S 101 and outputs impedance-converted signal S 103 to the output pin 151 at output impedance 165 , which is substantially equal to load impedance 166 . The load impedance 166 is the impedance of the load connected to the output pin 151 . For example, if the load impedance 166 is a pure resistance of 50Ω, there may be a 50-Ω antenna connected through a 50-Ω transmission path (not shown in the figure). More specifically, by impedance matching the load impedance 166 , the matching circuit 103 suppresses waveform distortion caused by reflection waves from the load while supplying the maximum power to the load. The switch unit 101 and matching circuits 102 and 103 constitute the load matching circuit 105 . The impedances are expressed as complex numbers of which the real part is the resistance component and the imaginary part is the reactance.

When a switch unit 101 is disposed to the output side of the final stage amplification unit 100 , signal loss by the switch unit 101 must be avoided. If the absolute value of the output impedance 162 of the matching circuit 102 is set higher than the absolute value of the on impedance 163 , the sum of the complex values of output impedance 162 and on impedance 163 is substantially equal to output impedance 162 . More particularly, the on impedance 163 is a level that can be ignored regardless of the phase, and signal loss by the switch unit 101 is reduced to a level that can be ignored.

For example, the on impedance 163 is typically approximately 1Ω, and the output impedance 162 is preferably set to 10Ω or greater and further preferably to several 10Ω. In this case the matching circuit 102 converts the typically 3-8Ω input impedance 161 to an output impedance 162 that is greater than the input impedance 161 , and reduces signal loss from the switch unit 101 . Because the input impedance 164 of the matching circuit 103 is substantially equal to a complex conjugate of the sum of complex numbers of the output impedance 162 and on impedance 163 , the absolute value of the input impedance 164 increases approximately equally to the absolute value of the output impedance 162 .

The output impedance 162 and the load impedance 166 are compared next. As described above, because the input impedance 164 is substantially equal to a complex conjugate of the output impedance 162 , their reactance components are mutually cancelled. As a result, the resistance component of the output impedance 162 is compared with the load impedance 166 , which is substantially composed of a resistance component. If the absolute value of the output impedance 162 is sufficiently greater than the absolute value of the on impedance 163 , the resistance component of the output impedance 162 can be greater or less than the load impedance 166 . If the resistance component of the output impedance 162 is substantially equal to the load impedance 166 , the matching circuit 103 can be omitted. If the resistance component of the output impedance 162 is different from the load impedance 166 , the matching circuit 103 impedance converts the input impedance 164 to an output impedance 165 substantially equal to the load impedance 166 . Note that the matching circuit 103 can also be omitted even when the resistance component of the output impedance 162 differs from the load impedance 166 if impedance matching to the load impedance 166 is not necessary.

By thus matching the output impedance 160 of the final stage amplification unit 100 at the input side, the load matching circuit 105 can extract maximum power from the final stage amplification unit 100 . Furthermore, by matching the 50-Ω load impedance 166 at the output side, the load matching circuit 105 can supply maximum power to the load and can suppress waveform distortion by wave reflection from the load. Yet further, by internally setting the absolute value of the output impedance 162 of the matching circuit 102 higher than the absolute value of the on impedance 163 of the switch unit 101 , the load matching circuit 105 can set the on impedance 163 to a relative level that can be ignored. More specifically, the matching circuit 102 sets the input impedance 161 relatively low to match the output impedance 160 of the final stage amplification unit 100 , and sets the output impedance 162 enough greater than the input impedance 161 that the on impedance 163 can be ignored. As a result, loss from the switch unit 101 can be reduced, waveform distortion can be suppressed, and maximum power can be supplied to the load when setting the switch unit 101 on the output side of the final stage amplification unit 100 .

FIG. 2 is a block diagram of a high frequency circuit according to a first embodiment of the invention. The high frequency circuit according to this first embodiment of the invention includes an input pin 150 , a final stage amplification unit 100 , a matching circuit 102 A, a switch unit 101 A, matching circuits 103 a and 103 b , output pins 151 a and 151 b , and a control unit 170 A.

The final stage amplification unit 100 amplifies the power of the input signal S 150 input to the input pin 150 , and outputs the amplified signal S 100 at output impedance 160 . The output impedance 160 is normally less than 50Ω. If the output of the final stage amplification unit 100 is high, such as when a 1-W input is boosted to several watts as in a cell phone, the output impedance 160 is generally approximately 3 to 8Ω.

The amplified signal S 100 is input to the matching circuit 102 A at an input impedance 161 substantially equal to a complex conjugate of the output impedance 160 . More specifically, the matching circuit 102 A extracts the maximum power from the final stage amplification unit 100 by impedance matching the output impedance 160 . Similarly to the output impedance 160 , the input impedance 161 is typically 3-8Ω. The matching circuit 102 A converts the impedance of the amplified signal S 100 , and outputs an impedance-converted signal S 102 at output impedance 162 .

The switch unit 101 A is a single-pole, double-throw switch. The control unit 170 A generates a control signal S 170 A denoting signal path selection information applied to the switch unit 101 A. The matching circuit 102 A controls the output impedance 162 based on control signal S 170 A. Also based on the control signal S 170 A, the switch unit 101 A selects path 171 a or path 171 b , and passes the impedance-converted signal S 102 at on impedance 163 using the selected path. The switch unit 101 A thus outputs pass signal S 101 a or pass signal S 101 b corresponding to the selected output path.

The pass signals S 101 a , S 101 b are input to the matching circuits 103 a and 103 b at an input impedance 164 a , 164 b substantially equal to a complex conjugate of a complex sum of the output impedance 162 and the on impedance 163 . That is, the matching circuits 103 a and 103 b extract the maximum power from the matching circuit 102 A by impedance matching the output impedance 162 . In addition, the matching circuits 103 a and 103 b convert the impedance of the pass signals S 101 a , S 101 b and output impedance-converted signals S 103 a , S 103 b to the output pins 151 a and 151 b at output impedance 165 a , 165 b , which is substantially equal to load impedance 166 . The load impedance 166 is the impedance of the load connected to the output pins 151 a and 151 b . For example, if the load impedance 166 is a pure resistance of 50Ω, there may be a 50-Ω antenna connected through a 50-Ω transmission path (not shown in the figure). By matching with the impedance of the amplified signal S 100 , the matching circuits 103 a and 103 b suppress waveform distortion caused by reflection waves from the load while supplying the maximum power to the load. The switch unit 101 A and matching circuits 102 A, 103 a , 103 b constitute a load matching circuit 105 A. The impedances are expressed as complex numbers of which the real part is the resistance component and the imaginary part is the reactance.

FIG. 3 is a circuit diagram showing the switch unit 101 A in the first embodiment of the invention. The switch unit 101 A has a single-pole, double-throw switch 106 c , and ground switches 106 a , 106 b on the output pin side. The switch unit 101 A turns on the switch 106 a , 106 b on the path that is not selected. The unselected path therefore goes to ground, paths 171 a and 171 b are reliably isolated, and interference therebetween is reduced. In a device such as a cell phone that is densely populated with high frequency circuits, it is necessary to isolate such parallel processing circuits. The switches 106 a , 106 b can, however, be omitted.

When a switch unit 101 A is disposed to the output side of the final stage amplification unit 100 , signal loss by the switch unit 101 A must be avoided. If the absolute value of the output impedance 162 of the matching circuit 102 A is set higher than the absolute value of the on impedance 163 , the sum of the complex values of output impedance 162 and on impedance 163 is substantially equal to output impedance 162 . More particularly, the on impedance 163 is a level that can be ignored regardless of the phase, and signal loss by the switch unit 101 A is reduced to a level that can be ignored.

For example, the on impedance 163 is typically approximately 1Ω, and the output impedance 162 is preferably set to 10Ω or greater and further preferably to several 10Ω. In this case the matching circuit 102 A converts the typically 3-8Ω input impedance 161 to an output impedance 162 that is greater than the input impedance 161 , and reduces signal loss from the switch unit 101 A. Because the input impedance 164 a , 164 b of the matching circuits 103 a and 103 b is substantially equal to a complex conjugate of the sum of the complex variables of the output impedance 162 and on impedance 163 , the absolute values of the input impedances 164 a , 164 b increase approximately equally to the absolute value of the output impedance 162 .

The output impedance 162 and the load impedance 166 are compared next. As described above, because the input impedances 164 a , 164 b are substantially equal to a complex conjugate of the output impedance 162 , their reactance components are mutually cancelled. As a result, the resistance component of the output impedance 162 is compared with the load impedance 166 , which is substantially composed of a resistance component. If the absolute value of the output impedance 162 is sufficiently greater than the absolute value of the on impedance 163 , the resistance component of the output impedance 162 can be greater or less than the load impedance 166 . If the resistance component of the output impedance 162 is substantially equal to the load impedance 166 , the matching circuits 103 a and 103 b can be omitted. If the resistance component of the output impedance 162 is different from the load impedance 166 , the matching circuits 103 a and 103 b impedance convert the input impedance 164 a , 164 b to an output impedance 165 a , 165 b substantially equal to the load impedance 166 . Note that the matching circuits 103 a and 103 b can also be omitted even when the resistance component of the output impedance 162 differs from the load impedance 166 if impedance matching to the load impedance 166 is not necessary.

FIG. 4A , FIG. 4B , FIG. 4C , and FIG. 4D are Smith charts describing the input/output impedance at various points in the first embodiment shown in FIG. 2 . The center of the Smith chart denotes the 50-Ω characteristic impedance ZC with the left end being the shorted (0Ω) side. The control unit 170 A generates a control signal S 170 A describing the frequency F 1 , F 2 (where F 1 <F 2 ) of the amplified signal S 100 . Based on this control signal S 170 A the switch unit 101 A selects the paths 171 a and 171 b corresponding to the frequency F 1 , F 2 .

FIG. 4A shows output impedance 160 . FIG. 4B shows output impedance 162 . FIG. 4C shows the input impedances 164 a , 164 b corresponding to frequencies F 1 , F 2 . FIG. 4D shows the output impedance 165 a , 165 b at frequency F 1 , F 2 . Impedances ZAF 1 , ZBF 1 , ZCF 1 , ZDF 1 correspond to frequency F 1 , and impedances ZAF 2 , ZBF 2 , ZCF 2 , ZDF 2 correspond to frequency F 2 . Because the final stage amplification unit 100 , matching circuit 102 A, switch unit 101 A, and matching circuits 103 a and 103 b each have their own frequency characteristic, impedances ZAF 1 , ZBF 1 , and ZCF 1 and impedances ZAF 2 , ZBF 2 , and ZCF 2 are at different positions.

Impedances ZAF 1 , ZAF 2 are lower than characteristic impedance ZC and near the short side. Impedances ZAF 1 , ZAF 2 each contain a reactance component. Impedances ZAF 1 , ZAF 2 are converted by the matching circuit 102 A to a higher impedance ZBF 1 , ZBF 2 and move closer to the characteristic impedance ZC. Impedances ZBF 1 , ZBF 2 also each contain a reactance component. If the effect of the on impedance 163 is ignored, impedances ZCF 1 , ZCF 2 are complex conjugates of impedances ZBF 1 , ZBF 2 . Impedances ZCF 1 , ZCF 2 are converted by the matching circuits 103 a and 103 b , respectively, to approximately 50-Ω impedances ZDF 1 , ZDF 2 , which go to the characteristic impedance ZC and have a reactance component of zero.

As shown in FIG. 4B , the resistance components of impedances ZBF 1 , ZBF 2 can differ, and the reactance components of impedances ZBF 1 , ZBF 2 can differ. If the effect of the on impedance 163 is ignored, the reactance component of impedance ZBF 1 and the reactance component of ZCF 1 are mutually cancelling, and the reactance component of impedance ZBF 2 and the reactance component of ZCF 2 are mutually cancelling. Furthermore, if the resistance components of impedances ZBF 1 , ZBF 2 are also substantially equal and the on impedance 163 is low enough that it can be ignored, compared with the resistance of ZBF 1 , ZBF 2 , insertion loss from the switch unit 101 A can be reduced. In other words, in order to reduce insertion loss from the switch unit 101 A, the resistance component of the output impedance 162 must be sufficiently greater than the on impedance 163 and substantially constant relative to each frequency F 1 , F 2 . More specifically, if the load impedance 166 is 50Ω, the resistance component of the output impedance 162 is set to 30-50Ω, for example.

In another specific example the control unit 170 A generates a control signal S 170 A denoting the power level P 1 , P 2 (where P 1 <P 2 ) of the amplified signal S 100 . Based on this control signal S 170 A the switch unit 101 A selects the paths 171 a and 171 b corresponding to the signal power P 1 , P 2 .

In yet another specific example the control unit 170 A generates a control signal S 170 A denoting the frequency F 1 , F 2 and the power level P 1 , P 2 of the amplified signal S 100 . Based on this control signal S 170 A the switch unit 101 A selects the paths 171 a and 171 b corresponding to the frequency F 1 , F 2 and signal power P 1 , P 2 .

By thus matching the output impedance 160 of the final stage amplification unit 100 at the input side, the load matching circuit 105 A in this first embodiment of the invention can extract maximum power from the final stage amplification unit 100 . Furthermore, by matching the 50-Ω load impedance 166 at the output side, the load matching circuit 105 A can supply maximum power to the load and can suppress waveform distortion by wave reflection from the load. Yet further, by internally setting the absolute value of the output impedance 162 of the matching circuit 102 A higher than the absolute value of the on impedance 163 of the switch unit 101 A, the load matching circuit 105 A can set the on impedance 163 to a relative level that can be ignored. More specifically, the matching circuit 102 A sets the input impedance 161 relatively low to match the output impedance 160 of the final stage amplification unit 100 , and sets the output impedance 162 enough greater than the input impedance 161 that the on impedance 163 can be ignored. As a result, loss from the switch unit 101 A can be reduced, waveform distortion can be suppressed, and maximum power can be supplied to the load when setting the switch unit 101 A on the output side of the final stage amplification unit 100 .

Furthermore, by using a switch unit 101 A with low signal loss, the input impedance 164 a , 164 b and output impedance 165 a , 165 b of the matching circuits 103 a and 103 b can be individually optimized based on the frequency F 1 , F 2 and power P 1 , P 2 . As a result, even if the selected frequency band of a multiband cell phone that is compatible with different wireless frequency bands changes, or the transmission power of a multimode cell phone that is compatible with different transmission systems changes, or if the combination of the selected frequency band and transmission power changes, the appropriately optimized matching circuit can be selected and used. As a result, the matching circuit is simplified and can be rendered smaller, the matching precision of each matching circuit can be improved, and transmission power efficiency and waveform precision can therefore be improved. The coverage area of the cell phone is therefore increased and power consumption is reduced.

This embodiment of the invention thus affords a small, high performance, and multifunctional high frequency circuit.

The switch unit 101 A and matching circuit 102 A are both controlled based on the control signal S 170 A in this embodiment, but the control signal S 170 A could be used to control only the switch unit 101 A.

The final stage amplification unit 100 could also be a multistage amplifier.

The second embodiment of the invention is described next with particular attention to the differences with the first embodiment. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the first embodiment, and further description thereof is omitted.

FIG. 5 is a block diagram of a high frequency circuit according to a second embodiment of the invention. The switch unit 101 A of the first embodiment is replaced by a switch unit 101 B in this second embodiment. The switch unit 101 B is a single-pole, n-throw (where n is an integer of 3 or more) switch. The control unit 170 B generates a control signal S 170 B denoting signal path selection information applied to the switch unit 101 B. The matching circuit 102 B controls the output impedance 162 based on control signal S 170 B. Also based on the control signal S 170 B, the switch unit 101 B selects path 171 a , 171 b , to 171 n and passes the impedance-converted signal S 102 at on impedance 163 using the selected path. The switch unit 101 B thus outputs pass signal S 101 a , pass signal S 101 b , . . . , pass signal S 101 n corresponding to the selected output path.

The pass signals S 101 a , S 101 b , to S 101 n are input to the matching circuits 103 a , 103 b , to 103 n at an input impedance 164 a , 164 b , to 164 n substantially equal to a complex conjugate of a complex sum of the output impedance 162 and the on impedance 163 . That is, the matching circuits 103 a , 103 b , to 103 n extract the maximum power from the matching circuit 102 B by matching with the impedance of the output impedance 162 . In addition, the matching circuits 103 a , 103 b , to 103 n convert the impedance of the pass signals S 101 a , S 101 b to S 101 n and output impedance-converted signals S 103 a , S 103 b , to S 103 n to the output pins 151 a , 151 b to 151 n at an output impedance 165 a , 165 b , to 165 n which is substantially equal to load impedance 166 . The load impedance 166 is the impedance of the load connected to the output pins 151 a , 151 b to 151 n.

By impedance matching the load impedance 166 , the matching circuits 103 a , 103 b , to 103 n suppress waveform distortion caused by reflection waves from the load while supplying the maximum power to the load. The switch unit 101 B, and matching circuits 102 B, 103 a , 103 b , to 103 n constitute a load matching circuit 105 B.

In one specific example the control unit 170 B generates a control signal S 170 B describing the frequency F 1 , F 2 to Fn (where F 1 <F 2 <Fn) of the amplified signal S 100 . Based on this control signal S 170 B the switch unit 101 B selects the signal path 171 a , 171 b to 171 n corresponding to the frequency F 1 , F 2 to Fn. In order to reduce insertion loss from the switch unit 101 B, the matching circuit 102 B sets the resistance component of the output impedance 162 sufficiently greater than the on impedance 163 and substantially constant relative to each frequency F 1 , F 2 to Fn.

In another specific example the control unit 170 B generates a control signal S 170 B denoting the power level P 1 , P 2 , to Pn (where P 1 <P 2 <Pn) of the amplified signal S 100 . Based on this control signal S 170 B the switch unit 101 B selects the path 171 a , 171 b to 171 n corresponding to the signal power P 1 , P 2 to Pn.

In yet another specific example the control unit 170 B generates a control signal S 170 B denoting n combinations of the frequency F 1 , F 2 to Fi (where i is an integer of 1≦i≦n) and power level P 1 , P 2 to Pj (where j is an integer of 1≦j≦n) of the amplified signal S 100 . Based on this control signal S 170 B the switch unit 101 B selects the paths 171 a , 171 b to 171 n corresponding to the n combinations of the frequency F 1 , F 2 to Fi and power level P 1 , P 2 to Pj.

This second embodiment of the invention has more output pins on the SPnT switch unit 101 B and more matching circuits 103 a , 103 b , to 103 n than the first embodiment. As a result, this embodiment can be rendered compatible with the desired number of bands and modes.

This second embodiment has one final stage amplification unit 100 and one matching circuit 102 B, but could be rendered with N final stage amplification units 100 and N matching circuit 102 B (where N is an integer of 2 or more), and the switch unit 101 B could select one of the paths 171 a , 171 b to 171 n for outputting the N impedance-converted signals S 102 output from the N matching circuits 102 B.

The third embodiment of the invention is described next with particular attention to the differences with the first embodiment. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the first embodiment, and further description thereof is omitted.

FIG. 6 is a circuit diagram showing an example of the matching circuit 102 A in a third embodiment of the invention. The high frequency circuit in this third embodiment is identical to the high frequency circuit of the first embodiment shown in FIG. 2 . FIG. 7A , FIG. 7B , and FIG. 7C are Smith charts showing the input/output impedance of selected parts in FIG. 2 and FIG. 6 .

As described in the first embodiment, the matching circuit 102 A controls the output impedance 162 based on the control signal S 170 A. To reduce insertion loss from the switch unit 101 A, the matching circuit 102 A sets the resistance component of the output impedance 162 sufficiently greater than the on impedance 163 and substantially constant to frequency F 1 , F 2 .

More specifically, the amplified signal S 100 is input to the matching circuit 102 A, which generates an internal matching circuit signal S 100 Z by a shunt capacitor and passive device 120 . The passive device 120 is a microstrip line or inductor.

The internal circuit 102 A 1 inside the matching circuit 102 A has an input node 121 and an output node 122 . A circuit having a capacitance C 1 , switch 107 , and capacitance C 2 connected in this order in series is parallel connected to a capacitance C 3 , and the ends of this parallel connection are respectively connected to the input node 121 and output node 122 .

The internal matching circuit signal S 100 Z is input to the input node 121 of the internal circuit 102 A 1 , which outputs impedance-converted signal S 102 from the output node 122 .

The switch 107 switches on/off based on the control signal S 170 input to the control node 123 of the switch 107 . When the switch unit 101 A selects signal path 171 a for frequency F 1 , the matching circuit 102 A turns the switch 107 on. When the switch unit 101 A selects signal path 171 b for frequency F 2 , the matching circuit 102 A turns the switch 107 off. The switch 107 thus changes the output impedance 162 .

FIG. 7A and FIG. 7B show the output impedance 162 state. FIG. 7C shows the input impedance 164 a , 164 b at frequency F 1 , F 2 , respectively. Impedances ZAF 1 , ZBF 1 , ZCF 1 correspond to frequency F 1 , and ZAF 2 , ZBF 2 , ZCF 2 correspond to frequency F 2 . When the switch 107 is on, the impedance ZAF 1 at frequency F 1 is sufficiently high as shown in FIG. 7A . However, because the serial capacitance between the input/output pins of the internal circuit 102 A 1 is relatively large, the impedance ZAF 2 to frequency F 2 is low. Therefore, if switch 107 is off at frequency F 2 , the serial capacitance of the internal circuit 102 A 1 is relatively small, and the impedance ZBF 2 to the frequency F 2 is sufficiently high as shown in FIG. 7B . In FIG. 7C the impedances ZCF 1 , ZCF 2 are in a complex conjugate relationship with impedances ZAF 1 , ZBF 2 .

Variations of the internal circuit 102 A 1 shown in FIG. 6 are described next. FIG. 10A shows an arrangement in which the capacitance C 1 connected to the input node 121 in the internal circuit 102 A 1 in FIG. 6 is omitted, and the switch 107 is connected directly to the input node 121 .

FIG. 10B shows an arrangement in which the capacitance C 1 , switch 107 , and capacitance C 2 are connected in a series circuit, the capacitance C 1 end is inserted between the input node 121 and output node 122 , and the capacitance C 2 end is to ground. Some other circuit could additionally be inserted between the input node 121 and output node 122 .

FIG. 10C shows an arrangement in which the capacitance C 1 connected to the input node 121 in the internal circuit 102 A 1 in FIG. 10B is omitted, and the one side of the switch 107 is inserted directly between the input node 121 and output node 122 .

The operation of the internal circuit 102 A 1 shown in FIG. 10A to FIG. 10C is as described above.

FIG. 11 shows a variation of a internal circuit 102 A 1 using microstrip lines. A series circuit including a switch 107 a and microstrip line 109 a , and a series circuit including a switch 107 b and microstrip line 109 b , are parallel connected, and nodes at the ends of the parallel circuits are connected to input node 121 and output node 122 . The microstrip line 109 a and 109 b differ in the line length, and adjust the output impedance 162 based on the control signal S 170 input to the control node 123 . The internal circuit 102 A 1 using microstrip lines can be rendered by forming the switches 107 a and 107 b on a semiconductor chip, forming the microstrip lines 109 a and 109 b on a circuit board module on which the semiconductor chips are mounted, and connecting them with wires. The internal circuit 102 A 1 shown in FIG. 11 can also be rendered by replacing the microstrip lines 109 a and 109 b with two inductors of different inductance.

The internal circuit 102 A 1 can also be rendered by replacing at least one of the capacitances C 1 , C 2 , C 3 with an inductor or microstrip line in the circuits shown in FIG. 6 and FIG. 10A to FIG. 10C .

The internal circuit 102 A 1 could also be rendered as a hybrid circuit composed of a suitable combination of the circuits shown in FIG. 6 , FIG. 10A to FIG. 10C , and FIG. 11 and these circuits in which at least one of the capacitances C 1 , C 2 , C 3 is replaced with an inductor or microstrip line. In the circuits rendering this hybrid circuit, the capacitances C 1 , C 2 , C 3 , inductors, and microstrip lines can be different sizes.

The matching circuit 102 A in this third embodiment of the invention is rendered as shown in FIG. 6 , FIG. 10A to FIG. 10C , and FIG. 11 to turn the switch 107 on/off. As a result, the resistance component of the output impedance 162 is sufficiently greater than the on impedance 163 and substantially constant at each frequency F 1 , F 2 . Insertion loss from the switch unit 101 A is also sufficiently reduced. This is effective when the frequencies F 1 and F 2 are several 10 MHz apart, and even more effective when 100 MHz apart. The design of the control unit 170 is simplified by linking selection of the paths 171 a and 171 b by the switch unit 101 A to the on/off state of the switch 107 in the matching circuit 102 A.

The fourth embodiment of the invention is described next with particular attention to the differences with the second and third embodiments. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the second and third embodiments, and further description thereof is omitted.

FIG. 8 is a circuit diagram showing an example of the matching circuit 102 B in a fourth embodiment of the invention. The high frequency circuit in this embodiment is identical to the high frequency circuit of the second embodiment shown in FIG. 5 . FIG. 9A and FIG. 9B are Smith charts showing the input/output impedance of selected parts in FIG. 5 and FIG. 8 .

As described in the second embodiment, the matching circuit 102 B controls the output impedance 162 based on the control signal S 170 B. To reduce insertion loss from the switch unit 101 B, the matching circuit 102 B sets the resistance component of the output impedance 162 sufficiently greater than the on impedance 163 and substantially constant to frequency F 1 , F 2 to Fn.

More specifically, the amplified signal S 100 is input to the matching circuit 102 B, which generates an internal matching circuit signal S 100 Z by a shunt capacitor and passive device 120 . The passive device 120 is a microstrip line or inductor.

The internal circuit 102 B 1 of the matching circuit 102 B has an input node 121 and an output node 122 . The internal circuit 102 B 1 includes n parallel circuits, including a series circuit having a capacitance C 1 , a switch 107 a , and a capacitance C 2 connected in order, m−1 identical series circuits replacing switch 107 a with a switch 107 b to 107 m (where m =n−1), and a capacitance C 3 parallel connected to the series circuits with the ends of the parallel circuits respectively connected to the input node 121 and output node 122 . In the m series circuits having capacitance C 1 and capacitance C 2 , capacitances C 1 and C 2 can be different from each other.

The internal matching circuit signal S 100 Z is input to the input node 121 of the internal circuit 102 B 1 , which outputs impedance-converted signal S 102 from the output node 122 .

The switches 107 a to 107 m switch on/off based on the m control signals S 170 input to the control nodes 123 of the switches 107 a to 107 m.

When the switch unit 101 B selects signal path 171 a for frequency F 1 , the matching circuit 102 B turns all switches 107 a to 107 m (where m=n−1) on. When the switch unit 101 B selects signal path 171 b for frequency F 2 , the matching circuit 102 B turns only switch 107 a off. Likewise, when the switch unit 101 B selects signal path 171 n for frequency Fn, the matching circuit 102 B turns all switches 107 a to 107 m off. As a result, the serial capacitance between the input/output pins of the internal circuit 102 B 1 decreases sequentially from frequency F 1 to frequency F 2 to frequency Fn. The output impedance S 102 thus increases independently of the frequency.

FIG. 9A shows the impedance state when frequency F 2 is selected and only switch 107 a is off. Impedance ZAF 2 is sufficiently high but impedance drops at frequencies other than frequency F 2 . This shows that it is difficult to keep impedance high irrespective of frequency using the same passive circuit. However, by using switches 107 a to 107 m , the output impedance S 102 changes as indicated by impedance ZBF 1 , ZBF 2 , to ZBFn for frequency F 1 , F 2 , to Fn, and is substantially constant as shown in FIG. 9B .

A variation of the matching circuit 102 B shown in FIG. 8 is described next.

FIG. 10D shows an arrangement in which all of the capacitances C 1 connected to the input node 121 in the internal circuit 102 B 1 in FIG. 8 are omitted, and the switches 107 a to 107 m are connected directly to the input node 121 .

FIG. 10E shows an arrangement having a series circuit including a capacitance C 1 , a switch 107 a , and a capacitance C 2 , and n−1 identical series circuits in which switch 107 a is replaced by a switch 107 b to 107 n parallel connected to the first series circuit. The capacitance C 1 end of each parallel circuit is connected between the input node 121 and output node 122 , and the capacitance C 2 end of each circuit is to ground. Some other circuit could additionally be inserted between the input node 121 and output node 122 .

FIG. 10F shows an arrangement in which all capacitances C 1 connected to the input node 121 in the internal circuit 102 B 1 in FIG. 10E are omitted, and one side of the switches 107 a to 107 n is inserted directly between the input node 121 and output node 122 .

FIG. 10G shows a variation of the internal circuit 102 B 1 in FIG. 8 in which the capacitance C 3 is omitted and there are n series circuits including a capacitance C 1 , a switch, and a capacitance C 2 .

FIG. 10H shows a variation of the arrangement in FIG. 10G in which all capacitances C 1 connected to the input node 121 are omitted, and the switches 107 a to 107 n are directly connected to the input node 121 .

The capacitances C 1 and C 2 can be different in each of the m or n circuits having at least one capacitance C 1 or C 2 in the arrangements shown in FIG. 10D to FIG. 10H .

The operation of the internal circuit 102 B 1 shown in FIG. 10D to FIG. 10H is as described above.

The internal circuit 102 B 1 can also be rendered by replacing at least one of the capacitances C 1 , C 2 , C 3 with an inductor or microstrip line in the circuits shown in FIG. 8 and FIG. 10D to FIG. 10H .

The internal circuit 102 B 1 could also be rendered as a hybrid circuit composed of a suitable combination of the circuits shown in FIG. 8 and FIG. 10D to FIG. 10H and these circuits in which at least one of the capacitances C 1 , C 2 , C 3 is replaced with an inductor or microstrip line. In the circuits rendering this hybrid circuit, the capacitances C 1 , C 2 , C 3 , inductors, and microstrip lines can be different sizes.

The matching circuit 102 B in this fourth embodiment of the invention is rendered as shown in FIG. 8 to turn the switches 107 a to 107 m on/off. As a result, the resistance component of the output impedance 162 is sufficiently greater than the on impedance 163 and substantially constant at each frequency F 1 , F 2 to Fn. Insertion loss from the switch unit 101 A is also sufficiently reduced.

Part of the m capacitances connected to the switches 107 a to 107 m in the internal circuit 102 B 1 shown in FIG. 8 can differ from the other capacitances. The m switches 107 a to 107 m can also be replaced by k (where 3≦k<m) switches 107 a to 107 k . In this case the k switches 107 a to 107 k are arranged so that the switches can be appropriately turned on/off in different combinations to produce n capacitances in the internal circuit 102 B 1 .

The fifth embodiment of the invention is described next with particular attention to the differences with the first to fourth embodiments. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the second and third embodiments, and further description thereof is omitted.

FIG. 12A is a block diagram of a high frequency circuit according to the fifth embodiment of the invention. FIG. 12B is a circuit diagram of the matching circuit 103 b in the fifth embodiment of the invention. FIG. 12C is a Smith chart describing the operation of the high frequency circuit according to the fifth embodiment of the invention.

As shown in FIG. 12B , a pass signal S 101 b is input to the matching circuit 103 b , which generates an internal matching circuit signal S 101 b Z by a passive device 120 . The passive device 120 is a microstrip line or inductor.

The internal circuit 103 b 1 of the matching circuit 103 b has an input node 124 and an output node 125 . The internal circuit 103 b 1 includes a series circuit having a capacitance C 1 , a switch 110 , and a capacitance C 2 connected in order, and a capacitance C 3 parallel connected to the series circuit with the ends of the parallel circuits respectively connected to the input node 124 and output node 125 .

The internal matching circuit signal S 101 b Z is input to the input node 124 of the internal circuit 103 b 1 , which outputs impedance-converted signal S 103 b from the output node 125 .

The switch 110 switches on/off based on the control signal S 170 A input to the control node 126 of the switch 110 .

In FIG. 12A the control unit 170 A generates a control signal S 170 A describing the frequency and signal power of the amplified signal S 100 . The switch unit 101 A selects path 171 a or path 171 b based on the frequency F 1 , F 2 of the amplified signal S 100 . The matching circuit 103 a operates at frequency F 1 and the matching circuit 103 b operates at frequency F 2 . For example, at frequency F 1 the matching circuit 103 a sets the output power of the amplified signal S 100 to P 1 based on the control signal S 170 A. At frequency F 2 , the matching circuit 103 b turns the switch 110 off when the power of the amplified signal S 100 is P 2 , and turns switch 110 on if the power of the amplified signal S 100 is P 3 , which is less than P 2 . As a result, when the power is P 3 , the input impedance 164 b of the matching circuit 103 b is higher than when the power is P 2 .

FIG. 12C and FIG. 12D are Smith charts showing the input impedance 161 of the matching circuit 102 A in this fifth embodiment of the invention. In FIG. 12C the impedance ZAP 2 indicates the input impedance 161 at power P 2 . In FIG. 12D , impedance ZAP 3 indicates the input impedance 161 at power P 3 . Because the input impedance 164 b of the matching circuit 103 b rises, impedance ZAP 3 is greater than impedance ZAP 2 .

By rendering the matching circuit 103 b as shown in FIG. 12B in this fifth embodiment of the invention, the switch 110 is controlled according to the power of the amplified signal S 100 to change the input impedance 164 b of the matching circuit 103 b . The input impedance 161 can thus be optimally adjusted according to the power, and the power efficiency of the final stage amplification unit 100 can be increased. In addition, the input impedance 161 can be optimized according to the frequency by using the switch unit 101 A to enable the matching circuits 103 a and 103 b according to the frequency. This fifth embodiment of the invention can thus maximize power efficiency for both frequency and power.

The matching circuit 103 b adjusts the input impedance 164 b according to the strength of the amplified signal S 100 , and the strength of the amplified signal S 100 can be expressed as either average power or peak power.

FIG. 12B shows the arrangement of the matching circuit 103 b , but the matching circuit 103 a could be arranged this way instead, or both matching circuit 103 a and matching circuit 103 b can be arranged this way.

Furthermore, in the second embodiment shown in FIG. 5 any one of the matching circuit 103 a to 103 n can be arranged as shown in FIG. 12B .

Yet further, the arrangement in FIG. 12B maximizes power efficiency according to the magnitude of the amplified signal S 100 , but could alternatively be used to minimize the distortion characteristic according to the magnitude of the amplified signal S 100 . An arrangement for maximizing power efficiency and an arrangement for minimizing distortion could also be selectively enabled according to the application. In this case at least one of capacitances C 1 , C 2 , and C 3 is switched in both arrangements.

As described in the fourth embodiment, the matching circuit 103 b shown in FIG. 12B can be modified in the same way as the internal circuits 102 B 1 shown in FIG. 8 and FIG. 10D to FIG. 10H , and can be further modified by replacing at least a part of the capacitances C 1 , C 2 , C 3 with an inductor or microstrip line.

The internal circuit 102 B 1 could also be rendered as a hybrid circuit composed of a suitable combination of the circuits shown in FIG. 8 , FIG. 10D to FIG. 10H , and FIG. 11 and these circuits in which at least one of the capacitances C 1 , C 2 , C 3 is replaced with an inductor or microstrip line. In the circuits rendering this hybrid circuit, the capacitances C 1 , C 2 , C 3 , inductors, and microstrip lines can be different sizes.

In the circuits rendering this hybrid circuit, the capacitances C 1 , C 2 , C 3 , inductors, and microstrip lines can be different sizes. Circuits rendered with microstrip lines as shown in FIG. 11 can also be mounted as described in the third embodiment.

The sixth embodiment of the invention is described next with particular attention to the differences with the fifth embodiment. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the fifth embodiment, and further description thereof is omitted.

FIG. 13A and FIG. 13B are waveform diagrams showing the change in the magnitude of the amplified signal S 100 in a period of time. When the amplified signal S 100 is a CDMA (code division multiple access), OFDM (orthogonal frequency division multiplexing), or similarly modulated signal, the amplitude of the amplified signal S 100 changes in a period of time. In FIG. 13A the peak power PA of the amplified signal S 100 is approximately 4 dB higher than the average power P 1 , and in FIG. 13B the peak power PB of the amplified signal S 100 is approximately 2 dB higher than the average power P 1 .

If amplified signal S 100 distortion can be decreased when processing a variable amplitude modulation signal, the quality of the SNR of the impedance-converted signal S 103 output to the antenna can be improved and crosstalk can be reduced. To do this the final stage amplification unit 100 must linearly amplify the input signal S 150 to peak power. However, the power efficiency of the final stage amplification unit 100 drops if the final stage amplification unit 100 is designed to linearly amplify the input signal to peak power PA as shown in FIG. 13A , even when the signal is only used to peak power PB as shown in FIG. 13B .

FIG. 14A and FIG. 14B show the power efficiency of the same final stage amplification unit 100 when generating the amplified signal S 100 shown in FIG. 13A and FIG. 13B .

In FIG. 14A the operating curve LA indicated by the bold line is characterized by average power P 1 and peak power PA, which corresponds to the maximum output power in the linear operating range RLN of the final stage amplification unit 100 . The power efficiency at average power P 1 is E 1 , and the peak power efficiency at peak power PA is EA.

In FIG. 14B the operating curve LB indicated by the bold dotted line is characterized by average power P 1 and peak power PB, which is lower than peak power PA. The power efficiency at average power P 1 is E 1 , and the peak power efficiency at peak power PB is EB, which is less than EA. The final stage amplification unit 100 operating state represented by the operating curve LA is called the high peak power mode, and the operating state represented by operating curve LB is called the low peak power mode.

Because peak power efficiency EB is lower than EA on operating curve LB, average power efficiency E 1 is equal to the average power efficiency E 1 on operating curve LA even though the peak power PB of the amplified signal S 100 is low. If the linear operating range RLN is lowered from peak power PA or less to peak power PB or less and the peak power efficiency at peak power PB is EA as shown by the operating curve LC denoted by the solid bold line in FIG. 14C , the peak power efficiency at average power P 1 goes from E 1 to a higher E 2 , and the final stage amplification unit 100 can be operated with higher efficiency.

The linear operating range RLN of the final stage amplification unit 100 can be changed by the input impedance 161 . In the fifth embodiment of the invention switch 110 is used to change the input impedance 164 b of the matching circuit 103 b to optimize the input impedance 161 for the average power. The switch 110 can be similarly used to change the input impedance 164 b of the matching circuit 103 b , optimize the input impedance 161 based on peak power PA and PB, and increase the power efficiency of the final stage amplification unit 100 .

More specifically, when the arrangement shown in FIG. 12B is operating in the high peak power mode outputting peak power PA, switch 110 is off so that the input impedance 161 decreases. When operating in a low peak power mode outputting peak power PB, the switch 110 is on to increase the input impedance 161 .

This sixth embodiment of the invention switches the switch 110 in the arrangement described in the fifth embodiment to change the input impedance 164 b of the matching circuit 103 b according to the peak power of the selected operating mode. As a result, the input impedance 161 is optimized for the peak output power of the selected operating mode, and the power efficiency of the final stage amplification unit 100 can be maximized. This sixth embodiment of the invention can be beneficially used for data communications, for example, where the peak power may be changed to increase the transmission rate using the same modulation method.

The switch that switches according to the peak power of the operation mode can be the switch 107 or the switches 107 a to 107 m of the matching circuit 102 described according to the third or fourth embodiments above. The switch unit 101 A or switch unit 101 B of the first or second embodiment could also be used.

The seventh embodiment of the invention is described next with particular attention to the differences with the fifth and sixth embodiments. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the fifth and sixth embodiments, and further description thereof is omitted.

FIG. 15 is a block diagram of a high frequency circuit according to a seventh embodiment of the invention. The high frequency circuit according to this embodiment of the invention is the high frequency circuit shown in FIG. 12A according to the fifth embodiment with the addition of a bias circuit 111 and power supply circuit 112 .

Based on the control signal S 170 A, the bias circuit 111 supplies a bias output signal S 111 denoting the bias current at the input pin to the final stage amplification unit 100 or the bias voltage between the input and common nodes. Based on the control signal S 170 A, the power supply circuit 112 supplies supply voltage S 112 to the final stage amplification unit 100 . If the final stage amplification unit 100 is a multistage amplifier, the bias circuit 111 and power supply circuit 112 supply the bias output signal S 111 and supply voltage S 112 to at least one amplification stage.

As described in the fifth and sixth embodiments, this seventh embodiment optimizes the input impedance 161 according to the average power or the peak power of the amplified signal S 100 . The bias output signal S 111 and the supply voltage S 112 of the final stage amplification unit 100 are also adjusted in conjunction with optimizing the input impedance 161 . By thus optimizing the input impedance 161 and the bias output signal S 111 and supply voltage S 112 , power efficiency is further improved and distortion is further reduced.

The final stage amplification unit 100 is a bipolar transistor that has at least two different emitter areas, and the emitter area can be changed based on the control signal. The final stage amplification unit 100 could also be rendered using a field-effect transistor having at least two different gate widths, and the gate width can be changed according to the control signal. By thus optimizing the input impedance 161 while also optimizing the emitter area or gate width, power efficiency can be further improved and distortion can be further reduced.

The eighth embodiment of the invention is described next with particular attention to the differences with the first to seventh embodiments. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the first to seventh embodiments, and further description thereof is omitted.

This eighth embodiment describes the scope of the circuits rendered on a semiconductor chip in the first to seventh embodiments.

In the second embodiment shown in FIG. 5 , at least a part of the switch unit 101 B and the matching circuits 102 B, and 103 a , 103 b to 103 n that constitute the load matching circuit 105 B are rendered on the single semiconductor chip of the eighth embodiment. The final stage amplification unit 100 could also be rendered on the semiconductor chip of the eighth embodiment. If the internal circuit 102 B 1 shown in FIG. 8 or the switch 110 shown in FIG. 12B is included in the matching circuits 102 B, and 103 a , 103 b to 103 n , at least a part of these switches is included in the semiconductor chip of the eighth embodiment.

These switches are rendered using field-effect transistors (FET). The switches could also be rendered using high electron mobility transistors (HEMT), in which case the on resistance per chip area is less than with a FET, signal pass loss is less, and the chip area can be reduced.

If the capacitance devices or inductance devices used in the matching circuits 102 B and 103 a , 103 b to 103 n are also formed on the semiconductor chip of the eighth embodiment, a multifunction, high performance switch circuit can be rendered in a highly integrated semiconductor chip with a small footprint, and a small, multifunctional high frequency circuit can be rendered to great effect.

The overall arrangement of the high frequency circuit can also be simplified by rendering the control unit 170 B, bias circuit 111 , and power supply circuit 112 on the semiconductor chip of the eighth embodiment.

The semiconductor chip of the eight embodiment and the matching circuits 102 B, and 103 a , 103 b to 103 n that are not rendered on the semiconductor chip can also be formed or mounted on a resin or ceramic substrate. The microstrip lines of the matching circuits 102 B, and 103 a , 103 b to 103 n are rendered on the substrate while the inductors and capacitances are mounted as chips. In this case the final stage amplification unit 100 can be included or not included in the semiconductor chip. If the final stage amplification unit 100 is not included in the semiconductor chip, the final stage amplification unit 100 is mounted as a discrete chip on the substrate.

By thus rendering the switch unit 101 B and matching circuits 102 B, and 103 a , 103 b to 103 n on a semiconductor chip according to the eighth embodiment of the invention, the size and cost of the high frequency circuit and the high frequency power amplifier can be reduced.

The ninth embodiment of the invention is described next with particular attention to the differences with the first to eighth embodiments. Other aspects of the arrangement, operation, and effect of this embodiment are the same as in the first to eighth embodiments, and further description thereof is omitted.

This ninth embodiment of the invention describes a specific implementation of the first embodiment shown in FIG. 2 with reference to FIG. 16 . FIG. 17A and FIG. 17B are Smith charts showing the input impedance 164 and 164 a of the matching circuits 103 a and 103 b.

In FIG. 16 the final stage amplification unit 100 is a single common-emitter transistor. In the matching circuit 102 A one side of a 1000 pF capacitance is connected to the power supply pin 152 to which the power supply voltage is applied, and the other side of the capacitance goes to ground. One end of a 6-mm long microstrip line is connected to the power supply pin 152 , and the other end of the 6-mm microstrip line is connected to the collector of the final stage amplification unit 100 and a 0.25-mm microstrip line. The other end of this 0.25-mm microstrip line is connected to a 4-pF capacitance and a 5-mm microstrip line. The other end of the 4-pF capacitance goes to ground. The other end of the 5-mm microstrip line is connected to a 30-pF capacitance. The other end of the 30-pF capacitance is connected to a 0.2-pF capacitance, the other side of which goes to ground, and to the input pin of the switch unit 101 A.

The two output pins of the switch unit 101 A are connected to the 10-pF capacitance of the matching circuits 103 a and 103 b . In matching circuit 103 a , the other end of the 10-pF capacitance is connected to a 0.95-pF capacitance, the other side of which goes to ground, and a 4.5-mm microstrip line. The other end of the microstrip line is connected to the output pin 151 a . In matching circuit 103 b , the other end of the 10-pF capacitance is connected to a 0.15-pF capacitance, the other side of which goes to ground, and a 2-mm microstrip line. The other end of this microstrip line is connected to output pin 151 b.

In the ninth embodiment thus comprised, the switch unit 101 A selects matching circuit 103 a when the frequency of the amplified signal S 100 is 1.7 GHz, and selects the matching circuit 103 b when the frequency of the amplified signal S 100 is 2.0 GHz. The input impedance 164 a changes according to the frequency on a path as shown in the Smith chart in FIG. 17A , and at 1.7 GHz is positioned as indicated by point 164 a F 1 . The actual input impedance 164 a at this time is (60.3-j23.8) Ω. The input impedance 164 b similarly changes according to the frequency on a path as shown in the Smith chart in FIG. 17B , and at 2.0 GHz is positioned as indicated by point 164 b F 2 . The actual input impedance 164 a at this time is (54.8-j5.9) Ω.

The input impedance 164 a denoted by point 164 a F 1 is a complex conjugate of the output impedance 162 at 1.7 GHz. Likewise, the input impedance 164 b denoted by point 164 b F 2 is a complex conjugate of the output impedance 162 at 2.0 GHz. More specifically, the resistance component of the output impedance 162 is approximately 55-60Ω at 1.7-2.0 GHz, and is sufficiently greater than the on impedance 163 of the switch unit 101 A.

This ninth embodiment of the invention shows a specific implementation of the matching circuit 102 A having an output impedance 162 sufficiently greater than the on impedance 163 of the switch unit 101 A. Loss imposed by the switch unit 101 A can thus be reduced.

Summary of the Embodiments

As described above, the load matching circuit 105 A in the first aspect of the invention can extract the maximum power from the final stage amplification unit 100 by matching the output impedance 160 of the final stage amplification unit 100 on the input side. By simultaneously matching the 50-Ω load impedance 166 on the output side, the load matching circuit 105 A can also supply the maximum power to the load and suppress waveform distortion caused by reflection waves from the load. Yet further, the load matching circuit 105 A can also drive the on impedance 163 to a relative level that can be ignored by internally setting the absolute value of the output impedance 162 of the matching circuit 102 A sufficiently higher than the absolute value of the on impedance 163 of the switch unit 101 A. More specifically, the matching circuit 102 A sets the input impedance 161 relatively low to match the output impedance 160 of the final stage amplification unit 100 while also setting the output impedance 162 enough greater than the input impedance 161 that the on impedance 163 can be ignored. As a result, when a switch unit 101 A is disposed to the output side of the final stage amplification unit 100 , loss from the switch unit 101 A can be reduced, waveform distortion can be suppressed, and maximum power can be supplied to the load.

Furthermore, by using a switch unit 101 A from which loss is reduced, the input impedance 164 a , 164 b and the output impedance 165 a , 165 b of the matching circuits 103 a and 103 b can be separately optimized based on frequency F 1 , F 2 and power P 1 , P 2 . Signals can therefore be processed using an optimized matching circuit whether the used frequency band changes in a multiband cell phone that is compatible with different wireless frequencies, whether the transmission power changes in a multimode cell phone that is compatible with different wireless communication methods, or whether both the frequency band and transmission power change in a multiband, multimode cell phone. As a result, the arrangement of the matching circuit can be simplified, the matching circuit can be reduced in size, the matching precision of each matching circuit can be improved, and transmission power efficiency and waveform precision can therefore be improved. Cell phone coverage can therefore be increased and power consumption can be reduced.

The first aspect of the invention thus affords a small, high performance, multifunction high frequency circuit.

The second aspect of the invention affords multiband and multimode compatibility with a desired number of frequencies and transmission methods by using a SPnT switch unit 101 B and matching circuits 103 a , 103 b , to 103 n.

The matching circuit 102 A in the third aspect of the invention is rendered as shown in FIG. 6 , FIG. 10A to FIG. 10C , and FIG. 11 to switch a switch 107 on/off. By switching the switch 107 appropriately on/off based on the frequency F 1 , F 2 , the resistance component of the output impedance 162 can be held substantially constant and sufficiently greater than the on impedance 163 . Insertion loss from the switch unit 101 A can also be sufficiently reduced.

The matching circuit 102 B in the fourth aspect of the invention is rendered as shown in FIG. 8 and switches 107 a to 107 m are turned on/off. By switching the switches 107 a to 107 m appropriately on/off based on the frequency F 1 , F 2 , the resistance component of the output impedance 162 can be held substantially constant and sufficiently greater than the on impedance 163 . Insertion loss from the switch unit 101 A can also be sufficiently reduced.

In the fifth aspect of the invention the matching circuit 103 b is rendered as shown in FIG. 12B , and a switch 110 is controlled on/off according to the strength of the amplified signal S 100 to change the input impedance 164 b of the matching circuit 103 b . The input impedance 161 can thus be optimized to the power, and the power efficiency of the final stage amplification unit 100 can be improved. The input impedance 161 can also be optimized for the frequency by using a switch unit 101 A to select the matching circuits 103 a and 103 b according to the frequency. The fifth aspect of the invention can thus maximize power efficiency for both frequency and power.

The sixth aspect of the invention is rendered identically to the fifth aspect of the invention, but switches the switch 110 according to the peak power of the operating mode to change the input impedance 164 b of the matching circuit 103 b . The input impedance 161 can therefore be optimized according to the peak power of the operating mode to maximize the power efficiency of the final stage amplification unit 100 .

Together with optimizing the input impedance 161 as described in the fifth and sixth aspects of the invention, the seventh aspect of the invention also adjusts the bias output signal S 111 and supply voltage S 112 of the final stage amplification unit 100 . Power efficiency is further improved and distortion is further reduced by thus optimizing the bias output signal S 111 and supply voltage S 112 while also optimizing the input impedance 161 .

The eighth aspect of the invention renders the switch unit 101 B and matching circuits 103 a , 103 b , to 103 n on a semiconductor chip, thereby reducing the size and cost of the high frequency circuit.

The switch units 101 , 101 A, 101 B and the switches 106 a , 106 b , 106 c , 107 are rendered using FETs in the embodiments described above, but can alternatively be rendered using other types of switch mechanisms, including HEMT, PIN diodes (positive-intrinsic-negative diodes), or micro electromechanical systems (MEMS). The switch units and switches can also be rendered using one or a plurality of transistors.

The final stage amplification unit 100 in the foregoing embodiments is rendered using a bipolar transistor, but other types of transistors can be used instead, including heterojunction bipolar transistors, silicon-germanium transistors, FET, and insulated gate bipolar transistors (IGBT). The final stage amplification unit 100 can be rendered using one or a plurality of transistors. The final stage amplification unit 100 can also be rendered as a multistage amplifier. When the final stage amplification unit 100 is rendered using such transistors, a common-emitter or common-source transistor is typically used. In this case the input node is the base or gate and the output node is the collector or drain, and the common node is the emitter or source.

The present invention can be used in a high frequency circuit, in a semiconductor device, and in a high frequency power amplifier.

Although the present invention has been described in connection with the preferred embodiments thereof with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims, unless they depart therefrom.