Amplifier output stage with extended operating range and reduced quiescent current

The present disclosure generally relates to output stages in amplifier circuits. More particularly, the present disclosure relates to a technique for increasing the output range in an amplifier circuit while maintaining reduced quiescent current by selectively boosting the drive signal to the output transistors.

An integrated amplifier circuit is typically constructed from a small chip of semiconductor material upon which an array of active/passive components have been constructed and connected together to form a functioning circuit. Integrated amplifier circuits are generally encapsulated in a plastic housing (chip) with signal, power supply, and control leads or pins accessible for connection to external electronic circuitry. Input signals, which are received by the integrated amplifier circuit through input pins, are processed by active and/or passive components in different amplifier stages (e.g., input stage, turn-around stage, and output stage). The output stage of the amplifier is responsible for driving the amplifiers load through the external pins of the integrated circuit.

Amplifier circuits with wide output signal ranges require that the output voltage supplied by the output stage approaches the power supply limits (or rails) under various output loading conditions while maintaining satisfactory performance characteristics. In bipolar junction transistor (BJT) designs, the performance characteristics are influenced by transistor's collector bias current (Ic), collector-to-base voltage operating point (Vbe), temperature, and other factors resulting from the semiconductor manufacturing process. The amplifier circuits loading requirements and output voltage ranges are generally determined by the output transistor's terminal voltages, such as the transistors minimum collector-emitter voltage (Vce-min), base-collector junction voltage (Vbc), and worst case base drive current (Ib). The required quiescent current (IQ) for the transistors in the output stage are typically dictated by the worst case region of operation for the amplifier's performance.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a block diagram illustrating an example output stage in an amplifier that includes an extended output range, arranged in accordance with at least some aspects of the present disclosure.

FIG. 2 is a schematic diagram illustrating an example output stage circuit with an extended output range, arranged in accordance with at least some aspects of the present disclosure.

FIG. 3 is a schematic diagram illustrating a further detailed example of the DRIVE N block for the circuit of FIG. 2 , arranged in accordance with at least some aspects of the present disclosure.

FIG. 4 is a schematic diagram illustrating a further detailed example of the DRIVE P block for the circuit of FIG. 2 , arranged in accordance with at least some aspects of the present disclosure.

FIG. 5 is graphical diagram illustrating a performance of an example output stage circuit with extended output range when base current boosting is activated.

FIG. 6 is graphical diagram illustrating another performance of an example output stage circuit with extended output range when base current boosting is de-activated.

Embodiments are described more fully below with reference to the accompanying drawings, which form a part hereof, and which show specific exemplary embodiments. However, embodiments may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope. Embodiments may be practiced as methods, systems, circuits or devices. The various embodiments will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for use of the terms. The meaning of “a,” “an,” and “the” may include reference to both the singular and the plural. The meaning of “in” may include “in” and “on.” The term “connected” may mean a direct electrical, electromagnetic, mechanical, logical, or other connection between the items connected, without any electrical, mechanical, logical or other intermediary therebetween. The term “coupled” can mean a direct connection between items, an indirect connection through one or more intermediaries, or communication between items in a manner that may not constitute a connection. The term “circuit” can mean a single component or a plurality of components, active and/or passive, discrete or integrated, that are coupled together to provide a desired function. The term “signal” can mean at least one current, voltage, charge, data, or other such identifiable quantity

Briefly stated, the present disclosure generally relates to increasing the output range of an amplifier circuit while maintaining reduced quiescent current by selectively boosting the drive signal to one or more output transistors in the output stage of the amplifier. The drive signal to each output transistor is selectively increased only when demanded by the output load conditions. The threshold for boosting the drive signal can be adjusted for optimized performance. In one example, a class AB output stage includes a separate drive boost circuit for each output transistor. For this example, each drive boost circuit has a separate threshold for boosting each of the drive signals to the output transistors. The boosting can also be adjusted to optimize the differential input stage and current mirror maximum current requirement while maintaining minimum required bias currents.

Bipolar transistors can have varying amounts of gain (Beta) that result as a consequence of processing variations, temperature changes, and other circuit driven operating conditions. In order to ensure high output signal swings in the output stage of an amplifier circuit, the operating conditions for the output stage must be carefully analyzed. For example, the amount of base current (Ib) required for a BJT in an output stage may need to be increased to satisfy increased loading conditions, while the amount of base current may need to be decreased when light loading conditions exist.

As the signal swing of the output stage begins to approach the power supply limits (either high supply or low supply), the output transistors may begin to exhaust their available headroom. For example, the minimum voltage is required across the collector and emitter terminals of a transistor (VCE), also known as the minimum saturation voltage or VCE-SAT(min). A high magnitude for VCE-SAT(min) can reduce the available headroom before signal distortion or clipping may occur in the output signal. The minimum saturation voltage is a function of the biasing conditions of the transistor (e.g., the base current), the environmental operating conditions of the transistor, and the processing driven gain of the transistor.

As the output signal swing in the output stage approaches the power supply limits, the gain of the amplifier decreases as a consequence of the above-described, an other, limitations of the output transistors. In the presently described system, method and apparatus, the useable gain of the amplifier over the desired operating frequency range (or Bandwidth) is compensated by increasing the base drive to the output transistors as will be described below.

FIG. 1 is a block diagram illustrating an example output stage ( 100 ) in an amplifier that includes an extended output range, arranged in accordance with at least some aspects of the present disclosure. The output stage ( 100 ) includes a differential amplifier block (X 1 ), a threshold detector block (X 2 ), a first gain block (X 3 ), a second gain block (X 4 ), a bias current block (X 5 ), a current mirror block (X 6 ), a summer block (X 7 ), and an output transistor block (X 8 ).

An output of the differential amplifier block (X 1 ) is a first current (I 1 ) that has a magnitude corresponding to the quantity (I+S), where I is a DC current portion from the amplifier, and S is the signal varying portion from the amplifier. The threshold detector block (X 2 ) is arranged to evaluate the first current (X 1 ) and compare it to a threshold (TH). When the magnitude of the first current (I 1 ) is below the threshold (TH), the threshold detector circuit disables the first gain block (X 3 ). When the magnitude of the first current (I 1 ) is above the threshold (TH), the threshold detector circuit enables the first gain block (X 3 ), which then provides a third current (I 3 ) that is a function of the first current (I 1 ) as given by: I 3 =G I1 . The third current is coupled to a first additive (+) input of the summer block (X 7 ).

The second gain block (X 4 ) is arranged to provide a second current (I 2 ) that is proportional to the first current (I 1 ) as given by: I 2 =2*I 1 . The resulting magnitude of the second current (I 2 ) corresponds to I 2 =2*(I+S). The second current (I 2 ) is coupled to a second additive (+) input of the summer block (X 7 ). The bias current block (X 5 ) is arranged to generate a nominal biasing current (IB), which is coupled to a third additive (+) input of the summer block (X 7 ). The current mirror block (X 6 ) is arranged to subtract a fourth (I 4 ) current from the subtractive (−) input of the summer block (X 7 ), where the fourth current is given by: I 4 =2*(I−S).

The output of the summer block drives a biasing current (IOUTB) to a biasing input of the output transistor (X 8 ). The biasing current is determined from the various inputs of the summer block as: IOUTB=IB+I 2 +I 3 −I 4 . Substituting for I 2 and I 4 yields: IOUTB=IB+I 3 +2*(I+S)−2*(I−S). Consolidating terms, the biasing current (IOUT) is given as: IOUT=IB+I 3 +4*S. As described earlier, the third current (I 3 ) is equal to zero when the first current (I 1 ) is below threshold TH, which means that IOUT=IB+4*S under this condition. However, when the first current (I 1 ) exceeds the threshold (TH), IOUT=IB+4*S+G I1 . It can thus be seen that the biasing current to the output transistor is boosted when the first current (I 1 ) exceeds the threshold (TH).

The gain multiplier of the second gain block (X 2 ) is illustrated as a gain of two (2), but any other appropriate gain may be selected as long as an equal gain factor is reflected by the subtractive (−) input of the summer block (X 7 ). In other words, when I 2 is determined as I 2 =W*(I+S), I 4 should be given determined as I 4 =W*(I+S). In such an example, the biasing current (IOUT) is given as: IOUT=IB+I 3 +2*W*S.

FIG. 2 is a schematic diagram illustrating an example output stage circuit ( 200 ) with an extended output range, arranged in accordance with at least some aspects of the present disclosure. Output stage circuit 200 includes transistors Q 1 -Q 8 , amplifier circuits A 1 -A 2 , resistors RIN and RL, and drive circuits X 1 -X 2 .

Transistors Q 1 , Q 2 and Q 3 are configured with common base-emitters, where transistors Q 2 and Q 3 have equal transistor areas (1:1 ratioed, or 1X each), and transistor Q 1 has a transistor area that is twice (2×) the relative area of either of transistors Q 2 or Q 3 . Transistor Q 1 has an emitter terminal coupled to node 201 , a base terminal coupled to node 204 , and a collector terminal coupled to node 202 . Transistor Q 2 has an emitter terminal coupled to node 201 , a base terminal coupled to node 204 , and a collector terminal coupled to node 203 . Transistor Q 3 is a configured in a diode arrangement with an emitter terminal coupled to node 201 , a base terminal coupled to node 204 , and a collector terminal coupled to node 204 .

Transistors Q 4 , Q 5 and Q 6 are also configured with common base-emitters, where transistors Q 5 and Q 6 have equal transistor areas (1:1 ratioed, or 1× each), and transistor Q 4 has a transistor area that is twice (2×) the relative area of either of transistors Q 5 or Q 6 . Transistor Q 4 has an emitter terminal coupled to node 212 , a base terminal coupled to node 210 , and a collector terminal coupled to node 209 . Transistor Q 5 has an emitter terminal coupled to node 212 , a base terminal coupled to node 210 , and a collector terminal coupled to node 211 . Transistor Q 6 is a configured in a diode arrangement with an emitter terminal coupled to node 212 , a base terminal coupled to node 210 , and a collector terminal coupled to node 210 .

Transistor Q 7 includes an emitter coupled to node 201 , a base coupled to node 213 , and a collector coupled to node 215 . Transistor Q 8 includes an emitter coupled to node 212 , a base coupled to node 214 , and a collector coupled to node 215 . Resistor RL is coupled between node 215 and a circuit ground (GND).

Amplifier circuit A 1 includes an input terminal at node 207 , a voltage output terminal at node 205 , a first current terminal at node 202 , and a second current terminal at node 209 . Amplifier circuit A 2 includes an input terminal at node 208 , a voltage output terminal at node 206 , a first current terminal at node 204 , and a second current terminal at node 210 . Resistor RIN is coupled between nodes 205 and 206 .

Drive circuit X 1 (DRIVE P) includes a first current input terminal at node 202 , a second current input terminal at node 211 , and a current output terminal at node 213 . Drive circuit X 2 (DRIVE N) includes a first current input terminal at node 209 , a second current input terminal at node 203 , and a current output terminal at node 214 .

In operation, a high power supply voltage (VCC) is applied to node 201 , a low power supply voltage (VEE) is applied to node 212 , and a differential input signal (INP, INN) is applied across nodes 207 and 208 . Transistors Q 1 -Q 3 are arranged as a two output current mirror, where transistor Q 3 senses the current flow (IQ 3 ) in the second amplifier circuit (A 2 ) at node 204 , transistor Q 1 provide the current (IQ 1 =2*IQ 3 ) to the first amplifier circuit (A 1 ) and the first drive circuit (X 1 ) at node 202 , and transistor Q 2 provides the current input (IQ 2 =1*IQ 3 ) to drive circuit X 2 at node 203 . Transistors Q 4 -Q 6 are arranged as another two output current mirror, where transistor Q 6 senses the current flow (IQ 6 ) in the second amplifier circuit (A 2 ) at node 210 , transistor Q 4 provide the current (IQ 4 =2*IQ 6 ) to the first amplifier circuit (A 1 ) and the second driver circuit (X 2 ) at node 209 , and transistor Q 5 provides the current input (IQ 5 =1*IQ 6 ) to drive circuit X 1 at node 211 .

The current flow in amplifier circuits A 1 and A 2 are determined by the DC biasing current (I) for the amplifier circuits, and an output signal current (S) which is responsive to the differential input signal (INP, INN) applied across nodes 207 and 208 (i.e., S=f(INP−INN)). The current flowing through the high supply terminal of amplifier circuit A 1 corresponds to IA 1 P, where IA 1 P=(I+S). The current flowing through the low supply terminal of amplifier circuit A 1 corresponds to IA 1 N, where IA 1 N=(I−S). Similarly, the current flowing through the high supply terminal of amplifier circuit A 2 corresponds to IA 2 P, where IA 2 P=(I-S), and the current flowing through the low supply terminal of amplifier circuit A 2 corresponds to IA 2 N, where IA 2 N=(I+S).

The first current input (IDP) to drive circuit X 1 at node 202 is responsive to the differential input signal as IDP=[IA 1 P−(2*IA 2 P)]=(−I+3*S), where the 2× factor is from the 2× transistor Q 1 , where I is determined by the DC or bias current portion and S is determined by the difference between INP and INN. Similarly, the first current input (IDN) to drive circuit X 2 at node 209 is responsive to the differential input signal as [IAIN−(2*IA 2 N)]=[−I−(3*S)], where the 2× factor is from the 2× transistor Q 4 . The second current input to drive circuit X 1 at node 211 is responsive to another current input signal (IQ 5 ) from transistor Q 5 , where IQ 5 =IA 2 N=(I+S). The second current input to drive circuit X 2 at node 203 is similarly responsive to yet another current input signal (IQ 2 ) from transistor Q 2 , where IQ 2 =IA 2 P=(I−S).

The first drive circuit (X 1 ) is arranged to combine currents similar to the summer block of FIG. 1 , where the base current (IB 7 ) for output transistor Q 7 is determined by: IB 7 −IDP−IBP−IQ 5 −IBOOSTP=0. IBP is the nominal biasing current for transistor Q 7 , and IBOOSTP is the boosted current which varies based on various operating conditions. As described previously above, the first current input (IDP) has a value given as IDP=(−I+3*S) and the current from transistor (Q 5 ) is has a value given as IQ 5 =(I+S). Therefore, the base current (IB 7 ) for transistor Q 7 can be simplified as: IB 7 =IBP+IBOOSTP+4*S. The boost current (IBOOSTP) varies based upon whether or not the sensed current, IQ 5 =(I+S), has exceeded a threshold (e.g., THP). The boost current is zero (IBOOSTP=0) when the current magnitude for (I+S) is detected as below the requisite threshold (e.g., THP) for boosting the drive to output transistor Q 7 . When the current magnitude for (I+S) is detected as exceeding the requite threshold (e.g., THP), then the boosted current is given as: IBOOSTP=GP (I+S) , where GP corresponds to the gain factor for base current boosting to transistor Q 7 as a function of the quantity (I+S). Thus, the base current (IB 7 ) for transistor Q 7 corresponds to IB 7 =[IBP+(4*S)] for non-boosted conditions, and further corresponds to IB 7 =[IBP+(4*S)+GP (I+S) ] for boosted conditions.

The second drive circuit (X 2 ) is arranged to combine currents similar to the summer block of FIG. 1 , where the base current (IB 8 ) for output transistor Q 8 is determined by: IDN+IBN+IQ 2 +IBOOSTN−IB 8 =0. IBN is the nominal biasing current for transistor Q 8 , and IBOOSTN is the boosted current which varies based on various operating conditions. As described previously above, the first current input (IDN) has a value given as IDN=[−I−(3*S)], and the current from transistor (Q 2 ) is has a value given as IQ 2 =(I−S). Therefore, the base current (IB 8 ) for transistor Q 8 can be simplified as: IB 8 =IBN+IBOOSTN−4*S. The boost current (IBOOSTN) varies based upon whether or not the sensed current, IQ 2 =(I−S), has exceeded a threshold (e.g., THN). The boost current is zero (IBOOSTN=0) when the current magnitude for (I−S) is detected as below the requisite threshold (e.g., THN) for boosting the drive to output transistor Q 8 . When the current magnitude for (I−S) is detected as exceeding the requite threshold (e.g., THN), then the boosted current is given as: IBOOSTN=GN (I−S) , where GN corresponds to the gain factor for base current boosting to transistor Q 8 as a function of the quantity (I−S). Thus, the base current (IB 8 ) for transistor Q 8 is give as IB 8 =[IBN−(4*S)] for non-boosted conditions, and IB 8 =[IBN−(4*S)+GN (I−S) ] for boosted conditions.

In some example implementations, metal-oxide semiconductor (MOS) devices for one or more devices in circuit 200 in lieu of BJT devices. For example, transistors Q 1 , Q 2 and Q 3 can be replaced with a MOS type of transistor without departing from the present disclosure. In this example, the W/L ratio of transistor Q 1 is twice that of either Q 2 or Q 4 , which have matched W/L ratios. Similarly, transistors Q 4 , Q 5 and Q 6 can be replaced with MOS transistors, where the W/L ratio of transistor Q 4 is twice that of either Q 5 or Q 6 , which have matched W/L ratios.

FIG. 3 is a schematic diagram illustrating a further detailed example of the DRIVE N block ( 300 ) for the circuit of FIG. 2 , arranged in accordance with at least some aspects of the present disclosure. The DRIVE N block ( 300 ) comprises a biasing circuit (X 31 ) and a combined threshold detection and base current boost circuit (X 32 ). Node 214 and node 209 are shorted together in this described implementation.

Biasing circuit X 31 includes transistors Q 31 -Q 34 and a current source X 33 . Current source X 33 is coupled between node 201 and node 301 . Transistor Q 31 is a diode configured transistor, with an area of 1*Y, that includes a base coupled to node 301 , a collector coupled to node 301 , and an emitter coupled to node 302 . Transistor Q 32 has an area of 1*Z, and includes a base coupled to node 301 , a collector coupled to node 201 , and an emitter coupled to node 214 . Transistor Q 33 is a diode configured transistor, with an area of 1*Z, that includes a base coupled to node 302 , a collector coupled to node 302 , and an emitter coupled to node 212 . Transistor Q 34 has an area of 1*Z, and includes a base coupled to node 302 , a collector coupled to node 214 , and an emitter coupled to node 212 .

The combined threshold detection and base current boost circuit (X 32 ) includes transistor Q 35 and resistor RTN. Resistor RTN is coupled between node 203 and 214 . Transistor Q 35 has a base coupled to node 203 , a collector coupled to node 201 , and an emitter coupled to node 214 .

In operation, the biasing circuit (X 31 ) is arranged to generate a nominal biasing current (IBN) for transistor Q 8 . The nominal biasing current is proportional to the current (IBNS) provided by current source X 33 , which can be adjusted by a biasing control signal (BIAS CONTROL N). Current IQ 2 from transistor Q 2 , which is given as (I−S), flows through resistor RTN to node 214 . When the current flowing through resistor RTN is low, very little voltage will develop across the resistor (RTN) and transistor Q 35 will be in a cut-off condition (IQ 35 =0). However, transistor Q 35 will become forward biased when sufficient current flows through resistor RTN. Once the biasing voltage for transistor Q 35 exceeds its threshold voltage (VRTN>VTH 35 ), the current from transistor Q 35 will be given as: IQ 35 =GN (I−S) =Beta 35 *(1+IB 35 ). Beta 35 is the forward conduction gain for transistor Q 35 , and IB 35 corresponds to the base current for transistor Q 35 . The base current for transistor Q 35 is determined by the threshold voltage of the transistor (which is temperature and process dependent), the forward biasing voltage across the base-emitter junction from resistor RTN*(I−S), and operating point conditions for transistor Q 35 . The total current resulting from transistors Q 2 and Q 35 is therefore given as: IQ 2 +IQ 35 =(I−S)+GN (I−S) .

In some example implementations, metal-oxide semiconductor (MOS) devices for one or more devices in circuit 300 in lieu of BJT devices. For example, transistor Q 35 can be replaced with a MOS type of transistor without departing from the present disclosure. In this example, IQ 35 will be determined from the drain current of a MOS transistor instead of an emitter current for a BJT device. The drain current for transistor Q 35 is determined by the threshold voltage of the transistor (which is temperature and process dependent), the forward biasing voltage across the gate-source terminals from resistor RTN*(I+S), and operating point conditions for transistor Q 35 .

Output transistor Q 8 can be scaled by a factor of N in size (e.g., N*Y) relative to the biasing transistors Q 31 (1*Y) such that the effects of temperature, process, and power supply variations on the nominal biasing current (IBN) are matched as closely as possible to those for transistor Q 8 .

FIG. 4 is a schematic diagram illustrating a further detailed example of the DRIVE P block for the circuit of FIG. 2 , arranged in accordance with at least some aspects of the present disclosure. The DRIVE P block ( 400 ) comprises a biasing circuit (X 41 ) and a combined threshold detection and base current boost circuit (X 42 ). Node 213 and node 202 are shorted together in this described implementation.

Biasing circuit X 41 includes transistors Q 41 -Q 44 and a current source X 43 . Current source X 43 is coupled between node 401 and node 212 . Transistor Q 41 is a diode configured transistor, with an area of 1*F., that includes a base coupled to node 401 , a collector coupled to node 401 , and an emitter coupled to node 402 . Transistor Q 42 has an area of 1*G, and includes a base coupled to node 401 , a collector coupled to node 401 , and an emitter coupled to node 213 . Transistor Q 43 is a diode configured transistor, with an area of 1*G, that includes a base coupled to node 402 , a collector coupled to node 402 , and an emitter coupled to node 412 . Transistor Q 44 has an area of 1*G, and includes a base coupled to node 402 , a collector coupled to node 213 , and an emitter coupled to node 201 .

The combined threshold detection and base current boost circuit (X 42 ) includes transistor Q 45 and resistor RTP. Resistor RTP is coupled between node 211 and 213 . Transistor Q 45 has a base coupled to node 211 , a collector coupled to node 212 , and an emitter coupled to node 213 .

In operation, the biasing circuit (X 41 ) is arranged to generate a nominal biasing current (IBP) for transistor Q 7 . The nominal biasing current is proportional to the current (IBPS) provided by current source X 43 , which can be adjusted by a biasing control signal (BIAS CONTROLP). Current IQ 5 from transistor Q 5 , which is given as (I+S), flows through resistor RTP from node 213 . When the current flowing through resistor RTP is low, very little voltage will develop across the resistor (RTP) and transistor Q 45 will be in a cut-off condition (IQ 45 =0). However, transistor Q 45 will become forward biased when sufficient current flows through resistor RTP. Once the biasing voltage for transistor Q 45 exceeds its threshold voltage (|VRTP|>|VTH 45 |), the current from transistor Q 45 will be given as: IQ 45 =GP (I+S) =Beta 45 *(1+IB 45 ). Beta 45 is the forward conduction gain for transistor Q 45 , and IB 45 corresponds to the base current for transistor Q 45 . The base current for transistor Q 45 is determined by the threshold voltage of the transistor (which is temperature and process dependent), the forward biasing voltage across the base-emitter junction from resistor RTP*(I+S), and operating point conditions for transistor Q 45 . The total current resulting from transistors Q 5 and Q 45 is therefore given as: IQ 5 +IQ 45 =(I+S)+GP (I+S) .

In some example implementations, metal-oxide semiconductor (MOS) devices for one or more devices in circuit 300 in lieu of BJT devices. For example, transistor Q 35 can be replaced with a MOS type of transistor without departing from the present disclosure. In this example, IQ 35 will be determined from the drain current of a MOS transistor instead of an emitter current for a BJT device. The drain current for transistor Q 35 is determined by the threshold voltage of the transistor (which is temperature and process dependent), the forward biasing voltage across the gate-source terminals from resistor RTN*(I+S), and operating point conditions for transistor Q 35 .

Output transistor Q 7 can be scaled by a factor of M in size (e.g., M*F) relative to the biasing transistors Q 41 (1*F) such that the effects of temperature, process, and power supply variations on the nominal biasing current (IBP) are matched as closely as possible to those for transistor Q 7 .

FIG. 5 is graphical diagram illustrating a performance of an example output stage circuit with extended output range when base current boosting is activated. As noted by the graph ( 500 ), the current continues to increase as the effect of the load is increased from 200 ohms to 100 ohms.

FIG. 6 is graphical diagram illustrating another performance of an example output stage circuit with extended output range when base current boosting is de-activated. As noted by the graph ( 500 ), the current reaches a maximum level as the effect of the load is increased from 200 ohms to 100 ohms in 20 ohm increments. For higher loading effects (i.e., lower values for load resistor RL corresponds to a higher loading effect), the clipping occurs at a lower current levels than that for reduced loading effects (i.e., higher values for load resistor RL).

Although the invention has been described herein by way of exemplary embodiments, variations in the structures and methods described herein may be made without departing from the spirit and scope of the invention. For example, the positioning of the various components may be varied. Individual components and arrangements of components may be substituted as understood to one of skill in the art having read the present disclosure. The various functions of circuits described herein may be separated or combined as required for a particular implementation. Therefore the described physical partitions of circuits and circuit components described herein may be varied to provide the same overall described functions. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.