Semiconductor circuit

1. Field of the Invention

The present invention relates to a differential amplifier. More specifically, the present invention relates to a differential amplifier stabilizing differential output by controlling output impedance.

2. Description of Related Art

FIG. 9 shows a differential operational amplifier configuring an input stage by NMOS-type differential pair and PMOS-type differential pair and an output stage by cascode current mirror as an amplifier including a typical wide-range common-mode input.

A typical Pch input part 1 and Nch input part 2 with respect to a wide-range common-mode input are configured by input terminals IN+ and IN−, Pch MOS transistors M 11 , M 12 , M 14 , and Nch MOS transistors M 9 , M 10 , M 13 . The MOS transistors M 13 and M 14 are set to constant current sources by potential of Vb 4 and Vb 5 that are gate potential.

An output part 3 driving output terminal OUT is configured by cascode-connected Pch MOS transistors M 2 , M 4 , and Nch MOS transistors M 6 , M 8 .

A current mirror circuit 4 which forms current mirror with the output part 3 is configured by cascode-connected Pch MOS transistors M 1 , M 3 , and Nch MOS transistors M 5 , M 7 .

The Pch MOS transistors M 1 and M 2 are set to constant current sources by gate potential Vb 1 , and gate potential Vb 2 is given to the Pch MOS transistors M 3 and M 4 and gate potential Vb 3 is given to the Nch MOS transistors M 5 and M 6 .

Further, in order to give feedback to the gate voltage of each of the Nch MOS transistors M 7 and M 8 that are current mirror current sources by the current flowing in the Pch input part 1 and Nch input part 2 , the gate of each of the MOS transistors M 7 and M 8 is connected to a node X 1 . The node X 1 is connected to a drain of each of the feedback transistors M 3 and M 5 of the current mirror circuit 4 .

If the current flowing in each of the input parts 1 and 2 is changed by changing the input voltage of each of the inputs IN+ and IN−, current flowing in each of the MOS transistors M 3 , M 5 , M 7 of the current mirror circuit 4 is changed. If the gate potential of the MOS transistors M 7 and M 8 is fixed to driving ability having constant current, the MOS transistors M 7 and M 8 behave in non-saturated region when current of each of the MOS transistors M 7 and M 8 is reduced. Therefore, VDS potential is reduced, VGS of each of the MOS transistors M 5 and M 6 increases, and the MOS transistor M 5 behaves in non-saturated region. Therefore, VDS potential is reduced and potential of the output OUT is extremely reduced. In the circuit in FIG. 9 , gate potential of each of the MOS transistors M 7 and M 8 is changed and current amount is regulated in order to stabilize output OUT when potential of the node X 1 is changed. This means that the MOS transistors M 7 and M 8 of the current mirror current source serve an important function in order to stabilize amplitude center of output.

Since effect of the power supply noise has recently become larger and larger as the power supply voltage decreases, output needs to be differentiated as in the circuit configuration of the prior art shown in Japanese Unexamined Patent Application Publication No. 6-237128.

FIG. 10 shows a circuit where PNP transistors and NPN transistors shown in Japanese Unexamined Patent Application Publication No. 6-237128 are replaced with Nch MOS transistors and Pch MOS transistors. In this technique, gate voltage of each of the MOS transistors M 7 and M 8 of the current mirror current source is taken out from central voltage of the cascode-connected transistor of the dummy that is prepared separately from the output current path, thereby realizing stabilized differential output signals OUT+ and OUT−.

However, since the cascode-connected transistor of the dummy that is prepared separately from the output current path is provided, extra current is needed, and high-speed performance and reduced power consumption cannot be realized.

FIGS. 11 and 12 each shows voltage waveform and current waveform of each node of the circuit of prior art in FIG. 10 . FIGS. 11 and 12 are added by the present inventor in order to explain a behavior of prior art in FIG. 10 . In each of FIGS. 11 and 12 , input amplitude potential difference at around power supply voltage of the inputs IN+ and IN− of the circuit of FIG. 10 is indicated in horizontal axis. FIGS. 13 and 14 each shows voltage waveform and current waveform of each node of the circuit of the prior art in FIG. 10 . FIGS. 13 and 14 are added by the present inventor in order to explain a behavior of prior art in FIG. 10 . In each of FIGS. 13 and 14 , input amplitude potential difference at around ground voltage of the inputs IN+ and IN− of the circuit of FIG. 10 is indicated in horizontal axis.

In the circuit of the prior art in FIG. 10 , current I 21 , I 22 , I 23 , and I 24 need to be flowed in feedback transistors M 21 , M 22 , M 23 , and M 24 controlling gate potential of each of the MOS transistors M 7 and M 8 of the current mirror current source. However, these current have no relationship with I 3 and I 4 , which decide transition speed of output terminals OUT+ and OUT−. A circuit used in a cell phone or the like requires low voltage, low current, and high-speed behavior in order to suppress power consumption. Therefore, it is not desired to flow current having no relationship with the transition speed of the output terminals OUT+ and OUT− as in the circuit of the prior art in FIG. 10 .

The potential difference between the output OUT+ and OUT− that are output amplitude is determined by output resistance between the source and the drain of output current I 3 and I 4 and MOS transistors M 15 , M 16 , M 4 , and M 6 . The transition speed of the output is determined by gate capacity of the MOS transistor that receives the signals of output OUT+ and OUT− and the output current I 3 and I 4 .

Therefore, since current of each of the output current I 3 and I 4 reduces, output amplitude and the transition speed are reduced. Since the common-mode input potential of each of the inputs IN+ and IN− is changed from high voltage around power supply voltage to low voltage around ground voltage, the MOS transistors M 15 , M 16 , M 4 , and M 6 behave in saturated state. Therefore, the output resistance between the source and the drain is substantially constant and the gate capacity of the MOS transistor receiving the signals of outputs OUT+ and OUT− is constant. However, in the circuit of the prior art, the common-mode input potential of each of the inputs IN+ and IN− is changed from high voltage around power supply voltage to low voltage around ground voltage as described above and the current change of each of the output current I 3 and I 4 is (I 1 −I 10 )/2−I 1 /2=−I 10 /2, (I 2 −I 9 )/2−I 2 /2=−I 9 /2. Therefore, the output amplitude of the circuit output and the transition speed are changed due to the change of the common-mode input potential. Because the current change of each of the output current I 3 and I 4 changes the amplitude voltage and the transition speed of the outputs OUT+ and OUT−, the operation speed of the circuit receiving the signals of the outputs OUT+ and OUT− is changed. In the typical MOS transistor circuit, the operation speed is decreased when the amplitude voltage of the input signal is small and the transition speed is low. Therefore, current of the output current I 3 and I 4 changes due to the change of the common-mode input potential and decrease of the operation speed of the circuit receiving the signals of the outputs OUT+and OUT− is a problem.

An amplifier including a differential output stage and a differential input stage, in which the differential output stage includes a first current path and a second current path outputting differential signals and connected between a first power supply and a second power supply, the first current path includes a first resistance element between the first power supply and a first node, a first transistor and a second transistor between the first node and a second node, and a second resistance element between the second node and the second power supply, the second current path includes a third resistance element between the first power supply and a third node, a third transistor and a fourth transistor between the third node and a fourth node, and a fourth resistance element between the fourth node and the second power supply, a gate of the first transistor is connected to the fourth node, a gate of the second transistor is connected to the third node, a gate of the third transistor is connected to the second node, a gate of the fourth transistor is connected to the first node, and current output from the differential input stage is connected to the first node and the third node.

According to the amplifier of the present invention, by connecting the gate of the transistor driving the output and a connecting point forming mirror configuration without using the feedback transistor, it is possible to give feedback corresponding to the common-mode input voltage and achieve the differential output without increasing current.

According to the present invention, it is possible to prevent current flowing in the output transistor from being changed due to change of the common-mode input potential and operation speed of the circuit from being reduced.

The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:

FIG. 1 is an example of a circuit configuration of a semiconductor device according to the present invention;

FIG. 2 is another example of the circuit configuration of the semiconductor device according to the present invention;

FIG. 3 is another example of the circuit configuration of the semiconductor device according to the present invention;

FIG. 4 is an example of an output when voltage around power supply voltage is applied to the input terminal of the circuit of FIG. 1 and a voltage waveform of each node;

FIG. 5 is an example of an output when voltage around power supply voltage is applied to the input terminal of the circuit of FIG. 1 and a voltage waveform of each node;

FIG. 6 is an example of an output when voltage around ground voltage is applied to the input terminal of the circuit of FIG. 1 and a voltage waveform of each node;

FIG. 7 is an example of an output when voltage around ground voltage is applied to the input terminal of the circuit of FIG. 1 and a voltage waveform of each node;

FIG. 8 is an example of a circuit configuration of the semiconductor device according to another embodiment;

FIG. 9 is an example of a circuit configuration of a semiconductor device according to a related art;

FIG. 10 is an example of the circuit configuration of the semiconductor device according to the related art;

FIG. 11 is an example of an output when voltage around power supply voltage is applied to the input terminal of the circuit of FIG. 10 and a voltage waveform of each node;

FIG. 12 is an example of an output when voltage around power supply voltage is applied to the input terminal of the circuit of FIG. 10 and a voltage waveform of each node;

FIG. 13 is an example of an output when voltage around ground voltage is applied to the input terminal of the circuit of FIG. 10 and a voltage waveform of each node; and

FIG. 14 is an example of an output when voltage around ground voltage is applied to the input terminal of the circuit of FIG. 10 and a voltage waveform of each node.

The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.

Hereinafter, the specific embodiment to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 shows an example of a configuration of a differential output amplifier according to the present embodiment.

A differential output amplifier 100 includes an input terminal 11 (input IN+), an input terminal 12 (input IN−), and a Pch input part 1 and an Nch input part 2 with respect to wide range common-mode input, an output part 7 , an output terminal 21 (output OUT+), and an output terminal 22 (output OUT−).

The Pch input part 1 includes Pch MOS transistors M 11 , M 12 , and M 14 . The MOS transistor M 11 has a gate connected to the input terminal 12 , a drain connected to a node X 6 , and a source connected to a drain of the MOS transistor M 14 . The MOS transistor M 12 has a gate connected to the input terminal 11 , a drain connected to a node X 5 , and a source connected to a drain of the MOS transistor M 14 . The MOS transistor M 14 has a gate to which potential Vb 5 is input, a drain connected to sources of the MOS transistors M 11 and M 12 , and a source connected to high-potential side power supply. The MOS transistor M 14 is set to a constant current source by the potential of Vb 5 which is gate potential.

The Nch input part 2 includes Nch MOS transistors M 9 , M 10 , and M 13 . The MOS transistor M 9 has a gate connected to the input terminal 12 , a drain connected to a node X 4 , and a source connected to a drain of the MOS transistor M 13 . The MOS transistor M 10 has a gate connected to the input terminal 11 , a drain connected to a node X 3 , and a source connected to a drain of the MOS transistor M 13 . The MOS transistor M 13 has a gate to which potential Vb 4 is input, a drain connected to sources of the MOS transistors M 9 and M 10 , and a source connected to low-potential side power supply VSS. The MOS transistor M 13 is set to a constant current source by the potential of Vb 4 which is gate potential.

The output part 7 includes Pch MOS transistors M 17 , M 18 , M 15 , and M 4 , and Nch MOS transistors M 16 , M 6 , M 19 , and M 20 . The output part 7 drives the output terminals 21 and 22 . The MOS transistor M 17 has a gate to which Vb 1 is input, a source connected to high-potential side power supply VDD, and a drain connected to the node X 3 . The MOS transistor M 18 has a gate to which Vb 1 is input, a source connected to high-potential side power supply VDD, and a drain connected to the node X 4 . The MOS transistor M 15 has a gate connected to the node X 6 , a source connected to the node X 3 , and a drain connected to the output terminal 22 . The MOS transistor M 4 has a gate connected to the node X 5 , a source connected to the node X 4 , and a drain connected to the output terminal 21 . The MOS transistor M 16 has a gate connected to the node X 4 , a source connected to the node X 5 , and a drain connected to the output terminal 22 . The MOS transistor M 6 has a gate connected to the node X 3 , a source connected to the node X 6 , and a drain connected to the output terminal 21 . The MOS transistor M 19 has a gate to which Vb 2 is input, a source connected to low-potential side power supply VSS, and a drain connected to the node X 5 . The MOS transistor M 20 has a gate to which Vb 2 is input, a source connected to low-potential side power supply VSS, and a drain connected to the node X 6 . The MOS transistors M 17 , M 15 , M 16 , M 19 , and M 18 , M 4 , M 6 , M 20 are cascode connected.

Current I 11 flows in the MOS transistor M 11 and current I 12 flows in the MOS transistor M 12 . The MOS transistors M 11 and M 12 form the Pch input part 1 . Current I 9 flows in the MOS transistor M 9 and current I 10 flows in the MOS transistor M 10 . The MOS transistor M 9 and the MOS transistor M 10 form the Nch input part 2 .

Current I 17 flows in the MOS transistor M 17 , current I 18 flows in the MOS transistor M 18 , current I 3 flows in the MOS transistors M 15 and M 16 , current I 4 flows in the MOS transistors M 4 , M 6 , current I 19 flows in the MOS transistor M 19 , and current I 20 flows in the MOS transistor M 20 . These transistors form the output part 7 .

Dimension of each of the transistors is set so that I 9 and I 10 are equal to each other, I 11 and I 12 are equal to each other, I 17 and I 18 are equal to each other, I 3 and I 4 are equal to each other, and I 19 and I 20 are equal to each other when the same potential is input to the input IN+ and IN−. In other words, the MOS transistors M 9 and M 10 , the MOS transistors M 11 and M 12 , the MOS transistors M 17 and M 18 , the MOS transistors M 15 and M 4 , the MOS transistors M 16 and M 6 , and the MOS transistors M 19 and M 20 are each formed in the same dimension.

Although VGS of each of the MOS transistors M 17 , M 18 , and M 19 , M 20 is set to be constant by Vb 1 and Vb 2 , current of each of I 9 , I 10 , and I 11 , I 12 changes due to the common-mode input potential change of the input IN+ and input IN−. Therefore, I 17 , I 18 , I 19 , and I 20 also change, and the MOS transistors M 17 , M 18 , and M 19 , M 20 change from saturated state (low current source) to non-saturated state (resistor) depending on the change of current.

In the circuit in FIG. 1 , feedback with respect to the common-mode input voltage is given to the gate of each of the output drive transistors M 15 , M 4 , M 16 , and M 6 by the cascode-connected transistor of each negative phase output.

Hereinafter, the behavior of the differential output amplifier in FIG. 1 will be described. When high voltage where common-mode input potential is around power supply voltage is applied to the input terminals 11 and 12 , the Pch input part 1 is turned off and I 11 and I 12 flowing in the MOS transistors M 11 and M 12 are 0 A. The Nch input 2 is turned on and current I 9 and I 10 flow in the MOS transistors M 9 and M 10 . Therefore, when high voltage where common-mode input potential is around power supply voltage is applied, this state is shown in FIG. 2 . Hereinafter, description will be made with reference to a circuit configuration shown in FIG. 2 .

The Nch input 2 is turned on and potential of each of the nodes X 3 and X 4 of the output part 7 is reduced. The same current I 3 and I 4 flow in the MOS transistors M 15 , M 16 , and M 4 , M 6 . Therefore, potential of each of the nodes X 6 and X 5 is reduced in order to secure VGS of each transistor.

The MOS transistor M 17 is in saturated state (constant current source) and current I 17 flows in the MOS transistor M 17 . Current flowing in the drive transistors M 15 , M 16 , and M 19 of the output OUT− is current I 3 as I 17 −I 10 . Similarly, the MOS transistor M 18 is in saturated state (constant current source) and current I 18 flows in the MOS transistor M 18 . Current flowing in the drive transistors M 4 , M 6 , and M 8 of the output OUT+ is current I 4 as I 18 −I 9 .

When low voltage where common-mode input potential is around ground voltage is applied to the input terminals 11 and 12 , the Nch input part 2 is turned off and I 9 and I 10 flowing in the MOS transistors M 9 and M 10 are 0 A. The Pch input part 1 is turned on and current I 11 and I 12 flow in the MOS transistors M 11 and M 12 . Therefore, when low voltage where common-mode input potential is around ground voltage is applied, this state is shown in FIG. 3 . Hereinafter, description will be made with reference to a circuit configuration shown in FIG. 3 .

The Pch input 1 is turned on and potential of each of the nodes X 6 and X 5 of the output part 7 is increased. The same current I 3 and I 4 flow in the MOS transistors M 15 , M 16 , and M 4 , M 6 . Therefore, potential of each of the nodes X 3 and X 4 is also increased in order to secure VGS of each transistor.

The MOS transistor M 19 is in saturated state (constant current source) and current I 19 flows in the MOS transistor M 19 . Current flowing in the drive transistors M 15 , M 16 , and M 17 of the output OUT− is current I 3 as I 19 −I 12 . Similarly, the MOS transistor M 20 is in saturated state and current I 8 flows in the MOS transistor M 20 . Current flowing in the drive transistors M 4 , M 6 , and M 18 of the output OUT+ is current I 4 as I 20 −I 11 .

From above description, it can be understood that the current I 3 and I 4 due to the difference of the common-mode input potential become equal to each other by making current of each of the MOS transistors M 17 , M 18 , M 19 , and M 20 in saturated state and current of each of M 13 and M 14 in saturated region the same (I 3 =I 17 −I 10 =I 19 −I 12 , I 4 =I 18 −I 9 =I 20 −I 11 ). Since current I 3 and I 4 are made equal to each other, VGS of each of the M 15 , M 4 , M 16 , and M 6 is made equal as well.

FIGS. 4 and 5 each shows a case where signal of differential small-amplitude is input to the input terminals 11 and 12 in high voltage where common-mode input potential is around power supply voltage. In FIG. 4 , a horizontal axis indicates potential difference between the input IN+ and the input IN−, and a vertical axis indicates voltage waveform of each node. In FIG. 5 , a horizontal axis indicates potential difference between the input IN+ and the input IN−, and a vertical axis indicates current waveform of each transistor. When high voltage where common-mode input potential is around power supply voltage is applied, this state can be shown in FIG. 2 .

A points in FIGS. 4 and 5 , which means a case where the input IN+ is in power supply voltage and the input IN− is in potential several tens of mV lower than power supply voltage will be described. VGS of each of the MOS transistors M 11 and M 12 is made equal to or below several tens of mV and therefore completely turned off. Therefore, Pch input part 1 is turned off, and I 11 and I 12 are 0 mA although not shown in the drawing. VGS of each of the MOS transistors M 9 and M 10 is sufficiently high potential, current I 9 and I 10 flow, and potential of each of the nodes X 3 and X 4 is reduced. Since VDS of each of the MOS transistors M 17 and M 18 is sufficiently high, the MOS transistors M 17 and M 18 are constant current sources, and substantially the same current I 17 and I 18 are flowed.

Since the transistor M 10 has higher VGS than the transistor M 9 does, current of I 10 is larger than current of I 9 , potential of the node X 3 is lower than the potential of the node X 4 , and current of I 4 is larger than current of I 3 . Since I 11 and I 12 are 0 mA, current I 19 flowing in the MOS transistors M 19 and M 20 is equal to I 3 and I 20 is equal to I 4 . Since current of I 20 is larger than current of I 19 , the MOS transistor M 19 is in non-saturated state and VDS is reduced. Therefore, potential of the node X 5 becomes lower than potential of the node X 6 .

From above description, it can be seen that output drive current I 4 is larger than I 3 , potential of the node X 4 is higher than that of X 3 , potential of the node X 6 is higher than that of X 5 , VGS of the MOS transistor M 15 is lower than VGS of the MOS transistor M 4 , and VGS of the MOS transistor M 16 is higher than VGS of the MOS transistor M 6 . Therefore, potential of the output OUT+ is higher than potential of OUT−.

B points in FIGS. 4 and 5 , which means a case where potential of the input IN+ is in potential several tens of mV lower than the power supply voltage and potential of IN− is power supply voltage will be described. In this case, mirror circuit is formed with respect to the case where the potential of the IN+ is in power supply voltage and the potential of the IN− is several tens of mV lower than the power supply voltage. Therefore, the outputs OUT− and the OUT+ are inverted.

Now, FIGS. 6 and 7 each shows a case where signal of the differential small-amplitude is input to the input terminals 11 and 12 in low voltage where common-mode input potential is around ground voltage. In FIG. 6 , a horizontal axis indicates potential difference between the input IN+ and the input IN− and a vertical axis indicates potential waveform of each node. In FIG. 7 , a horizontal axis indicates potential difference between the input IN+ and the input IN− as in FIG. 13 and a vertical axis indicates current waveform of each transistor. As described above, when high voltage where the common-mode input potential is around ground voltage is applied, this state can be shown in FIG. 3 .

A points in FIGS. 6 and 7 , which means a case where the IN+ is several tens of mV and the IN− is 0.0V will be described. VGS of each of the MOS transistors M 9 and M 10 is made equal to or below several tens of mV and therefore completely turned off. Therefore, Nch input part 2 is turned off, and I 9 and I 10 are 0 mA. VGS of each of the MOS transistors M 11 and M 12 is sufficiently high potential, current I 11 and I 12 flow, and potential of each of the nodes X 5 and X 6 is increased. Since VDS of each of the MOS transistors M 19 and M 20 is sufficiently high, the MOS transistors M 19 and M 20 are constant current sources, and substantially the same current I 19 and I 20 are flowed.

Since the MOS transistor M 11 has higher VGS than the transistor M 12 does, current of I 11 is larger than current of I 12 , potential of the node X 6 is higher than the potential of the node X 5 , and current of I 3 is larger than current of I 4 . Since I 9 and I 10 are 0 mA, current I 17 flowing in the MOS transistors M 17 and M 18 is equal to I 3 and I 18 is equal to I 4 . Since current of I 17 is larger than current of I 18 , the MOS transistor M 17 is in non-saturated state and VDS is reduced. Therefore, potential of the node X 3 becomes lower than potential of the node X 4 .

From above description, it can be seen that output drive current I 3 is larger than I 4 , potential of the node X 4 is higher than that of X 3 , potential of the node X 6 is higher than that of X 5 , VGS of the MOS transistor M 15 is lower than VGS of the MOS transistor M 4 , and VGS of the MOS transistor M 16 is higher than VGS of the MOS transistor M 6 . Therefore, potential of the output OUT+ is higher than potential of OUT−.

B points in FIGS. 6 and 7 , which means a case where potential of the input IN+ is 0V and potential of the IN− is several tens of mV will be described. In this case, mirror circuit is formed with respect to the case where the potential of the IN+ is in power supply voltage and the potential of the IN− is several tens of mV lower than the power supply voltage. Therefore, the output OUT− and the OUT+ are inverted.

Hereinafter, the effect of the differential output amplifier of the present embodiment in FIG. 1 will be described compared with the circuit of the prior art in FIG. 10 .

As described as the problems of the prior art, the circuit operation speed is greatly influenced by the amplitude of each of the outputs OUT+ and OUT− and the transition speed. The amplitude of each of the outputs OUT+ and OUT− and transition speed are greatly influenced by the output currents I 3 and I 4 .

According to the circuit of the prior art in FIG. 10 , the feedback circuit 6 is provided in addition to the output current I 3 and I 4 and current of I 21 +I 22 (=I 23 +I 24 ) needs to be flowed. On the contrary, in the circuit of the present embodiment in FIG. 1 , only the output current I 3 and I 4 need to be flowed. Therefore, power consumption can be reduced.

Further, in the circuit of the present embodiment of FIG. 1 , regardless of input common-mode voltage, only an expression I 3 =I 17 −I 10 =I 19 −I 12 needs to be satisfied in order to make the output current I 3 constant. Therefore, current I 17 of the MOS transistor M 17 in saturated state and saturated current I 19 of the MOS transistor M 19 are made to be equal to each other and the current of the Pch input 1 and the current of the Nch input 2 are made to be equal to each other.

Similarly, only an expression I 4 =I 18 −I 9 =I 20 −I 11 needs to be satisfied in order to make the output current I 4 constant. Therefore, current I 18 of the MOS transistor M 18 in saturated state and saturated current I 20 of the MOS transistor M 20 are made to be equal to each other and the current of the Pch input 1 and the current of the Nch input 2 are made to be equal to each other. Therefore, fluctuation of the output current I 3 and I 4 can be made 0 in calculation.

Therefore, by performing feedback to the output drive transistor with respect to input common-mode voltage without adding elements or current paths, current increase can be suppressed and output amplitude and transition speed can be stabilized.

It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. For example, FIG. 8 shows the circuit configuration of the first embodiment. In the circuit configuration in FIG. 8 , the MOS transistors M 1 , M 2 , M 7 , and M 8 are changed to resistors R 1 , R 2 , R 3 , and R 4 . In the circuit of the present embodiment, the same effect can be obtained even in the circuit configuration that is suited for low voltage operation.