CMOS image sensor

This application claims priority from Korean Patent Application No. 10-2007-0077016 filed on Jul. 31, 2007 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

1. Field of the Invention

The present invention relates to a semiconductor technology, and, in particular, to a CMOS (Complementary Metal-Oxide Semiconductor) image sensor that has an expanded dynamic range.

2. Description of the Related Art

In recent years, high-resolution camera-equipped apparatuses, such as digital cameras, camera-equipped cellular phones, and surveillance cameras, have become widespread. As an imaging device for such a camera, a CCD (Charge Coupled Device) or a CMOS (Complementary Metal-Oxide Semiconductor) image sensor is used.

The CMOS image sensor has features of ease of manufacturing and low cost compared with the CCD, and thus it is popular in solid-state imaging. Further, a unit pixel of the CMOS image sensor is composed of MOS transistors, and thus it can be implemented in a smaller area than that of the CCD, thereby providing high resolution. In addition, signal-processing logic can be formed in an image circuit, in which pixels are formed, such that the image circuit and the signal-processing circuit can be incorporated into a single body.

Since the CMOS image sensor generally has a dynamic range of approximately 60 dB, there is a limit to generating an image in a wide illuminance range. For this reason, in a screen having a bright image and a dark image, a bright portion may be saturated and become white, and a dark portion may not be expressed.

In addition, as a digital camera or a camera-equipped cellular phone is reduced in size, low-voltage driving is performed due to demands for reducing a unit area in the pixels of the image sensor and realizing low power consumption, which makes it difficult to ensure a sufficient dynamic range.

In the related art, in order to solve the above-described problems, the structure shown in FIG. 1 is used to expand the dynamic range of the image sensor.

FIG. 1 is a circuit diagram showing a unit pixel having a general 4-T structure in a CMOS image sensor.

Referring to FIG. 1 , the pixel having a 4-T structure is composed of one photodiode (PD) 110 , and four NMOS transistors, that is, a transfer transistor (Tx) 120 , a reset transistor (Rx) 122 , a drive transistor (Dx) 124 , and a select transistor (Sx) 126 .

In a state where the transfer transistor (Tx) 120 is turned off, if light is irradiated onto the surface of the photodiode (PD) 110 , holes and electrons are separated. Then, the holes flow to a ground to be then removed, and electrons accumulate in the photodiode (PD) 110 .

The transfer transistor (Tx) 120 functions as a transmission channel to apply a predetermined voltage to a gate 121 of the transfer transistor (Tx) 120 , and to transfer the electrons accumulated in the photodiode (PD) 110 by light to a floating diffusion region (FD) 130 . Further, the transfer transistor (Tx) 120 performs a reset function to completely remove the electrons from the photodiode (PD) 110 .

The reset transistor (Rx) 122 resets the floating diffusion region (FD) 130 by setting the potential of the floating diffusion region (FD) 130 to a desired value and eliminating charge. That is, the reset transistor (Rx) 122 eliminates the charge that has accumulated in the floating diffusion region (FD) 130 for signal detection.

The drive transistor (Dx) 124 operates according to the charge accumulated in the floating diffusion region (FD) 130 , and functions as a buffer amplifier having the configuration of a source follower. The select transistor (Sx) 126 is switched for addressing.

If charge accumulates in the photodiode (PD) 110 , a high voltage is applied to a gate of the reset transistor (Rx) 122 to set the voltage of the floating diffusion region (FD) 130 to V DD , and then a corresponding voltage value is read. Next, a high voltage is applied to the gate of the transfer transistor (Tx) 120 to transfer the charge that has accumulated in the photodiode (PD) 110 to the floating diffusion region (FD) 130 , a corresponding voltage value is read, and subsequently a difference between the read voltage values is read.

In this structure, in order to expand the dynamic range, the capacitance of the floating diffusion region (FD) 130 is increased to receive the charge from the photodiode (PD) 110 without overflow.

However, if the capacitance is increased, sensitivity of the CMOS image sensor is decreased, and a dark image may not be expressed. Therefore, it is not desirable to simply increase the capacitance of the floating diffusion region (FD) 130 .

An object of the present invention is to provide a CMOS image sensor, in which a plurality of floating diffusion regions are provided in a pixel, having the advantage of obtaining an expanded dynamic range without sacrificing sensitivity.

Objects of the present invention are not limited to those mentioned above, and other objects of the present invention will be apparent to those skilled in the art through the following description.

According to the embodiments of the present invention, a plurality of floating diffusion regions are provided in a pixel to have different capacitance, and thus an expanded dynamic range can be obtained without sacrificing sensitivity.

According to the embodiments of the present invention, the floating diffusion regions are separated from each other. Therefore, at low illuminance, a vivid image can be obtained with high sensitivity. In addition, at high illuminance, a vivid image can be obtained without causing an image to be saturated and whitened.

The above and other features and advantages of the present invention will become apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram showing a unit pixel having a general 4-T structure in a CMOS image sensor;

FIG. 2 is a circuit diagram showing a unit pixel of a CMOS image sensor having two floating diffusion regions according to an embodiment of the present invention;

FIG. 3 is a timing chart illustrating the operation of the circuit shown in FIG. 2 ;

FIG. 4 is a circuit diagram showing the structure of a CMOS image sensor according to another embodiment of the present invention;

FIG. 5 is a circuit diagram showing a unit pixel of a CMOS image sensor according to still another embodiment of the present invention; and

FIG. 6 is a timing chart illustrating the operation of the circuit shown in FIG. 5 .

Advantages and features of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the present invention to those skilled in the art, and the present invention will only be defined by the appended claims.

FIG. 2 is a circuit diagram showing a unit pixel of a CMOS image sensor having two floating diffusion regions according to an embodiment of the present invention.

Referring to FIG. 2 , a CMOS image sensor according to an embodiment of the present invention has a first floating diffusion region (FD 1 ) 230 a and a second floating diffusion region (FD 2 ) 230 b per unit pixel. FD 1 230 a and FD 2 230 b are separated from each other by a second transfer transistor (Tx 2 ) 220 b . In addition, a first transfer transistor (Tx 1 ) 220 a is disposed between a photodiode (PD) 210 and FD 1 230 a.

The photodiode (PD) 210 functions as a light-receiving unit that converts light into charge. It should be understood that any unit can be applied to the present invention insofar as it is a light-receiving unit that can convert light into charge.

FD 1 230 a is connected to a gate of a first drive transistor (Dx 1 ) 224 a and a first reset transistor (Rx 1 ) 222 a , and FD 2 230 b is connected to a gate of a second drive transistor (Dx 2 ) 224 b and a second reset transistor (Rx 2 ) 222 b.

A final image for a pixel is obtained by synthesizing signals Vout 1 and Vout 2 that are output from a first select transistor (Sx 1 ) 226 a and a second select transistor (Sx 2 ) 226 b.

The transfer transistors 220 a and 220 b , the reset transistors 222 a and 222 b , the drive transistors 224 a and 224 b , and the select transistors 226 a and 226 b shown in FIG. 2 have the same functions as the transistors shown in FIG. 1 .

Referring to FIG. 2 , FD 1 230 a is disposed close to the four transistors Tx 1 220 a , Tx 2 220 b , Rx 1 222 a , and Dx 1 224 a , and thus it has a capacitance larger than FD 2 230 b that is disposed close to the three transistors Tx 2 220 b , Rx 2 222 b , and Dx 2 224 b.

At this time, the capacitance of FD 1 230 a is maximized within a predetermined range to receive large amounts of charge while the sensitivity is low. Further, the capacitance of FD 2 230 b is minimized within the predetermined range to increase the sensitivity while not receiving large amounts of charge.

In such a manner, a signal having a wide dynamic range with respect to illuminance but low sensitivity can be acquired in FD 1 230 a , and a signal having a small dynamic range with respect to illuminance but high sensitivity can be acquired in FD 2 230 b.

That is, the charge accumulated in the photodiode 210 is transmitted to FD 1 230 a through the first transfer transistor (Tx 1 ) 220 a to obtain a wide dynamic range signal, and then the wide dynamic range signal is output as Vout 1 through Dx 1 224 a and Sx 1 226 a . Next, the wide dynamic range signal obtained in FD 1 230 a is transmitted to FD 2 230 b through the second transfer transistor (Tx 2 ) 220 b to obtain a high-sensitive signal, and then the high-sensitivity signal is outputs as Vout 2 through Dx 2 224 b and Sx 2 226 b.

The signals Vout 1 and Vout 2 are synthesized, thereby obtaining the final image for a pixel.

FIG. 3 is a timing chart illustrating the operation of the circuit shown in FIG. 2 .

Referring to FIG. 3 , Sx 1 226 a is turned on at time t 0 when a selection control signal rises, and a column including a corresponding CMOS pixel element is selected.

Next, Rx 1 222 a is turned on at time t 1 to reset FD 1 230 a to V DD , and then a corresponding voltage value is read.

At time t 2 , a high voltage is applied to a gate of the Tx 1 220 a to transmit the charge accumulated in the photodiode 210 to FD 1 230 a , and a corresponding voltage value is read. A difference between the two voltage values is output as a final signal value. That is, the output signal covers a wide range of illuminance, and thus a vivid image can be obtained with high illuminance without causing saturation.

After time t 2 , Sx 2 226 b is turned on, and a column including a corresponding CMOS pixel element is selected. In this case, the same column is selected by Sx 1 226 a and Sx 2 226 b.

At time t 3 , the Rx 2 222 b is turned on to rest FD 2 230 b to V DD , and then a corresponding voltage value is read. Next, at time t 4 , a high voltage is applied to a gate of the Tx 2 220 b to transmit the charge accumulated in FD 1 230 a to FD 2 230 b , and then a corresponding voltage value is read. A difference between the two voltage values is output as a final signal value. In FD 2 230 b , a high-sensitivity signal is output due to low capacitance, such that a vivid image can be obtained with low illuminance.

As a result, the two final signal values are synthesized after a time t 4 , such that an illuminance range can be expanded while the sensitivity of the CMOS image sensor can be maintained.

FIG. 4 is a circuit diagram showing the structure of a CMOS image sensor according to another embodiment of the present invention. Referring to FIG. 4 , images from two pixels of the CMOS image sensor are processed by a single circuit.

That is, an image-processing circuit block 450 shown in FIG. 4 has the same configuration and function as the circuit shown in FIG. 2 . In FIG. 4 , however, a first floating region (FD 1 ) 430 a is connected to a third transfer transistor (Tx 3 ) 420 c , and Tx 3 420 c is connected to a second photodiode (PD 2 ) 410 b.

A first photodiode (PD 1 ) 410 a and a second photodiode (PD 2 ) 410 b respectively function as light-receiving units of first and second pixels in the CMOS image sensor.

For example, charge collected by the PD 1 410 a is transmitted to FD 1 430 a and FD 2 430 b under the control of Tx 1 420 a , thereby obtaining output signals Vout 1 and Vout 2 for the first pixel. In this case, since Tx 3 420 c does not operate, charge collected in the PD 2 410 b is not transmitted to FD 1 430 a.

Subsequently, the Tx 1 420 a does not operate and the Tx 3 420 c operates. Then, the charge collected in the PD 2 410 b is transmitted to FD 1 430 a and FD 2 430 b , thereby obtaining output signals Vout 1 and Vout 2 for the second pixel. In this case, since the Tx 1 420 a does not operate, the charge collected in the PD 1 410 a is not transmitted to FD 1 430 a.

That is, a single image-processing circuit block 450 is shared by two light-receiving units, and thus the integration of the CMOS image sensor can be increased.

FIG. 5 is a circuit diagram showing a unit pixel of a CMOS image sensor according to still another embodiment of the present invention.

Referring to FIG. 5 , it can be seen that the circuit shown in FIG. 5 has the same configuration as the circuit shown in FIG. 2 , excluding a capacitor 550 .

The capacitor 550 is connected to a gate of a Dx 2 524 b , that is, a FD 2 530 b , to increase capacitance of FD 2 530 b . Accordingly, FD 1 530 a functions as a high-sensitivity output unit, and FD 2 530 b functions as a wide dynamic range/low-sensitivity output unit, unlike the circuit shown in FIG. 2 , in which FD 1 230 a functions as a wide dynamic range output signal and FD 2 230 b functions as a high-sensitivity output unit.

Therefore, referring to FIG. 5 , the wide dynamic range signal is output as Vout 2 , and the high-sensitivity signal is output as Vout 1 .

FIG. 6 is a timing chart illustrating the operation of the circuit shown in FIG. 5 .

Referring to FIG. 6 , Sx 1 526 a and the Sx 2 526 b are simultaneously turned on at time t 0 when the selection control signal rises, and a column including a corresponding CMOS pixel element is selected.

Next, at time t 1 , the reset transistor (Rx 1 ) 522 a and the reset transistor (Rx 2 ) 522 b are simultaneously turned on to set FD 1 530 a and FD 2 530 b to V DD , and then a corresponding voltage value is read.

At time t 2 , a voltage V h is applied to the first transfer transistor (Tx 1 ) 520 a , and a voltage V m is applied to the second transfer transistor (Tx 2 ) 520 b . At this time, the voltage V m is lower than the voltage V h .

Subsequently, at time t 2 , FD 2 530 b receives the excessive charge in FD 1 530 a , such that a high-sensitivity signal is obtained from FD 1 530 a , and a low-sensitivity/wide dynamic range signal is obtained from FD 2 530 b . Next, the two signals are synthesized, thereby acquiring a wide dynamic range/high-sensitivity signal.

Similar to the CMOS image sensor shown in FIG. 4 , the circuit shown in FIG. 5 can be shared by at least two light-receiving units. This change can be easily made by those skilled in the art from FIG. 4 .

Although the present invention has been described in connection with the exemplary embodiments of the present invention, it will be apparent to those skilled in the art that various modifications and changes may be made thereto without departing from the scope and spirit of the present invention. Therefore, it should be understood that the above embodiments are not limitative, but illustrative in all aspects.