Power supply circuit

This application claims priority from German Patent Application No. 10 2007 014 398.4, filed 26 Mar. 2007.

The present invention generally relates to a power supply circuit. More particularly, but not exclusively, the present invention relates to a circuit for supplying power to a high power white LED flashlight, with minimized peak current from the power supply battery.

White LEDs are often used in mobile telephones, for example as flashlights for a digital camera integrated in the phone resulting in high peak power needs. This is especially the case when they are used to provide an instantaneous flashlight. Furthermore, it is often the case that several such LEDs are provided. When the LEDs are switched on, they draw a large amount of power from the battery provided as the power supply.

The present invention has been devised with the foregoing in mind. The present invention provides a power supply circuit for supplying current to a pair of white LEDs connected in series. The circuit comprises a DC-DC power converter and a charge pump coupled to an output of the DC-DC power converter. A super capacitor is coupled to the charge pump and is adapted to be charged to a voltage on top of the voltage at the converter output during a first mode of operation. In a second mode of operation, the super capacitor is discharged through the LEDs so that the LEDs flash. A control stage switches between the first mode of operation and the second mode of operation. This means that the circuit provides enough power to satisfy the high-power requirements of white LEDs, while drawing a minimum amount of current from the power supply battery, which is particularly important in portable electronic devices.

The charge pump preferably comprises an inverter with a supply input connected to the converter output and an output connected to a capacitor of the charge pump. The full output voltage of the converter is therefore used as an input to the charge pump and the voltage generated by the charge pump is added to the output voltage of the converter.

A soft start scheme can be implemented by the control stage including a soft-start pre-charge phase, which limits the inrush current during start-up of the power supply circuit. The control stage can be adapted to switch from the first mode to the second mode of operation only after the converter has completed the soft-start pre-charge phase, for example if the output voltage of the power converter reaches a predetermined voltage level. A possible configuration for the control stage is that it has a first error amplifier with a first input coupled to a first reference voltage source and a second input coupled to a current sink in the current path of the LEDs. A second error amplifier then has a first input coupled to a second reference voltage source and a second input coupled to the output of the power converter. Switching means then connect a control input of a pulse width modulator in the converter with the output of the first error amplifier in a current regulation mode and with the output of the second error amplifier in a voltage regulation control mode.

Preferably, the super capacitor has a capacitance of 0.1 F or greater. and a current regulator is provided in the power supply circuit, which is operable to limit the current through the LEDs during the second “flash” mode of operation.

The power supply circuit according to the invention can be used in any electronic device where it is required to have multi-die white LEDs and is particularly useful in mobile phones having digital cameras with flash. The present invention uses only limited peak power from the battery of such a device so does not place high demands on the power supply.

Further advantages and characteristics of the invention ensue from a description below of a preferred embodiment, and from the accompanying drawing, in which:

The sole FIGURE is a circuit diagram of a power supply circuit according to the invention.

Referring now to the FIGURE, an LED circuit comprises terminals VIN and GND, which are operable to be connected to a voltage supply (not shown), which can be a battery in a portable electronic device. The terminal VIN is connected to the input node of a DC-DC power converter and the terminal GND is connected to ground. The power converter comprises a capacitor C 05 and an inductor L 01 , which form a storage/filtering circuit well-known in the art, operable to provide a constant voltage. The capacitor C 05 is connected between the output node of the power converter and ground and the inductor L 01 is connected between the input node of the power converter and a node which is connected to the drain terminal of a MOS transistor MN 01 and the drain terminal of a MOS transistor MN 02 .

The source terminal of the transistor MN 01 is connected to ground and the drain terminal of the transistor MN 02 is connected to one plate of a capacitor C 05 and one input of a control stage, which is described in detail below. The other plate of the capacitor C 05 is connected to ground. The transistors MN 01 and MN 02 act as switches and the power converter is operable to provide an output voltage to a voltage rail VOUT. MN 02 has an internal body-diode BD 01 . A pair of Schottky diodes D 02 and D 03 are connected in series such that the diode D 03 is connected to the same node as the capacitor C 05 and both diodes D 03 and D 02 are forward biased in a direction away from the node connected to the capacitor C 05 .

A node interconnecting the inductor L 01 and the drain terminal of the transistor MN 01 and the source terminal of the transistor MN 02 is connected to a charge pump arrangement. The charge pump comprises a conventional CMOS inverter with an n-type MOS transistor MN 05 and a p-type MOS transistor MP 04 . The transistors MP 04 and MN 05 have interconnected drain terminals. The source terminal of the transistor MP 04 is connected to the voltage rail VOUT and the source terminal of the transistor MN 05 is connected to ground. A node N 1 interconnecting the drain terminals of the transistors MP 04 and MN 05 is connected to a coupling capacitor C 02 , which couples the output of the charge pump to a node interconnecting the diodes D 02 and D 03 on a voltage rail VC/P (the charge pump output voltage). The node interconnecting the inductor LO 1 and the transistors MN 01 and MN 02 is connected to the gate terminals of both transistors MP 04 and MN 05 via resistors R 4 and R 3 , respectively. Another pair of Schottky diodes D 04 and D 05 are connected in series between a node interconnecting the gate terminal of the transistor MP 04 and the resistor R 4 and a node interconnecting the gate terminal of the transistor MN 05 and the resistor R 3 . The diodes are forward biased in a direction from the gate terminal of the transistor MN 05 to the gate terminal transistor MP 04 . A node interconnecting the diodes D 04 and D 05 is connected to a node interconnecting the resistors R 4 and R 3 .

The cathode of the diode D 02 is connected to the input of an LED LED 01 , and also to one plate of a capacitor C 03 and one plate of a capacitor C 04 . The other plate of the capacitor C 03 is connected to ground and the other plate of the capacitor C 04 is connected to a voltage rail VOUT, as are one plate of the capacitor C 05 and the drain terminal of the transistor MN 02 . The capacitor C 04 is known as a “super-capacitor”; that is, it has a very high value of capacitance of between 0.1 F and 1000 F. The capacitor C 03 has a much smaller capacitance than the capacitor C 04 , about 1 μF, but capacitors C 03 and C 04 are virtually connected in parallel so as to provide a combined capacitance. The output of the LED LED 01 is connected to the input of an LED LED 02 so that both LEDs LED 01 and LED 02 are connected in series with each other. The output of the LED LED 02 is connected to the drain terminal of a MOS transistor MN 03 so that the LEDs LED 01 and LED 02 are forward biased in a direction from the cathode of the diode D 02 to the drain terminal of the transistor MN 03 . The LEDs are provided on a separate die from the rest of the circuit but are connected to the capacitors C 03 and C 04 . The interconnection and coupling is such that charge on the capacitors C 03 and C 04 can supply the LEDs LED 01 and LED 02 . The source terminal of the transistor MN 03 is connected to one input of the control stage described below and the gate terminal of the transistor MN 03 is connected to the voltage rail VOUT.

The control stage for controlling the power supply circuit and switching between modes of operation is connected to several nodes on the voltage rail VOUT via the switching transistors MN 01 , MN 02 and a cascode transistor MN 03 . Gate terminals of the transistors MN 01 and MN 02 are connected to the outputs of drivers B 1 and B 2 , respectively. The driver B 2 is configured to output a signal that is the inverse of the signal output from the driver B 1 so that when the switch MN 01 is ON, the switch MN 02 is OFF and vice versa. The output of a pulse width modulator PWM is coupled to the inputs of the drivers B 1 and B 2 so that both drivers B 1 and B 2 are controlled by output signals from the pulse width modulator PWM.

A node on the voltage rail VOUT situated between nodes connecting VOUT to the drain terminal of the transistor MN 02 and the charge capacitor CO 5 is connected to a resistor R 1 . The resistor R 1 is connected in series with another resistor R 2 , which is also connected to ground. A node interconnecting the resistors R 1 and R 2 is connected to one input of a first error amplifier AMP 1 . The other input of the amplifier AMP 1 is connected to a first reference voltage VREF 1 . The output of the LED LED 02 is coupled, via the cascode transistor MN 03 , to a current regulator I 1 and to one input of a second error amplifier AMP 2 . The other input of the amplifier AMP 2 is connected to a second reference voltage source VREF 2 . The current regulator I 1 is switched to ground by a switch S 1 . Practically, instead of the switch S 1 and current source I 1 , the current source I 1 itself may be switched on and off. The outputs of the error amplifiers AMP 1 and AMP 2 are both connected to a two-way switch S 2 , which is operable to connect the output of the first error amplifier AMP 1 to the input of the pulse width modulator PWM during the “charge” mode of operation of the circuit and to connect the output of the second error amplifier AMP 2 with the input of the pulse width modulator PWM during the “flash” phase of operation. A smoothing capacitor C 06 is connected between a node interconnecting the switch S 2 and the pulse width modulator PWM input.

In the charge mode of operation, the switch S 2 is closed at the output of the amplifier AMP 1 so that the output of the amplifier AMP 1 is connected to the pulse width modulator PWM. The switch S 1 is open and the control stage is switched to a voltage regulation loop. The output signal from the pulse width modulator PWM to the drivers B 1 and B 2 is high so that the output of B 1 is high and the output of B 2 is low. Therefore the signal to the gate terminal of the switching transistor MN 01 is high and so MN 01 is ON and the signal to the gate terminal of the transistor MN 02 is low so that MN 02 is OFF. The pulse width modulator initially limits the switch peak current of the transistor MN 01 so that the current is increased in steps of 250 mA every 500 ms. This is a “soft-start” scheme that limits the inrush current during start of the circuit. This means that the output voltage of the power converter is also limited. Current from the inductor L 01 charges the capacitor C 05 , which generates the output voltage of the power converter at the voltage rail VOUT. The arrangement consisting of resistors R 3 and R 4 and diodes D 04 and D 05 which are coupled to the gate terminals of the transistors MP 04 and MN 05 in the inverter serves to prevent large shoot-through currents through the inverter. Only either MN 05 or MP 04 is switched on. The voltage at the node N 1 is toggling between two potentials: VOUT and ground. This voltage is added to the potential present across the capacitor C 02 . The diode D 02 and the capacitor C 03 form a rectification circuit that is used to generate the VC/P output voltage.

The voltage signal output from the inverter is coupled to the diode D 02 by the capacitor C 02 and is rectified by the diode D 02 before being applied to the voltage rail VC/P. The capacitor C 03 and the super capacitor C 04 are charged and the voltage at VOUT is stepped up to a value of 5.5 V. The voltage level at VOUT; i.e., the output voltage of the power converter is compared with the reference voltage VREF 1 by the amplifier AMP 1 .

In flash mode, the switch S 1 is closed. The cascode transistor MN 03 is conducting and the switch S 2 switches from the output of the amplifier AMP 1 to the output of the amplifier AMP 2 so that the control stage is now in a current regulation loop. When the switch S 1 is closed, limited current flows through the LEDs LED 01 and LED 02 , with the current being limited by the current regulator I 1 . The LED output voltage is compared with the reference voltage VREF 2 at the amplifier AMP 2 . Because the output of the voltage regulated power converter is combined with the output of the high-value capacitance capacitor in the “fire” phase of operation, which is charged with limited current from the charge pump circuit in the “charge-up” phase of operation, the LED circuit allows a pair of white LEDs to be operated as a flashlight when connected in series, regardless of the battery voltage. The two LEDs connected in series have a higher efficiency compared to a single LED with similar electrical power.

Although the present invention has been described with reference to a specific embodiment, it is not limited to this embodiment and no doubt alternatives will occur to the skilled person that lie within the scope of the invention as claimed.