Variable-gain low-noise amplifier

1. Field of the Invention

The present invention relates to a low-noise amplifier, and more particularly, to a variable-gain low-noise amplifier.

2. Description of the Related Art

For implementation of good communication in a long distance, output power of a transmitter may be designed to be increased, or a sensitivity of a receiver may be designed to be improved. However, the approach for increasing the output power of the transmitter is not preferable due to limitation of power level of an output stage of the transmitter, influence to associated apparatuses, and cost thereof. Therefore, the approach for improving the sensitivity of the receiver is preferably used. The sensitivity characteristics of the receiver can be expressed by a noise figure (NF) which represents a degree of extracting reception signal from noises. The smaller the NF is, the better the sensitivity of the receiver is.

Recently, portable communication technologies in frequency bandwidths of 400 MHz to 2.5 GHz have been rapidly developed. Therefore, technologies for radio frequency (RF) devices and circuits have also been important. In such an RF device or system, a low-noise amplifier (LNA) is a circuit for amplifying a very small signal received through an antenna of a receiver without noise. In general, since the low-noise amplifier is disposed at the first state of the receiver, the NF of the low-noise amplifier determines a whole performance of the receiver. Therefore, in the low-noise amplifier, noise and signal deformation need to be suppressed.

FIG. 1 is a circuit diagram illustrating a conventional low-noise amplifier.

Referring to FIG. 1 , the low-noise amplifier 100 includes three inductors Ld, Lg, and Ls and three MOS transistors M 1 , M 2 , and M 3 .

The inductor Ls is an input-impedance matching inductor. When a frequency of an input signal is f 0 , an imaginary part of the input impedance is 0 (zero). At this time, the input impedance is matched to a desired value of 50Ω by adjusting the inductance of the input-impedance matching inductor Ls, so that maximum signal transmission can be obtained. The inductor Lg is a frequency-band inductor. A frequency band of operation of the low-noise amplifier is determined by adjusting the inductance of the frequency-band inductor Lg. The inductor Ld is a resonance inductor. The resonance inductor Ld together with a parasitic capacitance between a drain of the second MOS transistor M 2 and a substrate and a gate capacitance of the third MOS transistor M 3 constitutes a resonance circuit that resonates at a desired frequency.

The second MOS transistor M 2 has a common gate amplifier structure in which reverse isolation between input and output can be increased. That is, an influx of a signal reflected from an apparatus which receives the output of the low-noise amplifier can be suppressed as large as possible. The feedback from the output to the input can be minimized, so that stability of the circuit can be improved. The third MOS transistor M 3 has a common source amplifier structure in which gain can be increased.

The first MOS transistor M 1 , that is, an input transistor has a common source structure in which an inductor is inserted between the gate and the source. The input impedance Z i can be expressed by Equation 1.

Here, if Z i =50Ω by adjusting the value of Ls, the input impedance matching can be obtained. In this method, there is no need for connection to an external circuit, so that the method has an advantage in terms of noise figure (NF). The gain of the amplifier, that is, trans-conductance Gm is independent of bias, but it is correlated to only the input-impedance matching inductor Ls. [impedance→input impedance] The trans-conductance Gm and small-signal gain Av of the circuit can be expressed by Equations 2 and 3, respectively.

Referring to Equation 3, it can be seen that the small-signal gain A v of the low-noise amplifier that is subject to impedance and frequency matching is independent of bias, but it is inversely proportional to a signal frequency w 0 and source inductance Ls.

In design of such a low-noise amplifier shown in FIG. 1 , it is necessary to minimize the noise figure (NF), to ensure IP 3 (third order intercept point), to lower input impedance, and to maintain suitable gain. Here, a small value of the NF denotes that a low-noise amplifier generates a small amount of noise. If the NF has a small value, a low level of signal can be amplified irrespective of influence of noise, so that a small-sized antenna can be implemented.

However, although the aforementioned electric characteristics are satisfied, the gain of the low-noise amplifier needs to be varied so as to widen applications range of the low-noise amplifier.

The present invention provides a variable-gain low-noise amplifier.

According to an aspect of the present invention, there is provided a variable-gain low-noise amplifier comprising a first load, a second load, a third load, an input transistor, a pole/zero control circuit, and a gain control circuit. A first terminal of the first load is connected to a power-source voltage, and a second terminal thereof is connected to an output terminal. The second load is operated in response to a bias voltage, and a first terminal thereof is connected to the output terminal. A first terminal of the input transistor is connected to the second terminal of the second load, and a gate thereof is connected to an input terminal. The pole/zero control circuit adjusts frequency characteristics and a gain in response to at least one pole/zero control signal. A first terminal of the pole/zero control circuit is connected to the input terminal, and a second terminal thereof is connected to the output terminal. The gain control circuit adjusts the gain in response to at least one gain control signal. A first terminal of the gain control circuit is connected to a common terminal of the second load and the input transistor, a second terminal thereof is connected to the input terminal, and a third terminal thereof of is connected to a first terminal of the third load. A second terminal of the third load is connected to a ground voltage.

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram illustrating a conventional low-noise amplifier;

FIG. 2 is a conceptual view illustrating a low-noise amplifier with variable gain according to the present invention;

FIG. 3 is a view illustrating one embodiment of the variable-gain low-noise amplifier according to the present invention illustrated in FIG. 2 ;

FIG. 4 is a view illustrating another embodiment of the variable-gain low-noise amplifier according to the present invention illustrated in FIG. 3 ;

FIG. 5 is a view illustrating a general amplifier having an inverter structure; and

FIG. 6 is a graph illustrating a result of computer simulation of the variable-gain low-noise amplifier according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a conceptual view illustrating a low-noise amplifier with variable gain according to the present invention.

Referring to FIG. 2 , the variable-gain low-noise amplifier 200 includes a first load L 1 , a second load M 1 , a third load L 2 , an input transistor M 2 , a pole/zero control circuit 210 , a gain control circuit 220 , and an input signal sustaining capacitor Cgs.

The first load L 1 can be implemented with an inductor of which first terminal is connected to a power-source voltage Vdd and of which second terminal is connected to an output terminal Vo. The second load M 1 can be implemented with an MOS transistor of which first terminal is connected to the output terminal Vo and of which gate is applied with a bias voltage Vb. A first terminal of the input transistor M 2 is connected to the second terminal Vo 1 of the second load M 1 , a second terminal thereof is connected to a second terminal of the third load L 2 , and a gate thereof is connected to the input terminal Vin.

The pole/zero control circuit 210 adjusts a gain and frequency characteristics of the low-noise amplifier 200 in response to at least one pole/zero control signal CON 1 . A first terminal of the pole/zero control circuit is connected to the input terminal Vin, and a second terminal thereof is connected to the output terminal Vo. The gain control circuit 220 adjusts the gain of the low-noise amplifier 200 in response to at least one gain control signal CON 2 . A first terminal of the gain control circuit is connected to a common node Vo 1 of the second load M 1 and the input transistor M 2 , a second terminal thereof is connected to the input terminal Vin, and a third terminal thereof is connected to a first terminal of the third load L 2 . The second terminal of the third load L 2 is connected to a ground voltage GND. The third load can be implemented with an inductor.

A first terminal of the input signal sustaining capacitor Cgs is connected to the input terminal Vin, and a second terminal thereof is connected to the first terminal of the third load L 2 .

FIG. 3 is a view illustrating one embodiment of the variable-gain low-noise amplifier according to the present invention illustrated in FIG. 2 .

Referring to FIG. 3 , the variable-gain low-noise amplifier 300 has the same construction as the variable-gain low-noise amplifier 200 except that 1) the pole/zero control circuit 210 and the gain control circuit 220 are illustrated more in detail, and 2) the pole/zero control signal CON 1 is replaced with n (n is an integer) pole/zero control signals CON 11 to CON 1 n , and the gain control signal CON 2 is replaced with m (m is an integer) gain control signals CON 21 to CON 2 m.

Accordingly, hereinafter, the pole/zero control circuit 210 and the gain control circuit 220 will be described more in detail.

The pole/zero control circuit 210 includes a feedback capacitor Cf, a first switch-resistor circuit 211 , a second switch-resistor circuit 212 , and an n-th switch-resistor circuit 213 .

A first terminal of the feedback capacitor Cf is connected to the output terminal Vo.

The first switch-resistor circuit 211 includes an 11-th switch transistor M 11 and a first resistor R 1 . A first terminal of the 11-th switch transistor M 11 is connected to a second terminal of the feedback capacitor Cf, and a gate thereof is applied with the first pole/zero control signal CON 11 . A first terminal of the first resistor R is connected to a second terminal of the 11-th switch transistor M 1 , and a second terminal thereof is connected to the input terminal Vin.

The second switch-resistor circuit 212 includes a 12-th switch transistor M 12 and a second resistor R 2 . A first terminal of the 12-th switch transistor M 12 is connected to the second terminal of the feedback capacitor Cf, and a gate thereof is applied with the second pole/zero control signal CON 12 . A first terminal of the second resistor R 2 is connected to a second terminal of the 12-th switch transistor M 12 , and a second terminal thereof is connected to the input terminal Vin.

The n-th switch-resistor circuit 213 includes a 1n-th switch transistor M 1 n and an n-th resistor Rn. A first terminal of the 1n-th switch transistor M 1 n is connected to the second terminal of the feedback capacitor Cf, and a gate thereof is applied with the n-th pole/zero control signal CON 1 n . A first terminal of the n-th resistor Rn is connected to a second terminal of the 1n-th switch transistor M 1 n , and a second terminal thereof is connected to the input terminal Vin.

The gain control circuit 220 includes a first gain control circuit 221 , a second gain control circuit 222 , and an m-th gain control circuit 223 .

The first gain control circuit 221 includes a 21-th switch transistor M 21 , a first dividing capacitor C 1 , a second dividing capacitor C 2 , and a first current source transistor CS 1 . A first terminal of the first dividing capacitor C 1 is connected to the input terminal Vin. A first terminal of the 21-th switch transistor M 21 is connected to a second terminal of the first dividing capacitor C 1 , a second terminal thereof is connected to a node which generates the first divided voltage Vd 1 , and a gate thereof is applied with the first gain control signal CON 21 . A first terminal of the second dividing capacitor C 2 is connect to the node which generates the first divided voltage Vd 1 , and a second terminal thereof is connected to the first terminal of the third load L 2 . A first terminal of the first current source transistor CS 1 is connected to the common node Vo 1 of the second load M 1 and the input transistor M 2 , a second terminal thereof is connected to the first terminal of the third load L 2 , and a gate thereof is applied with the first divided voltage Vd 1 .

The second gain control circuit 222 includes a 22-th switch transistor M 22 , a third dividing capacitor C 3 , a fourth dividing capacitor C 4 , and a second current source transistor CS 2 . A first terminal of the third dividing capacitor C 3 is connected to the node which generates the first divided voltage Vd 1 . A first terminal of the 22-th switch transistor M 22 is connected to a second terminal of the third dividing capacitor C 3 , a second terminal thereof is connected to a node which generates the second divided voltage Vd 2 , and a gate thereof is applied with the second gain control signal CON 22 . A first terminal of the fourth dividing capacitor C 4 is connected to the node which generates the second divided voltage Vd 2 , and a second terminal thereof is connected to the ground voltage GND of the third load L 2 . A first terminal of the second current source transistor CS 2 is connected to the common node Vo 1 of the second load M 1 and the input transistor M 2 , a second terminal thereof is connected to the first terminal of the third load L 2 , and a gate thereof is applied with the second divided voltage Vd 2 .

The m-th gain control circuit 223 includes a 2m-th switch transistor M 2 m , a fifth dividing capacitor C 5 , a sixth dividing capacitor C 6 , and an m-th current source transistor CSm. A first terminal of the fifth dividing capacitor C 5 is connected to a node which generates (m−1)-th divided voltage Vd(m−1). A first terminal of the 2m-th switch transistor M 2 m is connected to a second terminal of the fifth dividing capacitor C 5 , a second terminal thereof is connected to a node which generates the m-th divided voltage Vdm, and a gate thereof is applied with the m-th gain control signal CON 2 m . A first terminal of the sixth dividing capacitor C 6 is connected to the node which generates the m-th divided voltage Vdm, a second terminal thereof is connected to the first terminal of the third load L 2 . A first terminal of the m-th current source transistor CSm is connected to the common node Vo 1 of the second load M 1 and the input transistor M 2 , a second terminal thereof is connected to the first terminal of the third load L 2 , and a gate thereof is applied with the m-th divided voltage Vdm.

FIG. 4 is a view illustrating another embodiment of the variable-gain low-noise amplifier according to the present invention illustrated in FIG. 3 .

Referring to FIG. 4 , the variable-gain low-noise amplifier 400 has the same construction as low-noise amplifier 300 shown in FIG. 3 except for a gain control circuit 420 . Accordingly, hereinafter, only the gain control circuit 420 will be descried more in detail.

The gain control circuit 420 includes a first gain control circuit 421 , a second gain control circuit 422 , and an m-th gain control circuit 423 .

The first gain control circuit 421 includes a 21-th switch transistor M 21 , a first dividing capacitor C 1 , a second dividing capacitor C 2 , and a first current source transistor CS 1 . A first terminal of the first dividing capacitor C 1 is connected to the input terminal Vin. A first terminal of the 21-th switch transistor M 21 is connected to a second terminal of the first dividing capacitor C 1 , and a gate thereof is applied with the first gain control signal CON 21 . A first terminal of the second dividing capacitor C 2 is connected to a second terminal of the 21-th switch transistor M 21 , and a second terminal thereof is connected to the first terminal of the third load L 2 . A first terminal of the first current source transistor CS 1 is connected to the common node Vo 1 of the second load M 1 and the input transistor M 2 , a second terminal thereof is connected to the first terminal of the third load L 2 , and a gate there of is connected to a common terminal of the 21-th switch transistor M 21 and the second dividing capacitor C 2 .

The second gain control circuit 422 includes a 22-th switch transistor M 22 , a third dividing capacitor C 3 , a fourth dividing capacitor C 4 , and a second current source transistor CS 2 . A first terminal of the third dividing capacitor C 3 is connected to the input terminal Vin. A first terminal of the 22-th switch transistor M 22 is connected to a second terminal of the third dividing capacitor C 3 , and a gate thereof is applied with the second gain control signal CON 22 . A first terminal of the fourth dividing capacitor C 4 is connected to a second terminal of the 22-th switch transistor M 22 , and a second terminal thereof is connected to the first terminal of the third load L 2 . A first terminal of the second current source transistor CS 2 is connected to the common node Vo 1 of the second load M 1 and the input transistor M 2 , a second terminal thereof is connected to the first terminal of the third load L 2 , and a gate is connected to a common terminal of the 22-th switch transistor M 22 and the fourth dividing capacitor C 4 .

The m-th gain control circuit 423 includes a 2m-th switch transistor M 2 m , a fifth dividing capacitor C 5 , a sixth dividing capacitor C 6 , and an m-th current source transistor CSm. A first terminal of the fifth dividing capacitor C 5 is connected to the input terminal Vin. A first terminal of the 2m-th switch transistor M 2 m is connected to a second terminal of the fifth dividing capacitor C 5 , and a gate thereof is applied with the m-th gain control signal CON 2 m . A first terminal of the sixth dividing capacitor C 6 is connected to a second terminal of the 2m-th switch transistor M 2 m , and a second terminal thereof is connected to the first terminal of the third load L 2 . A first terminal of the m-th current source transistor CSm is connected to the common node Vo 1 of the second load M 1 and the input transistor M 2 , a second terminal thereof is connected to the first terminal of the third load L 2 , and a gate thereof is connected to a common terminal of the 2m-th switch transistor M 2 m and the sixth dividing capacitor C 6 .

Hereinafter, operations of the variable-gain low-noise amplifier according to the present invention will be described.

FIG. 5 is a view illustrating a general amplifier having an inverter structure.

Referring to FIG. 5 , the general amplifier 500 includes a load MOS transistor M 1 and an input transistor M 2 . A first terminal of the load MOS transistor M 1 is connected to the power-source voltage Vdd, a second terminal thereof is connected to the output terminal Vo, and a gate thereof is applied with a bias voltage Vbias. A first terminal of the input transistor M 2 is connected to the output terminal Vo, a second terminal thereof is connected to the ground voltage GND, and a gate thereof is applied with the input signal Vin.

A gain of the variable-gain low-noise amplifier 500 can be expressed by Equation 4.

Here, g o1 and g o2 denote conductances of the load MOS transistor M 1 and the input transistor M 2 , respectively. In addition, since a bulk bias of the load MOS transistor M 1 is directly connected to a substrate but not the output terminal Vo, g m1b is a back-gate transconductance which is generated due to a body effect that a voltage of the substrate serves like a gate signal, and g m2 is a transconductance of the input transistor M 2 .

In general, since back-gate transconductance g m1b is larger than the conductances of the load MOS transistor M 1 and the input transistor M 2 , Equation 4 can be reduced into Equation 5.

Since the back-gate transconductance g m1b is a fixed value, as the transconductance g m2 of the input transistor M 2 is varied, the gain of the amplifier can be varied. Since the conductance can be considered as a current, in the following description, the current and conductance will be treated as the same concept.

As shown in FIG. 3 , the gain control circuit 220 of the variable-gain low-noise amplifier 300 includes a plurality of gain control circuits 221 to 223 which have the respective current sources CS 1 to CSm. The first current source CS 1 included in the first gain control circuit 221 can supply a constant source current through the common terminal of the second load M 1 and the input transistor M 2 in response to the first divided voltage Vd 1 generated by dividing the input signal Vin based on a capacitance difference between two dividing capacitors C 1 and C 2 . The second current source CS 2 included in the second gain control circuit 222 can supply a constant source current through the common terminal of the second load M 1 and the input transistor M 2 in response to the second divided voltage Vd 2 generated by dividing the first divided voltage Vd 1 based on a capacitance difference between two dividing capacitors C 3 and C 4 . Similarly, the m-th current source CSm included in the m-th gain control circuit 223 can supply a constant source current through the common terminal of the second load M 1 and the input transistor M 2 in response to the m-th divided voltage Vdm generated by dividing the (m−1)-th divided voltage Vd(m−1) based on a capacitance difference between two dividing capacitors C 5 and C 6 .

Similarly, as shown in FIG. 4 , the gain control circuit 420 of the variable-gain low-noise amplifier 400 includes a plurality of gain control circuits 421 to 423 which have the respective current sources CS 1 to CSm. The first current source CS 1 included in the first gain control circuit 421 can supply a constant source current through the common terminal of the second load M 1 and the input transistor M 2 in response to a divided voltage generated by dividing the input signal Vin based on a capacitance difference between two dividing capacitors C 1 and C 2 . The second current source CS 2 included in the second gain control circuit 422 can supply a constant source current through the common terminal of the second load M 1 and the input transistor M 2 in response to a divided voltage generated by dividing the input signal Vin based on a capacitance difference between two dividing capacitors C 3 and C 4 . Similarly, the m-th current source CSm included in the m-th gain control circuit 423 can supply a constant source current through the common terminal of the second load M 1 and the input transistor M 2 in response to a divided voltage generated by dividing the input voltage Vin based on a capacitance difference between two dividing capacitors C 5 and C 6 .

Referring to the above description and Equation 5, since the gain of the amplifier is proportional to an amount of varied source current supplied through the common terminal of the second load M 1 and the input transistor M 2 , the low-noise amplifier according to the present invention can vary the amount of the source current supplied through the common terminal of the second load M 1 and the input transistor M 2 . The gain control circuit 220 shown in FIG. 3 is different from the gain control circuit 420 shown in FIG. 4 in that a plurality of the gain control circuits 221 , 222 , and 223 are connected in series to each other, but a plurality of the gain control circuits 421 , 422 , and 423 are connected in parallel to each other. In case of FIG. 3 , since a plurality of the gain control circuits 221 , 222 , and 223 are connected in series to each other, if a front gain control circuit is not selected, a following gain control circuit is disabled. In case of FIG. 4 , since a plurality of the gain control circuits 421 , 422 , and 423 are connected in parallel to each other, each gain control unit can separately operated irrespective of selection of other gain control units.

The conventional amplifier shown in FIG. 5 is different from the variable-gain low-noise amplifier shown in FIGS. 3 and 4 according to the present invention in that the output terminal Vo of the conventional amplifier is connected to the common terminal of the second load M 1 and the input transistor M 2 , but the output terminal of the amplifiers according to the present invention is connected to the common terminal of the first load L 1 and the second load M 1 . In the variable-gain low-noise amplifiers according to the present invention, the same gain can be obtained except that the voltage level of the output terminal Vo is increased by a voltage drop across the second load M 1 .

The pole/zero control circuit 210 connected between the output terminal Vo and the input terminal Vin performs a function of controlling poles and zero points on a frequency response curve so as to stabilize electric characteristics such as a phase margin in a frequency band where the amplifier is operated. Since this function is well-known, description thereof is omitted.

FIG. 6 is a graph illustrating a result of computer simulation of the variable-gain low-noise amplifier according to the present invention.

Referring to FIG. 6 , the computer simulation is carried out in various regions; a high-gain region High, a middle-gain region Mid, and low-gain regions Low 1 and Low 2 . As the gain is varied from the high-gain region H to the low-gain region Low 2 , noise figure (NF) and the third order intercept point (IP 3 ) are linearly varied.

Sensitivity characteristics of a receiver can be expressed by using the NF which represents a degree of extracting a received signal from noises. As described above, the smaller the NF is, the better the sensitivity is. However, in a case where the gain of the amplifier is varied like the variable-gain low-noise amplifier according to the present invention, the linearity of the NF and IP 3 becomes more important factor. According to the variable-gain low-noise amplifier of the present invention, since the NF and IP 3 are linearly varied, desired electric characteristics can be obtained.

As described above, in a variable-gain low-noise amplifier according to the present invention, a gain thereof can be varied, and characteristics of NF and IP 3 can also be linearly varied, so that the variable-gain low-noise amplifier can be used for general purposes without separate design of a new low-low amplifier matching with characteristics of a receiving stage.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.