Power converter for compensating a maximum output power

This application claims priority from U.S. Provisional Patent Application No. 60/944,096, filed on Jun. 14, 2007.

1. Field of the Invention

The present invention relates to a power converter, and more particularly, to a power converter used for compensating a maximum output power.

2. Description of Related Art

Power converters are generally used to power many of electronic devices. The pulse-width modulation (PWM) technique is a conventional technology used in a power converter to control and regulate the output power. Various protection functions are built-in in the power converter to protect the power converter from permanent damage. The function of compensating maximum output power is commonly used for overload and short-circuit protections.

FIG. 1 shows a traditional power converter. The power converter includes a power transformer T 1 having a primary winding N P and a secondary winding N S . The power transformer T 1 is to provide galvanic isolation between an AC line input and an output of the power converter for safety. The primary winding N P is supplied with an input voltage V IN of the power converter. In order to regulate an output voltage V O of the power converter, a control circuit coupled in series with the primary winding N P of the power transformer T 1 generates a PWM signal V PWM in response to a feedback signal V FB . The control circuit comprises an oscillator 10 , a first comparator 31 , a second comparator 32 , a logic circuit 33 , and a flip-flop 20 . The PWM signal V PWM controls a power switch Q 1 to switch the power transformer T 1 . A current-sense resistor R S is connected in series with the power switch Q 1 to determine the maximum output power of the power converter. The current-sense resistor R S turns a switching current I P of the power transformer T 1 to a current-sense signal V CS . The current-sense signal V CS is coupled to the control circuit. If the current-sense signal V CS is greater than a limit signal V M through the first comparator 31 , the control circuit is coupled to disable the PWM signal V PWM , and it also restricts the maximum output power of the power converter.

FIG. 2 shows the signal waveforms of the PWM signal and the current-sense signal of the power converter in FIG. 1 . As the PWM signal V PWM becomes logic-high, the switching current I P will be generated accordingly. A peak value I P1 of the switching current I P can be given by,

I P ⁢ ⁢ 1 = V IN L P × T ON ( 1 )

The maximum output power P O can be expressed by,

In Equations (1) and (2), L P is the inductance of the primary winding N P of the transformer T 1 , and T ON is an on-time of the PWM signal V PWM while the power switch Q 1 is switched on, and T S is the switching period of the PWM signal V PWM .

From Equation (2), we find that the output power varies as the input voltage V IN varies. The input voltage ranges between 90V AC and 264V AC when the safety regulations are taken into consideration, and wherein the power limit in a high-line input voltage is many times higher than the power limit in a low-line input voltage. There is a delay time T D from the moment the voltage in current-sense signal V CS is higher than the limit signal V M to the moment the PWM signal V PWM is actually turned off. The maximum output power is also affected by the delay time T D of the control circuit. In the period of the delay time T D , the power switch Q 1 is still turned on, and it keeps on-state for delivering the output power. Therefore, the actual on-time of the PWM signal V PWM is equal to T ON +T D , and the actual maximum output power P O becomes as follows:

Although the delay time T D is short, generally within the range of 200 nsec˜350 nsec, the higher operating frequency and smaller switching period T S , the more influential impact is caused by the delay time T D . Therefore, the input voltage should be compensated properly, such that the input voltage does not affect the maximum output power.

An objective of the invention is to provide a power converter and a PWM controller for compensating a maximum output power.

The present invention provides a power converter for compensating a maximum output power. The power converter includes a power switch, an oscillator, a control circuit and a delay modulator. The power switch is coupled to a primary winding of the power converter for switching a power transformer, and the power transformer is supplied with an input voltage of the power converter. The oscillator generates a pulse signal. The control circuit is coupled to the oscillator for generating a PWM signal and an over current signal in response to the pulse signal and a current sense signal of the power converter, wherein the PWM signal controls the power switch, and the over current signal is activated for cycle-by-cycle limiting an on-time of the PWM signal once the current sense signal is higher than a limit signal. The delay modulator is coupled to the control circuit for generating a delay control signal in response to the PWM signal and the over current signal, wherein the delay control signal is used to prolong a propagation delay time of the control circuit in response to the on-time of the PWM signal, and the propagation delay time can be compensated by the on-time of the PWM signal to limit the maximum output power under a high-line input voltage and a heavy-load condition, and the propagation delay time can be adjusted to achieve an identical maximum output power between a low-line input voltage and the high-line input voltage.

Furthermore, the present invention provides a PWM controller for compensating a maximum output power. The power converter includes an oscillator, a control circuit and a delay modulator. The oscillator generates a pulse signal. The control circuit is coupled to the oscillator for generating a PWM signal and an over current signal in response to the pulse signal and a current sense signal of the power converter, wherein the PWM signal controls a power switch, and the over current signal is activated for cycle-by-cycle limiting an on-time of the PWM signal once the current sense signal is higher than a limit signal. The delay modulator is coupled to the control circuit for generating a delay control signal in response to the PWM signal and the over current signal, wherein the delay control signal is used to prolong a propagation delay time of the control circuit in response to the on-time of the PWM signal, and the propagation delay time can be compensated by the on-time of the PWM signal to limit the maximum output power under a high-line input voltage and a heavy-load condition, and the propagation delay time can be adjusted to achieve an identical maximum output power between a low-line input voltage and the high-line input voltage.

FIG. 1 shows a traditional power converter.

FIG. 2 shows the signal waveforms of the PWM signal and the current-sense signal of the traditional power converter.

FIG. 3 shows a power converter having a PWM controller in accordance with the invention.

FIG. 4 shows the delay modulator in accordance with the invention.

FIG. 5 shows the waveforms of the PWM controller in the low-line input voltage according to the invention.

FIG. 6 shows the waveforms of the PWM controller in the high-line input voltage according to the invention.

The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.

FIG. 3 shows a circuit diagram of a power converter according to an embodiment of the invention. The power converter includes a power switch Q 1 and a PWM controller. The power switch Q 1 is coupled to a primary winding of the power converter for switching a power transformer T 1 . The power transformer T 1 has the primary winding N P and a secondary winding N S . The power transformer T 1 transfers the stored energy from the primary winding N P to the secondary winding N S . The primary winding N P of the power transformer T 1 is supplied with an input voltage V IN of the power converter. In order to regulate an output voltage V O of the power converter, the PWM controller is coupled in series with the primary winding N P of the power transformer T 1 to generate a PWM signal V PWM in response to a feedback signal V FB .

In one embodiment, the PWM controller comprises an oscillator 10 , a control circuit 30 and a delay modulator 60 . The control circuit 30 comprises a flip-flop 20 , comparators 31 , 32 and a logic circuit 33 . The oscillator 10 generates a pulse signal PLS to the flip-flop 20 . The flip-flop 20 generates the PWM signal V PWM in response to the pulse signal PLS and an output terminal of the logic circuit 33 . The PWM signal V PWM controls the power switch Q 1 to switch the power transformer T 1 . In general, the input voltage ranges between 90V AC and 264V AC when the safety regulations are taken into consideration, and wherein the maximum output power in a high-line input voltage is many times higher than the maximum output power in a low-line input voltage. An on-time T ON of the PWM signal V PWM is correlated to an amplitude of the input voltage V IN . Therefore, the on-time T ON of the PWM signal V PWM is decreased in response to the increase of the input voltage V IN , and the on-time of the PWM signal V PWM is increased in response to the decrease of the input voltage V IN .

The control circuit 30 is coupled to the oscillator 10 for generating the PWM signal V PWM and an over current signal V OC in response to the pulse signal PLS and a current sense signal V CS of the power converter, wherein the PWM signal V PWM controls the power switch Q 1 , and the over current signal V OC is activated for cycle-by-cycle limiting the on-time T ON of the PWM signal V PWM once the current sense signal V CS is higher than a limit signal V M . The delay modulator 60 is coupled to the control circuit 30 for generating a delay control signal V TD in response to the PWM signal V PWM and the over current signal V OC , wherein the delay control signal V TD is used to prolong a propagation delay time T D of the control circuit 30 in response to the on-time T ON of the PWM signal V PWM . The propagation delay time T D can be compensated by the on-time T ON of the PWM signal V PWM to limit the maximum output power under a high-line input voltage and a heavy-load condition. The propagation delay time T D can be adjusted to achieve an identical maximum output power between a low-line input voltage and the high-line input voltage.

The on-time T ON of the PWM signal V PWM is correlated to an amplitude of the input voltage V IN , wherein on-time T ON of the PWM signal V PWM is decreased in response to the increase of the input voltage V IN , and the on-time T ON of the PWM signal V PWM is increased in response to the decrease of the input voltage V IN . The objective of the present invention is to develop an adjustable propagation delay time in accordance with the on-time of the PWM signal V PWM and the amplitude of the input voltage V IN . The propagation delay time of the high-line input voltage is shorter than the propagation delay time of the low-line input voltage.

FIG. 4 shows the delay modulator in accordance with the invention. The delay modulator 60 comprises a state-detect unit 611 and a delay-adjusted unit 620 . The state-detect unit 611 is coupled to the control circuit 30 for generating a state signal S HL in response to the PWM signal V PWM and the over current signal V OC . The state-detect unit 611 can be implemented by an AND gate. The delay-adjusted unit 620 is coupled to the state-detect unit 611 for generating the delay control signal V TD in response to the state signal S HL . The delay-adjusted unit 620 comprises a saw-tooth circuit 630 and a correction circuit 621 . The saw-tooth circuit 630 is coupled to the state-detect unit 611 for generating a saw-tooth signal V C in accordance with the state signal S HL . The saw-tooth circuit 630 comprises a charge circuit and a discharge circuit.

The charge circuit includes a charge current I C and a capacitor C S . The capacitor C S is coupled to the state-detect unit 611 through the charge current I C . When both of the PWM signal V PWM and the over current signal V OC are logic-high, the state signal S HL is a high-level. Once the state signal S HL is high and the capacitor C S is charged by the charge current I C , a slope of the saw-tooth signal V C will be rising. However, the charge circuit is for charging the capacitor C S in response to the high-level of the state signal S HL . As mentioned above, the over current signal V OC is logic-high in accordance with the current sense signal V CS is lower than the limit signal V M through the comparator 31 .

The discharge circuit includes a discharge current I DIS and a discharge switch 631 . The discharge current I DIS is coupled to the charge circuit for receiving the saw-tooth signal V C and coupled to the state-detect unit 611 for receiving the state signal S HL through the discharge switch 631 . When the PWM signal V PWM or the over current signal V OC is logic-low, the state signal S HL is a low-level. Once the state signal S HL is low and the capacitor C S is discharged by the discharge current I DIS through the discharge switch 631 , a slope of the saw-tooth signal V C is falling. Furthermore, the discharge circuit is for discharging the capacitor C S in response to the low-level of the state signal S HL . As mentioned above, the over current signal V OC is logic-low in accordance with the current sense signal V CS is higher than the limit signal V M through the comparator 31 . The correction circuit 621 is coupled to the saw-tooth circuit 630 for generating the delay control signal V TD once the saw-tooth signal V C is higher than a ground level. The correction circuit 621 can be implemented by a comparator.

FIG. 5 shows the waveforms of the PWM controller in the low-line input voltage according to the present invention. Referring to FIG. 3 and FIG. 4 , in the low-line input voltage, the PWM signal V PWM,LV keeps a longer on-time T ON,LV to generate a higher saw-tooth signal V C,LV . Based on the higher saw-tooth signal V C,LV , a longer propagation delay time T D,LV is generated when the power switch Q 1 is turned off. In other words, both of the charge current I C and the discharge current I DIS are lasted a long period, and then result the higher saw-tooth signal V C,LV and the longer on-time T ON,LV .

FIG. 6 shows the waveforms of the PWM controller in the high-line input voltage according to the present invention. Referring to FIG. 3 and FIG. 4 , in the high-line input voltage, the PWM signal V PWM,HV keeps a shorter on-time T ON,HV to generate a lower saw-tooth signal V C,HV . Based on the lower saw-tooth signal V C,HV , a shorter propagation delay time T D,HV is generated when the power switch Q 1 is turned off. In other words, both of the charge current I C and the discharge current I DIS are lasted a short period, and then result the lower saw-tooth signal V C,LV and the shorter on-time T ON,HV .

Comparing to FIG. 5 and FIG. 6 , the on-time T ON,LV of the PWM signal V PWM,LV in the low-line input voltage is longer than the on-time T ON,HV of the PWM signal V PWM,HV in the high-line input voltage, the propagation delay time T D,LV in the low-line input voltage is longer than the propagation delay time T D,HV in the high-line input voltage. Therefore, during the period of the low-line input voltage, the longer on-time T ON,LV causes the longer propagation delay time T D,LV in accordance with the higher saw-tooth signal V C,LV . During the period of the high-line input voltage, the shorter on-time T ON,HV causes the shorter propagation delay time T D,HV in accordance with the lower saw-tooth signal V C,HV . From the above description, the maximum output power under the high-line input voltage and the heavy-load condition can be compensated properly, such that the difference between the low-line and high-line input voltage does not affect the maximum output power, an identical maximum output power for the low-line and high-line input voltage can be achieved.

The foregoing descriptions of the detailed embodiments are only illustrated to disclose the features and functions of the present invention and not restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the disclosure of the present invention should fall within the scope of the appended claims.