Continuous multigate transistors

The present application is based on, and claims priority date from Taiwan Application Serial Number 097104263, filed Feb. 4, 2008, the entire disclosure of which is incorporated by reference herein.

This disclosure relates to transistors, especially to continuous multigate transistors having adjacent poly gates with different dopant. The multigate transistors can be used in integrated circuits, and memories such as read only memory (ROM), nonvolatile memory, dynamic random access memory (DRAM), and static random access memory (SRAM).

FIG. 1 Prior Art—Traditional Transistors in Parallel Connection

FIG. 1 shows traditional transistors in parallel connection, the first transistor T 1 with a first Gate G 1 ; the dielectric layer 11 is made under the first gate G 1 . The dielectric layer 11 has two ends; a source S and a drain D are made under the dielectric layer 11 , each near one of the two ends of the first dielectric layer 11 . A second transistor T 2 with a second Gate G 2 , is in parallel to and spaced apart from the first gate G 1 ; a dielectric layer 12 is made under the second gate G 2 . The dielectric layer 12 has two ends; the common source S and the common drain D are extended under the dielectric layer 12 , each near one of the two ends of the dielectric layer 12 . There is semiconductor material 13 between the common source S and the common drain D.

The two transistors T 1 , T 2 in parallel connection according to the traditional structure are with the same device structure, and having a similar threshold voltage (Vt). The two gates G 1 , and G 2 are made of the same semiconductor material and doped with a same dopant. A unit length L exists between them to form two transistors in parallel connection. The minimum length in Y direction for the traditional transistors in parallel connection is of three unit lengths (3 L). A unit length L is a minimum width of a design rule used in the manufacturing process for such transistors.

Nowadays, a typical memory chip has 10 8 ˜10 10 transistors made thereon in a single chip. With the technology progress, the number of transistor in a single chip is increasing progressively. As the number of transistor increases for a single chip, the semiconductor material used for a memory chip is therefore increasing. It is desirable to reduce the occupied chip area for a single memory chip on a piece of wafer, while with a same number of transistors on a single memory chip. This not only increases yield for a semiconductor wafer but also meets the requirement of light weight and miniaturization for a memory chip.

FIG. 2 Prior Art—Traditional Transistors in Series Connection

FIG. 2 shows traditional transistors in series connection, the first transistor T 21 with a first Gate G 21 . A dielectric layer 21 is made under the first transistor T 21 . A source S is made under and on the left side of the dielectric layer 21 . A drain/source DS is made under and on the right side of the dielectric layer 21 . A second transistor T 22 with a second Gate G 22 is neighboring to the first transistor T 21 . A dielectric layer 22 is made under the second gate G 22 . The drain/source DS functions as a source for the second transistor T 22 . A drain D is made under and on the right side of the dielectric layer 22 . There is semiconductor material 23 in between the drains D and the sources S. The first gate G 21 and the second G 22 are spaced by a unit length (L). A unit length L is a minimum width of a design rule used in the manufacturing process for such transistors.

The two transistors T 21 , T 22 in series connection according to the traditional structure are with a same device structure, and having a similar threshold voltage (Vt). The two gates G 21 , G 22 are made of the same semiconductor material and doped with a same dopant. A unit length L exists between them to form two transistors in series connection. The minimum distance in X direction is of five unit lengths (5 L). A unit length L is a minimum width of a design rule used in the manufacturing process for such transistors.

FIG. 1 . shows a prior art—parallel connection

FIG. 2 . shows a prior art—series connection

FIG. 3 . shows a first embodiment—parallel connection

FIG. 4 . shows a second embodiment—series connection

FIG. 5A shows an additional transistor added to the embodiment illustrated in FIG. 3

FIG. 5B shows an additional transistor added to the embodiment illustrated in FIG. 3

FIG. 6A shows an additional transistor added to the embodiment illustrated in FIG. 4

FIG. 6B shows an additional transistor added to the embodiment illustrated in FIG. 4

This invention discloses a design for transistors which saves half area of semiconductor material comparing with traditional ones, while with a same number of transistors in a single memory chip. This invention is realized to implant a first area of a semiconductor material with a first dopant, and to implant a second area on the same semiconductor material, adjacent and continuous to the first area, with a second dopant complementary to the first dopant. The two areas are the first and second gate in the transistor. With this technology applied in memory device, one can save half area of semiconductor than the traditional one.

FIG. 3 Shows a First Embodiment—Continuous Multigate Transistors in Parallel Connection

A first transistor T 31 has a first Gate G 31 (N) made of semiconductor material and doped with a first dopant, e.g. N type dopant. A dielectric layer 31 is made under the first gate G 31 . The dielectric layer 31 has a first end (i.e. left side of the figure) and a second end (i.e. right side of the figure). A source S is made under and on the left side of the dielectric layer 31 . A drain D is made under and on the right side of the dielectric layer 31 . A second transistor T 32 has a second Gate G 32 (P) made of semiconductor material and doped with a second dopant (e.g. a P type dopant) which is complementary to the first dopant, abuts against the first gate G 31 . The dielectric layer 31 extends under the second gate G 32 . The dielectric layer 31 has a first end (i.e. left side of the figure) and a second end (i.e. right side of the figure). The source S extends under the dielectric layer 31 to become a source of the second transistor T 32 . The drain D extends under the dielectric layer 31 to become a drain of the second transistor T 32 . In other words, the two transistors T 31 and T 32 share a common source S, and share a common drain D. There is semiconductor material 33 between the common source S and the common drain D.

The two transistors T 31 , T 32 are made to be in parallel connection. The adjacent transistors are made side by side and with gates doped with different dopant. Furthermore, the adjacent transistors have different threshold voltage (Vt) from each other. A length of 2 L for the adjacent transistor in Y direction is only two-third (⅔) of that for the traditional transistors in parallel connection as shown in FIG. 1 . ⅔ is calculated from the comparison of the corresponding lengths 2 L v. 3 L, and then 2 L/3 L=⅔.

When the number of transistor is extremely large to be made on a single chip, the occupied area of a single chip on the semiconductor wafer saves half. The occupied area for a single chip according to this embodiment and compared with a traditional one as shown in FIG. 1 is as follows:

The length for traditional transistors in parallel connection is: (2n−1)L. However, the length for continuous multigate transistors in parallel connection is: nL

Wherein, n is the number of transistors. L is a unit length of a design rule for a transistor.

(2n−1)L is simplified to be 2 nL when n is extremely a large number.

=

The adjacent transistors T 31 , T 32 have an adjacent gates G 31 , G 32 . PN junction is formed between the adjacent gates G 31 , G 32 . For the independent operation for the adjacent transistors, and avoiding the current flow interference between the PN junction, the adjacent transistors are designed with different threshold voltages. In the embodiment as shown in FIG. 3 , the first transistor T 31 is made to be with a first threshold voltage Vt 31 which is higher than the threshold voltage Vt 32 of the second transistors T 32 . e.g. Vt 31 =V DD /2+Vt 32 . Thereafter, the PN junction will never be turned on during normal operation.

A typical operation parameters can be described as follows:

T 31 is at high state when the gate G 31 is applied with a voltage of V DD , and T 31 is at low state when the gate G 31 is applied with a voltage of V DD /2. In the meanwhile, T 32 is at high state when the gate G 32 is applied with a voltage of V DD /2, and T 32 is at low state when the gate G 32 is applied with a voltage of 0V. The states for transistors T 31 , T 32 are summarized as follows:

Transistor T31 Transistor T32 with Gate G31 with Gate G32 High V DD V DD /2 Low V DD /2 0 V FIG. 4 Shows a First Embodiment—Continuous Multigate Transistors in Series Connection

The continuous multigate transistors in series connection as shown in FIG. 4 , comprises:

A first gate G 41 (N) made of semiconductor material and doped with a first dopant, e.g. N type dopant; a second gate G 42 (P), adjacent to the first gate G 41 (N), made of semiconductor material and doped with a second dopant, e.g. P type dopant. A dielectric layer 41 is made under the first gate G 41 (N) and the second gate G 42 (P). The dielectric layer 41 has a first end (i.e. left side of the figure) and a second end (i.e. right side of the figure). A source S is made under and on the left side of the dielectric layer 41 . A drain D is made under and on the right side of the dielectric layer 41 . There is semiconductor material 43 between the source S and the drain D.

The adjacent transistors T 41 , T 42 are made side by side and with gates doped with different dopant. Furthermore, the adjacent transistors have different threshold voltage (Vt) from each other. A length of 4 L for the adjacent transistor in X direction is only four-fifth (⅘) of that for the traditional transistors in parallel connection as shown in FIG. 2 . ⅘ is calculated from comparison of the corresponding lengths 4 L v. 5 L, and then, 4 L/5 L=⅘.

When the number of transistor is extremely large to be made on a single chip, the occupied area of a single chip on the semiconductor wafer saves half. The occupied area for a single chip according to this embodiment and compared with a traditional one as shown in FIG. 2 is as follows:

The length in X direction for traditional transistors in series connection is: (2n+1)L. However, the length in X direction for continuous multigate transistors in series connection is: (n+2)L

Wherein, n is the number of transistors. L is a unit length of a design rule for a transistor.

(2n+1)L is simplified to be 2 nL when n is extremely a large number.

(n+2)L is simplified to be nL when n is extremely a large number.

=

The threshold voltages setting are the same as that described for FIG. 3 as an example. A typical operation parameters can be described as follows:

T 41 is at high state when the gate G 41 is applied with a voltage of V DD , and T 41 is at low state when the gate G 41 is applied with a voltage of V DD /2. In the meanwhile, T 42 is at high state when the gate G 42 is applied with a voltage of V DD /2, and T 42 is at low state when the gate G 42 is applied with a voltage of 0V. The states for transistors T 41 , T 42 are summarized as follows:

FIG. 5A . illustrates an embodiment wherein an additional transistor added with respect to the embodiment illustrated in FIG. 3 . In this embodiment a third transistor T 33 is added after transistor T 32 ,the transistor T 33 has a gate G 33 doped with N dopant. The dimension in Y direction for three paralleled transistors of the present invention is 3 L.

FIG. 5B . illustrates an embodiment wherein an additional transistor being added with respect to the embodiment illustrated in FIG. 3 . In this embodiment, a third transistor T 30 is added before transistor T 31 , the transistor T 30 has a gate G 30 doped with P dopant. The dimension in Y direction for three paralleled transistors of the present invention is 3 L.

FIG. 6A . illustrates an embodiment wherein an additional transistor being added with respect to the embodiment illustrated in FIG. 4 . In this embodiment a third transistor T 43 is added to the right of transistor T 42 , the transistor T 43 has a gate G 43 doped with N dopant. The dimension in X direction for three continuous serial transistors of the present invention is 5 L.

FIG. 6B . illustrates an embodiment wherein an additional transistor being added with respect to the embodiment illustrated in FIG. 4 . In this embodiment a third transistor T 40 is added to the right of transistor T 41 , the transistor T 40 has a gate G 40 doped with P dopant. The dimension in X direction for three continuous serial transistors of the present invention is 5 L.

While the preferred several embodiments have been described by way of example, it will be apparent to those skilled in the art that various modifications may be made in the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of the present invention, as defined by the appended claims.