System for displaying image and digital-to-analog converting method

1. Field of the Invention

The invention relates to a D/A converting circuit, and in particular relates to a low powered D/A converting circuit.

2. Description of the Related Art

FIG. 1 is a conventional four-bit resisting digital to analog converter (D/A converter) 100 . The four-bit resisting D/A converter 100 comprises sixteen serial resistors (R 1 ˜R 16 ) and sixty four (4*16) switch transistors. The serial resistors are coupled between a reference voltage Vref and a ground voltage GND. As shown in FIG. 1 , the four-bit resisting D/A converter 100 uses serial resistors (R 1 ˜R 16 ) to generate sixteen different voltages and controls turning on or off of switch transistors according to digital data (D 1 , D 2 , D 3 and D 4 ) to output different output voltages corresponding to digital data (D 1 , D 2 , D 3 and D 4 ) to output terminal 101 . Though the four-bit resisting D/A converter 100 can rapidly generate different output voltages corresponding to digital data (D 1 , D 2 , D 3 and D 4 ) by using the voltage dividing method. However, resistors and switch transistor are required more for higher resolution. For example, if the converter is an eight-bit converter, the converter needs 512 serial resistors and 2048 switch transistors. The required circuit layout size is much larger than the four-bit converter. Thus, the resisting D/A converter is not suitable for high-resolution D/A converter application. In addition, a lot of power consumption is required by the resisting D/A converter.

Recently, with display panel trends of higher resolution, lower power and smaller size display panels, reduction of power consumption and circuit layout size have become more and more important.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

An embodiment of a digital to analog converter is provided. The digital to analog converter comprises a charge sharing circuit and a voltage boosting circuit. The charge sharing circuit receives first to (N-1)th bits of serial digital signals by sequence and shares and stores charges in a first capacitor and a second capacitor by sequence according to a reference voltage, a ground voltage, a first clock signal and the first to (N−1)th bits of serial digital signals. The voltage boosting circuit determines whether to boost a first terminal and a second terminal of the second capacitor to the reference voltage according to a second clock signal and an Nth bit of the serial digital signal after receiving the (N−1)th bit of the serial digital signal. The charge sharing circuit outputs an analog signal from the second terminal of the second capacitor after the voltage boosting circuit receives the Nth bit of the serial digital signal.

Another embodiment of a digital to analog converting method is provided. The method comprises: (a) sharing and storing charges in a first capacitance and a second capacitance by sequence according to a reference voltage, a ground voltage, a first clock and first to (N−1)th bits of serial digital signals; (b) deciding whether to boost a first terminal and a second terminal of the second capacitance to the reference voltage according to a second clock signal and the Nth bit of the serial digital signal; and (c) outputting an analog signal from the second terminal of the second capacitance after a voltage boosting circuit receives the Nth bit of the serial digital signal.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 is a conventional four-bit resisting digital to analog converter (D/A converter);

FIG. 2 is a schematic block diagram of a digital to analog converter (D/A converter) according to an embodiment of the invention;

FIG. 3 is a schematic block diagram of a digital to analog converter (D/A converter) according to another embodiment of the invention;

FIG. 4 is a digital to analog converter (D/A converter) according to another embodiment of the invention;

FIG. 5 is a flow chart of digital signals converting to analog signals according to another embodiment of the invention; and

FIG. 6 schematically shows another embodiment of a system for displaying images.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 2 is a schematic block diagram of a digital to analog converter (D/A converter) 250 according to an embodiment of the invention. The D/A converter 250 comprises a charge sharing circuit 210 , a voltage boosting circuit 220 and a discharging circuit 230 . The charge sharing circuit 210 receives serial digital signals D[ 1 ]˜D[n−1] by sequence. Then, the voltage boosting circuit 220 receives the serial digital signal D[n]. The D/A converter 250 outputs analog signals 252 to a loading circuit 260 according to the serial digital signal D[ 1 :n]. Meanwhile, the discharging circuit 230 discharges the charge sharing circuit 210 according to a reset signal Reset. More detailed discussion of circuitry and operation of the D/A converter 250 are presented as following.

FIG. 3 is a schematic block diagram of a digital to analog converter (D/A converter) 350 according to another embodiment of the invention. The D/A converter 350 comprises a charge sharing circuit 310 , a voltage boosting circuit 320 and a discharging circuit 330 . The charge sharing circuit 310 can comprise a third switch M 3 , fourth switch M 4 , fifth switch M 5 , sixth switch M 6 , seventh switch M 7 , eighth switch M 8 , ninth switch M 9 , tenth switch M 10 , first capacitor C 1 and second capacitor C 2 . The third switch M 3 is coupled between a reference voltage Vref 1 and a node P 1 . The third M 3 receives the serial digital signals D[ 1 ]˜D[n−1] by sequence and is turned on or off according to the digital signals D[ 1 ]˜D[n−1]. The fourth switch M 4 is coupled between a ground voltage GND and a node P 1 . The third M 4 also receives the serial digital signals D[ 1 ]˜D[n−1] by sequence and is turned on or off according to the digital signals D[ 1 ]˜D[n−1]. When the third switch M 3 is turned, the fourth switch M 4 is turned off. When the fourth switch M 4 is turned on, the third switch M 3 is turned off. The fifth switch M 5 is coupled between the reference voltage Vref 1 and a node P 2 and turned on or off according to the voltage level of the node P 1 . The sixth switch M 6 is coupled between the ground voltage GND and the node P 2 and turned on or off according to the voltage level of the node P 1 . When the fifth switch M 5 is turned on, the sixth switch M 6 is turned off and vice versa. The seventh switch M 7 and the ninth switch M 9 are coupled between the node P 2 and the first capacitor C 1 and turned on or off respectively according to clock signals CLK and BCLK. The eighth switch M 8 and the tenth switch M 10 are coupled between the first capacitor C 1 and the second capacitor C 2 and turned on or off respectively according to clock signals BCLK and CLK. When the seventh switch M 7 and the ninth switch M 9 are turned on, the eighth switch M 8 and the tenth switch M 10 are turned off. When the seventh switch M 7 and the ninth switch M 9 are turned off, the eighth switch M 8 and the tenth switch M 10 are turned on. The first capacitor C 1 is coupled between the seventh switch M 7 and ground voltage GND. The second capacitor C 2 is coupled between the voltage boosting circuit 320 and a loading circuit 360 . The first bit of the serial digital signals D[ 1 ] is the least significant bit (LSB) and the Nth bit of the serial digital signals D[n] is the Most significant bit (MSB).

The voltage boosting circuit 320 can comprise a NAND gate 322 , first switch M 1 and second switch M 2 . The NAND gate 322 generates a control signal 324 according to the serial digital signal D[n] and a clock signal CK 8 . The first switch M 1 is coupled between the second capacitor C 2 and the ground voltage GND. When the charge sharing circuit 310 receives the serial digital signal D[ 1 ]˜D[n−1], the first switch M 1 is turned on according to the control signal 324 and the second capacitor C 2 directly connects to the ground voltage GND. The second switch M 2 is coupled between the second capacitor C 2 and the reference voltage Vref 1 . When the D/A converter 350 receives the serial digital signal D[n], the second switch M 2 directs the second capacitor C 2 to connect to the reference voltage Vref 1 or the ground voltage GND according to the control signal 324 .

The charge discharging circuit 330 can be an eleventh switch M 11 coupled between the ground voltage GND and the loading circuit 360 . After the D/A converter 350 receives the serial digital signals D[ 1 ]˜D[n] and the charge sharing circuit 310 outputs an analog signal 352 , the eleventh switch M 11 discharges the first capacitor C 1 and the second capacitor C 2 according to the reset signal Reset.

According to an embodiment of the invention, the charge storing sizes of the first capacitor C 1 and the second capacitors C 2 can be the same. The second, third, fifth, eighth, ninth switches can be PMOS transistors and the first, fourth, sixth, seventh and tenth switches can be NMOS transistors. When the serial digital signals D[ 1 ]˜D[n−1] are at a low voltage level, the third switch M 3 is turned on and the fourth switch M 4 is turned off. The node P 1 is at the reference voltage Vref 1 . The fifth switch M 5 is turned off and the sixth switch M 6 is turned on. Thus, the node P 2 is at the ground voltage GND. When the serial digital signals D[ 1 ]˜D[n−1] are at a high voltage level, the third switch M 3 is off and the fourth switch M 4 is turned on. The node P 1 is at the ground voltage GND. The fifth switch M 5 is turned on and the sixth switch M 6 is turned off. Thus, the node P 2 is at the reference voltage Vref 1 .

Since the clock signals CLK and BCLK are opposite to each other, the seventh switch M 7 and the ninth switch M 9 are turned on or off simultaneously and the eighth switch M 8 and the tenth switch M 10 are turned on or off simultaneously. Further, the seventh switch M 7 and the tenth switch M 10 are not turned on simultaneously and the eighth switch M 8 and the ninth switch M 9 are also not turned on simultaneously. When the seventh switch M 7 and ninth switch M 9 are turned on, the first capacitor C 1 charges or discharges according to the voltage level of the node P 2 . When the fifth switch M 5 is turned on, the first capacitor C 1 charges. When the sixth switch M 6 is turned on, the first capacitor discharges. When the eighth switch M 8 and the tenth switch M 10 are turned on (the seventh switch M 7 and the ninth switch M 10 are turned off), the second capacitor C 2 and the first capacitor C 1 share charges to determine the cross voltages of the second capacitor C 2 and the first capacitor C 1 . According to another embodiment of the invention, the charge sharing circuit 310 is not composed of the ninth transistor M 9 and the tenth transistor M 10 .

When the D/A converter 350 receives the serial digital signals D[ 1 ]˜D[n−1], the control signal 324 is at a high voltage level. The first switch M 1 is turned on and the second capacitor C 2 is coupled between the ground voltage GND and the loading circuit 360 . When the D/A converter 350 receives the serial digital signal D[n], the control signal 324 is at a high or low voltage level according to the clock signal CK 8 and the serial digital signal D[n]. According to another embodiment of the invention, when the serial digital signal D[n] is zero, the control signal 324 is at a high voltage level. The first switch M 1 is turned on and the second capacitor C 2 is coupled between the ground voltage GND and the loading circuit 360 . When the serial digital signal D[n] is one, the control signal 324 is at a low voltage level. The second switch M 2 is turned on and the second capacitor C 2 is coupled between the reference voltage Vref 1 and the loading circuit 360 . Thus, both terminals of the second capacitor C 2 are simultaneously boosted to the reference voltage Vref 1 .

As shown in FIG. 3 , assuming the serial digital signal D[n] is an eight-bit serial digital signal, the voltage Vout of the analog signal 352 is

Since the reference voltage Vref 1 is half of the power voltage Vdd (Vref 1 =Vdd/2), the D/A converter 350 uses the reference voltage Vref 1 , not the power voltage Vdd. Thus, the D/A converter 350 consumes less power.

FIG. 4 is a digital to analog converter (D/A converter) 450 according to another embodiment of the invention. The D/A converter 450 is similar to the D/A converter 350 . The difference is the voltage boosting circuit. The voltage boosting circuit 420 can comprise a NAND gate 422 and a switch SW 1 . The NAND gate 422 generates a control signal 424 according to the Nth bit of the serial digital signals D[n] and the clock signal CK 8 . The switch SW 1 is coupled between the second capacitor C 2 and the reference voltage Vref 1 or the ground voltage GND. When the charge sharing circuit 310 receives the serial digital signals D[ 1 ]˜D[n−1], the first terminal of the second capacitor C 2 is coupled to the ground voltage GND. When the D/A converter 450 receives the Nth bit of the serial digital signal D[n], the second capacitor C 2 is coupled to the reference voltage Vref 1 or the ground voltage GND according to the control signal 424 . Since other operations of the D/A converter 450 are the same as those of the D/A converter 350 , detailed descriptions are not described again.

FIG. 5 is a flow chart of digital signals converting to analog signals according to another embodiment of the invention. In step 520 , the first to (N−1)th bits of the serial digital signals are received. The charges are shared and stored in the first capacitor C 1 and the second capacitor C 2 of the charge sharing circuit 310 by sequence according to the reference voltage Vref 1 , ground voltage GND, first clock signal CLK and first to (N−1)th bits of the serial digital signals D[ 1 ]˜D[n−1]. In step 540 , the Nth bit of the serial digital signal D[n] is received, and then it is decided whether to boost the first terminal and the second terminal of the second capacitor C 2 to the reference voltage Vref 1 according to the second clock signal CLK 8 and the Nth bit of the serial digital signal D[n]. After the voltage boosting circuit 320 receives the Nth bit of the serial digital signal D[n], the analog signal 352 is outputted from the second terminal of the second capacitor C 2 (Step S 560 ). The charges of the first capacitor C 1 and the second capacitor C 2 are discharged according to the reset signal Reset (step S 580 ).

FIG. 6 schematically shows another embodiment of a system for displaying images which, in this case, is implemented as a display panel 400 or an electronic device 600 . As shown in FIG. 6 , display panel 400 comprises the D/A converter 250 of FIG. 2 . The display panel 400 can form a portion of a variety of electronic devices (in this case, electronic device 600 ). Generally, an electronic device 600 can comprise a display panel 400 and a power supply 500 . Further, the power supply 500 is operatively coupled to the display panel 400 and provides power to the display panel 400 . The electronic device 600 can be a mobile phone, digital camera, PDA (personal data assistant), notebook computer, desktop computer, television, or portable DVD player, for example.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.