Bootstrap circuit for H-bridge structure utilizing N-channel high-side fets

The invention is generally directed to the area of H-Bridge circuits. The invention is directed, particularly, but not exclusively to a method and apparatus for driving high-side switching devices in an H-Bridge circuit.

H-Bridge circuits may be employed as power switching circuits. For example, H-Bridge circuits may be employed as drive circuitry for electrical motors, as drive circuitry for electroluminescent lamp circuits, as DC/AC inverter circuitry, and as regulator output circuitry in switching regulators. Further H-Bridge circuits are employed in a variety of other applications and circuits.

In these and other applications, H-Bridge circuits may be employed to selectively control a direction of current flow through, or the polarity of voltage to, an element. The element may be an inductor, a motor, an electroluminescent lamp circuit, a coil of a transformer, a solenoid, an electrical device, an electrical component, and/or the like.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale.

For a better understanding of the present invention, reference will be made to the following Detailed Description, which is to be read in association with the accompanying drawings, wherein:

FIG. 1 is a block diagram of an embodiment of a circuit according to aspects of the present invention;

FIG. 2 is a schematic diagram of another embodiment of a circuit according to aspects of the present invention;

FIG. 3 is a block diagram of an embodiment of a regulator controller according to aspects of the present invention;

FIG. 4 is a schematic diagram of yet another embodiment of a circuit according to aspects of the present invention; and

FIG. 5 is a schematic diagram of a further embodiment of a circuit according to aspects of the present invention.

Various embodiments of the present invention will be described in detail with reference to the drawings. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference. References in the singular are made merely for clarity of reading and include plural reference unless plural reference is specifically excluded. The meaning of either “in” or “on” includes both “in” and “on.” The term “or” is an inclusive “or” operator, and is equivalent to the term “and/or” unless specifically indicated otherwise. The term “based on” or “based upon” is not exclusive and is equivalent to the term “based, at least in part, on” and includes being based on additional factors, some of which are not described herein. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function or functions. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. A “signal” may be used to communicate using active high, active low, time multiplexed, synchronous, asynchronous, differential, single-ended, or any other digital or analog signaling or modulation techniques. A “signal” may also be employed to provide and/or transmit power. Where either a field effect transistor (FET) or a bipolar transistor may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa. A FET or bipolar transistor is “closed” when the status of the transistor is such that there is a current path through the transistor. A FET or bipolar transistor is “open” when the status of the transistor is such that there is substantially no current path through the transistor. However, while a transistor is open, some leakage current may flow through the transistor. The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may.

Briefly stated, the invention relates to an apparatus and method for driving high-side switching devices in an H-Bridge circuit. The apparatus includes first and second N-Channel high-side switching devices. Each of the high-side switching devices is associated with, and is selectively driven by, a driver circuit. Each of the driver circuits is associated with, and is powered from, a bootstrap capacitor. The apparatus further includes a cross-couple circuit that is arranged to charge each of the bootstrap capacitors based, at least in part, on whether the low-side switching device that is associated with the other bootstrap capacitor is open or closed.

FIG. 1 is a block diagram of an embodiment of circuit 100 . Circuit 100 may include switching devices SW 1 -SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , cross-couple circuit 110 , and element 120 .

In one embodiment, circuit 100 is arranged as buck/boost regulator output circuitry to regulate regulated power signal VOUT to a substantially constant voltage over a range of input voltages of input power signal VIN. For example, circuit 100 may be arranged to regulate regulated power signal VOUT to +12 volts, +3.3 volts, +1.8 volts, and/or the like.

As illustrated, circuit 100 is coupled to positive input power supply signal VIN and to ground. However, in other embodiments, circuit 100 may be coupled between a positive input power supply and a negative input power supply, between ground and a negative power supply, between two positive power supplies, and/or the like.

In one embodiment, switching devices SW 1 -SW 4 are arranged in an H-Bridge configuration to selectively couple first switch node NS 1 to input power signal VIN or to ground and to selectively couple second switch node NS 2 to regulated power signal VOUT or to ground. Switching devices SW 1 -SW 4 may include N-Channel FETs, such as MOSFETs, junction field-effect transistors (JFETs), insulated gate bi-polar transistors (IGBTs), and/or the like. However, in other embodiments, P-Channel FETs, BJTs, relays, other electrically controlled switching devices, and/or the like, may also be suitably employed in switching devices SW 1 -SW 4 .

In one embodiment, driver circuit DR 1 is arranged to provide drive signal S 1 DR to switching device SW 1 based, at least in part, on switch control signal SCTL 1 . Also, in one embodiment, driver circuit DR 2 is arranged to provide drive signal S 2 DR to switching device SW 2 based, at least in part, on switch control signal SCTL 2 . Level-shift circuits, inverting or non-inverting buffers, amplifier circuits, comparators, and/or the like, may be employed in driver circuits DR 1 and DR 2 . In one embodiment, low-side driver circuits may also be provided to provide drive signals to switching devices SW 3 and SW 4 .

In one embodiment, driver circuits DR 1 and DR 2 include level-shift circuits that provide output logic levels that are respectively referenced to the voltage at nodes NS 1 and NS 2 . By respectively referencing driver circuits DR 1 and DR 2 to the voltage at nodes NS 1 and NS 2 , driver circuits DR 1 and DR 2 may be enabled to provide drive signals S 1 DR and S 2 DR to drive N-Channel devices in switching devices SW 1 and SW 2 while the voltages at nodes NS 1 and NS 2 are not substantially equal to ground.

Bootstrap capacitors C 1 and C 2 are respectively arranged to provide power to driver circuits DR 1 and DR 2 . Bootstrap capacitors C 1 and C 2 are further arranged to be charged based, at least in part, on whether switching devices SW 3 and SW 4 are open or closed. For example, in one embodiment, circuit 100 is arranged such that capacitor C 1 is charged via bootstrap diode D 1 while switching device SW 3 is closed and is charged via cross-couple circuit 110 while switching device SW 4 is closed. Likewise, in this embodiment, circuit 100 is arranged such that capacitor C 2 is charged via bootstrap diode D 2 while switching device SW 4 is closed and is charged via cross-couple circuit 110 while switching device SW 3 is closed.

Bootstrap capacitors C 1 and C 2 may each be any type of capacitor. For example, bootstrap capacitors C 1 and C 2 may be ceramic capacitors (e.g., X5R, NPO, or X7R), tantalum capacitors, electrolytic capacitors, paper capacitors, plastic film capacitors, glass capacitors, and/or the like. Also, bootstrap capacitors C 1 and C 2 may be formed on a monolithic integrated circuit. Further, the capacitance value each of bootstrap capacitors C 1 and C 2 may be any suitable value. In one embodiment, the capacitance value is selected based, at least in part, on the power requirements of driver circuits DR 1 and DR 2 ; the drive requirements of switching devices SW 1 and SW 2 ; the expected duty-cycles for switching device SW 1 -SW 4 ; and/or the like.

In one embodiment, bootstrap diodes D 1 and D 2 are arranged such that substantially no current flows from node NB 1 to bootstrap power signal VDD or from node NB 2 to bootstrap power signal VDD while enabling current flow from bootstrap power signal VDD to nodes NB 1 and NB 2 . Bootstrap diodes D 1 and D 2 may be Schottky or other fast acting diodes. However, any other suitable diode may be employed as bootstrap diodes D 1 and D 2 . Also, bootstrap power signal VDD may be provided from any suitable power source. For example, bootstrap power signal VDD may be provided from input power signal VIN, from a battery, from a regulator, and/or the like. In one embodiment, bootstrap power signal VDD is provided by a low dropout or other linear regulator.

In one embodiment, cross-couple circuit 110 is arranged to charge bootstrap capacitor C 1 based, at least in part, on whether switching device SW 4 is open or closed and is further arranged to charge bootstrap capacitor C 2 based, at least in part, on whether switching device SW 3 is open or closed. Cross-couple circuit 110 is described in further detail below, for certain embodiments.

Element 120 may be an inductor, a motor, an electroluminescent lamp circuit, a coil of a transformer, a solenoid, an electrical device, an electrical component, and/or the like, through which a direction of current flow, or a polarity of voltage to, may be selectively controlled. For example, circuit 100 may provide a current path from node NS 1 , through element 120 , to node NS 2 by closing switching devices SW 1 and SW 4 . Likewise, circuit 100 may provide a current path from node NS 2 , through element 120 , to node NS 1 by closing switching devices SW 2 and SW 3 . Element 120 may be virtually any device through which current may flow.

FIG. 2 is a schematic diagram of an embodiment of circuit 200 . Circuit 200 may be employed as an embodiment of circuit 100 of FIG. 1 . Circuit 200 may include switching devices SW 1 -SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , cross-couple circuit 210 , and element 220 . In one embodiment, circuit 200 is arranged to operate as regulator output circuitry in a buck/boost regulator.

Cross-couple circuit 210 may include resistor R 1 . In one embodiment, resistor R 1 is coupled between nodes NB 1 and NB 2 such that capacitor C 1 may be charged via resistor R 1 while switching device SW 4 is closed and such that capacitor C 2 may be charged via resistor R 1 while switching device SW 3 is closed.

In one embodiment, the value of resistor R 1 defines, in part, an RC time constant that is related to the charging characteristics of capacitors C 1 and C 2 . Accordingly, the value of R 1 may be selected to define the RC time constant at any suitable value. In one embodiment, the value of resistor R 1 is less than approximately 1 MegaOhm. However, in certain embodiments, the range of suitable values of resistor R 1 includes values spanning orders of magnitude (e.g., 100 Ohms-10 MegaOhms).

Switching devices SW 1 and SW 2 may respectively include N-Channel FETs M 1 and M 2 . In one embodiment, N-Channel FETs M 1 and M 2 are enhancement mode MOSFETs. However, JFETs, IGBTs, and/or the like, may also be employed in switching devices SW 1 and SW 2 instead of N-Channel FETs. These and other variations are within the spirit and scope of the invention.

Element 220 may include inductor L 1 that is coupled between nodes NS 1 and NS 2 . Inductor L 1 may be any suitable inductor.

Switching devices SW 3 and SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , and bootstrap diodes D 1 and D 2 may be employed as respective embodiments of switching devices SW 3 and SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , and bootstrap diodes D 1 and D 2 of FIG. 1 .

In one embodiment, circuit 200 is arranged operate as output circuitry for a synchronously rectified switching buck/boost regulator by selectively coupling input power signal VIN to inductor L 1 of element 220 and by selectively coupling inductor L 1 to regulated power signal VOUT. In another embodiment, an asynchronously rectified switching buck/boost regulator may be provided. For example, switching devices SW 3 and SW 4 may include asynchronous rectification devices (e.g., diodes).

In one example of buck mode operation, while switching device SW 4 is held opened and switching device SW 2 is held closed, switching devices SW 1 and SW 3 are switched to selectively couple input power signal VIN or ground to inductor L 1 of element 220 . While switching device SW 1 is closed, switching device SW 3 is open and energy is provided from input power signal VIN to inductor L 1 , at node NS 1 , and to regulated power signal VOUT. At some point, switching device SW 1 is opened and switching device SW 3 is closed to provide rectification. Current then flows from ground to inductor L 1 , at node NS 1 . This cycle repeats on a periodic basis.

In an example of boost mode operation, while switching device SW 3 is held opened and switching device SW 1 is held closed, switching devices SW 2 and SW 4 are switched to selectively couple inductor L 1 of element 220 , at node NS 2 , to regulated power signal VOUT or ground. While switching device SW 4 is closed, switching device SW 2 is open to isolate regulated power signal VOUT from ground. At some point, switching device SW 4 is opened and switching device SW 2 is closed. Energy then flows from inductor L 1 to regulated power signal VOUT. This cycle repeats on a periodic basis.

In the operation of one embodiment, one of driver circuits DR 1 or DR 2 is switching its associated switching device (e.g., not holding it closed) regardless of whether circuit 200 is providing buck mode regulation or boost mode regulation. Based on this switching, the bootstrap capacitor associated with the switching driver circuit will charge via its associated bootstrap diode and the bootstrap capacitor associated with the other driver circuit will be charged via cross-couple circuit 210 .

FIG. 3 is a block diagram of an embodiment of regulator controller 350 . Regulator controller 350 includes reference source REF 1 , error amplifier 352 , switch control logic 354 , and pulse modulation circuit 356 . Regulator controller 350 may be employed, for example, to control the operation of circuit 200 of FIG. 2 by monitoring regulated power signal VOUT or another output signal relative to signal VREF and by modulating switch control signals SCTL 1 -SCTL 4 based, at least in part, on such monitoring.

In one embodiment, error amplifier 352 is arranged to provide error signal ERR based on the difference between regulated power signal VOUT and reference signal VREF. Although not shown, error amplifier 352 may also include compensation circuitry. In other embodiments, other circuitry may be employed instead of error amplifier 352 . For example, other differential amplifier circuits, instrumentation amplifiers, analog or digital comparators, operational amplifiers, ring analog-to-digital converters, controller analog-to-digital converters, and/or the like, may be suitably employed instead of error amplifier 352 . In one embodiment, a controller analog-to-digital converter, such as described by U.S. Pat. No. 7,250,884 to Hee Wong, is employed. The entirety of U.S. Pat. No. 7,250,884 is hereby incorporated by reference.

Reference signal VREF is provided by reference source REF 1 . Reference source REF 1 may be either internal or external and may provide a reference voltage of any suitable value. For example, reference source REF 1 may include a band-gap reference circuit. In other embodiments, a reference current source may be suitably employed instead of a reference voltage source.

In one embodiment, switch control logic 354 is arranged to receive control inputs 360 and to provide one or more control signals CONTROL_OUT to pulse modulation circuit 356 . Signal(s) CONTROL_OUT may be employed to indicate an operational mode (e.g. buck, boost, PFM, PWM, startup, shutdown, etc.); to modify switching thresholds; to adjust timing; and/or the like. Control signals 360 may include clock signal CLK, various reference voltages, load current limits, load current indicators, input current limits, input current indicators, temperature limits, temperature indicators, compensation signals, mode selection signals, and/or the like.

Pulse modulation circuit 356 is arranged provide switch control signals SCTL 1 -SCTL 4 based on signals ERR, CONTROL_OUT, and/or CLK. In one embodiment, pulse modulation circuit 356 includes a pulse width modulation (PWM) circuit. In other embodiments, pulse modulation circuit 356 may include a pulse frequency modulation (PFM) circuit, a charge transfer modulation (CTM) circuit, hybrid circuits, and/or the like.

In some embodiments, regulator controller 350 may differ from the illustrated embodiment. For example, regulator controller 350 may include over-voltage protection circuitry, under-voltage protection circuitry, over-current protection circuitry, under-current protection circuitry, temperature protection circuitry, or battery status monitoring circuitry; regulator controller 350 may be arranged as a current mode regulator controller; and/or the like. These and other variations are within the spirit and scope of the invention.

FIG. 4 is a schematic diagram of an embodiment of circuit 400 . Circuit 400 may be employed as an embodiment of circuit 100 of FIG. 1 . Circuit 400 may include switching devices SW 1 -SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , cross-couple circuit 410 , and element 420 . In one embodiment, circuit 400 is arranged to operate as regulator output circuitry in a buck/boost regulator.

In one embodiment, cross-couple circuit 410 includes resistors R 2 and R 3 and cross-couple diodes D 3 and D 4 . Resistors R 2 and R 3 and cross-couple diodes D 3 and D 4 are arranged such that the RC time constants for each of bootstrap capacitors C 1 and C 2 is separately defined. This, for example, may simplify circuit design if driver circuit DR 1 has different power requirements than those of driver circuit DR 2 ; if switching device SW 1 is different from switching device SW 2 ; if different capacitors are employed for bootstrap capacitors C 1 and C 2 ; if switching devices SW 1 and SW 2 are expected to have different duty-cycles; and/or the like. Further, in one embodiment, different voltages (not shown) are applied to the anodes of each of bootstrap diodes D 1 and D 2 . In these and other embodiments, resistors R 2 and R 3 may be selected such that the RC time constants for each of bootstrap capacitors C 1 and C 2 are substantially equal. However, resistors R 2 and R 3 may also be selected such that the RC time constants for each of bootstrap capacitors C 1 and C 2 are different.

In one embodiment, cross-couple diodes D 3 and D 4 are Schottky or other fast acting diodes that are arranged such that bootstrap capacitor C 1 may be charged via bootstrap diode D 2 , cross-couple diode D 4 , and resistor R 3 and such that bootstrap capacitor C 2 may be charged via bootstrap diode D 1 , cross-couple diode D 3 , and resistor R 2 . However, other suitable diodes may be employed as diodes D 3 and D 4 .

Also, switching devices SW 3 and SW 4 of circuit 400 , as shown in FIG. 4 , respectively include N-Channel FETs M 3 and M 4 . However, as discussed above, other switching devices may be employed in switching devices SW 3 and SW 4 instead of N-Channel FETs.

Switching devices SW 1 and SW 2 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , and element 420 may be employed as respective embodiments of switching devices SW 1 and SW 2 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , and element 120 of FIG. 1 .

FIG. 5 is a schematic diagram of an embodiment of circuit 500 . Circuit 500 may be employed as an embodiment of circuit 100 of FIG. 1 . Circuit 500 may include switching devices SW 1 -SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , cross-couple circuit 510 , and element 520 . In one embodiment, circuit 500 is arranged to operate as motor control circuitry to reversibly drive motor MOTOR 1 of element 520 .

In one embodiment, circuit 500 is arranged to selectively control a direction of current flow through, or the polarity of voltage to, element 520 by selectively providing a current path between input power signal VIN and ground. For example, circuit 500 may provide a current path from node NS 1 , through element 520 , to node NS 2 by closing switching devices SW 1 and SW 4 . Likewise, circuit 500 may provide a current path from node NS 2 , through element 520 , to node NS 1 by closing switching devices SW 2 and SW 3 . As discussed above, circuit 500 may be coupled between other voltage sources.

In one embodiment, element 520 includes motor MOTOR 1 . MOTOR 1 may be, for example, a DC brushless motor, a linear motor, a stepper motor, a universal motor, a coreless DC motor, a brushed DC motor, a ball-bearing DC motor, and/or the like. In one embodiment, MOTOR 1 is a stepper motor.

In other embodiments, an electroluminescent lamp circuit, a coil of a transformer, a solenoid, an electrical device, an electrical load, an electrical component, and/or the like, may be employed in element 520 , or driven by circuit 500 , instead of MOTOR 1 . These and other variations are within the spirit and scope of the invention.

Switching devices SW 1 -SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , and cross-couple circuit 510 may be employed as respective embodiments of switching devices SW 1 -SW 4 , driver circuits DR 1 and DR 2 , bootstrap capacitors C 1 and C 2 , bootstrap diodes D 1 and D 2 , and cross-couple circuit 110 of FIG. 1 .

The above specification, examples and data provide a description of the method and applications, and use of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, this specification merely set forth some of the many possible embodiments for the invention.