Output power detection circuit with threshold limiting characteristics

This application hereby claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application Ser. No. 60/898,901, filed 1 Feb. 2007, entitled “OUTPUT POWER DETECTION WITH THRESHOLD LIMITING CHARACTERISTICS”.

The present invention is related to that disclosed in U.S. Provisional Patent Application Ser. No. 60/898,901. U.S. Provisional Patent Application Ser. No. 60/898,901 is assigned to the assignee of the present application. The subject matter disclosed in U.S. Provisional Patent Application Ser. No. 60/898,901 is hereby incorporated by reference into the present disclosure as if fully set forth herein.

Embodiments of the present invention relate generally to radio frequency (RF) power amplifiers and more specifically, to an output power detection circuit with threshold limiting characteristics.

Radio frequency (RF) power amplifiers are often used in wireless devices, such as cellular telephones. Extending the battery life is a key concern for users and manufacturers of these wireless devices. One of the key factors in determining the battery life of a wireless device is the power consumption of the RF power amplifiers. The RF power amplifiers are designed to operate into an optimal load impedance and are typically coupled to an antenna of the wireless device.

However, under a load mismatch condition, such as, for example, when the antenna of the wireless device approaches objects (e.g., metal structures, human contact, or a hand in the near field of the antenna, or the like), the load impedance of the RF power amplifier changes and the RF power amplifier draws excess current. In some cases, the current can exceed more than two times the current drawn under an optimal load impedance. When the RF power amplifier draws excess current, the battery life of the wireless device is reduced. In addition, the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) linearity limits are often exceeded when the RF power amplifier draws excess current. This reduction in battery life and exceeding of the ACPR and EVM limits are undesirable.

FIG. 1 illustrates a schematic diagram of a detection circuit 100 according to the prior art. Detection circuit 100 includes RF amplifier stages A 1 -A 3 , a voltage detection V DET signal, an external bias control signal, an RF IN signal, an RF OUT signal, an output coupler 102 , a diode D 1 , and a collector voltage V CC . Output coupler 102 senses the forward output power from RF amplifier stages A 1 -A 3 (i.e., RF OUT signal), which is rectified by diode D 1 to provide a voltage detection V DET signal. The voltage detection V DET signal is applied to an external power control device to adjust the external bias control Ext BIAS signal until the detected output voltage from output coupler 102 equalizes with the power control signal voltage of the external power control device, thereby substantially maintaining a constant forward output power from RF amplifier stages A 1 -A 3 .

However, the use of detection circuit 100 is disadvantageous, because the external power control device does not provide a mechanism to limit the amount of current that is drawn by RF amplifier stages A 1 -A 3 . For example, under certain load mismatch conditions, the external power control device will continue to draw as much current as is necessary in order to maintain the forward output power of RF amplifier stages A 1 -A 3 constant with the external power control device. Among other things, this reduces the efficiency of RF amplifier stages A 1 -A 3 and decreases the battery life of the wireless device, which, as described above, is disadvantageous for users and manufacturers of these wireless devices.

FIG. 2 illustrates a schematic diagram of another detection circuit 200 according to the prior art. Detection circuit 200 includes RF amplifier stages A 1 -A 3 , voltage detection V DET signal, an external collector voltage V CC control signal, RF IN signal, RF out signal, output coupler 102 , diode D 1 , and a bias voltage V BIAS signal. Detection circuit 200 is similar to detection circuit 100 , except that instead of using an external power control device to adjust the bias current of RF amplifier stages A 1 -A 3 , detection circuit 200 uses the external power control device to adjust the collector voltage V CC of RF amplifier stages A 1 -A 3 .

However, the use of detection circuit 200 is disadvantageous, for the same reasons as discussed above with respect to detection circuit 100 . In addition, implementation of a hard current limit with detection circuits 100 and 200 is not desirable, as it may adversely affect the RF characteristics of RF amplifier stages A 1 -A 3 . For example, as the output power of RF amplifier stages A 1 -A 3 is ramping to a specified value, as defined by the external power control device, a sharp discontinuity may occur when the supply current reaches a predetermined maximum limiting value. This sharp discontinuity is commonly referred to as a hard limit and causes various spurious emissions and unwanted harmonics in the frequency domain. These spurious emissions and unwanted harmonics are undesirable.

The novel features believed to be characteristic of embodiments of the invention are set forth in the appended claims. However, embodiments of the invention will best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings, wherein embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

FIG. 1 illustrates a schematic diagram of a detection circuit according to the prior art;

FIG. 2 illustrates a schematic diagram of another detection circuit according to the prior art;

FIG. 3 illustrates a high-level block diagram of a wireless device according to an exemplary embodiment of the present invention;

FIG. 4 illustrates a schematic diagram of an output power detection circuit according to one embodiment of the present invention; and

FIG. 5 illustrates a schematic diagram of an output power detection circuit according to another embodiment of the present invention.

Reference will now be made to the following detailed description of the exemplary embodiments of the present invention. Those skilled in the art will recognize that embodiments of the present invention provide many inventive concepts and novel features that are merely illustrative and not to be construed as restrictive. Accordingly, the specific embodiments discussed herein are given by way of example and do not limit the scope of the embodiments of the present invention. In addition, those skilled in the art will understand that for purposes of explanation, numerous specific details are set forth, though embodiments of the invention can be practiced without these specific details, and that certain features have been omitted so as to more clearly illustrate embodiments of the invention.

FIG. 3 illustrates a high-level block diagram of a wireless device 300 according to an exemplary embodiment of the present invention. In one embodiment of the present invention, wireless device 300 comprises an antenna 302 , a switch/duplexer 304 , a transmitter 306 , a receiver 308 , TX/RX circuitry 310 , a speaker/microphone 312 , a main processor 314 , a display/keypad 316 , a memory 318 , and a battery 320 . Wireless device 300 may be any wireless device, including, but not limited to, conventional cellular telephones, paging devices, personal digital assistant devices, text-messaging devices, portable computers, or any other like device capable of wireless communication.

As will be explained below in greater detail, transmitter 306 comprises radio frequency (RF) power amplifier circuitry including output power detection circuitry, one or more RF power amplifier stages, and other like circuitry. In one embodiment of the present invention, the RF power amplifier circuitry of transmitter 306 is formed on a Gallium Arsenide (GaAs) substrate. However, other semiconductor materials (e.g., silicon, silicon germanium, indium phosphide, gallium nitride, silicon carbide, aluminum gallium arsenide; indium gallium arsenide; indium gallium phosphide; indium aluminum arsenide; aluminum gallium nitride; indium gallium nitride; gallium arsenide antimonide; indium gallium arsenide nitride; and aluminum arsenide) may be used. In addition, for purposes of illustration and ease of explanation, embodiments of the present invention are described in terms of bipolar junction transistor (BJT) technology (e.g., heterojunction bipolar transistors (HBTs)). However, embodiments of the invention may be practiced using other transistor technology, including, for example, but not limited to, field effect transistor (FET) technology (e.g., junction field effect transistors, heterostructure field effect transistors, modulation-doped field effect transistors, metal-semiconductor field effect transistors (MESFETs), high electron mobility transistors, metamorphic high electron mobility transistors, and pseudomorphic high electron mobility transistors (pHEMTs)) or complementary metal-oxide semiconductor (CMOS) technology.

TX/RX circuitry 310 receives from antenna 302 an incoming signal transmitted by, for example, a communication system or a wireless network provider, through switch/duplexer 304 and receiver 308 . TX/RX circuitry 310 processes and sends the incoming signal to the speaker (i.e., voice data) or to main processor 314 (e.g., web browsing) for further processing. Likewise, TX/RX circuitry 310 receives analog or digital voice data from the microphone or other outgoing data (e.g., web data, e-mail) from main processor 314 . TX/RX circuitry 310 transmits an RF signal that is transmitted through transmitter 306 via antenna 302 .

Main processor 314 executes a basic operating system program stored in memory 318 in order to control the overall operation of wireless device 300 . For example, main processor 314 controls the reception of signals and the transmission of signals by TX/RX circuitry 310 , receiver 308 , and transmitter 306 . Main processor 314 is capable of executing other processes and programs resident in memory 318 and may move data into or out of memory 318 , as required by an executing process.

Main processor 314 is also coupled to display/keypad 316 . The user of wireless device 300 uses the keypad to enter data into wireless device 300 . The display may be a liquid crystal display capable of rendering text and/or at least various graphics; alternate embodiments may use other types of displays. Battery 320 is coupled with the electrical components of wireless device 300 , in accordance with known electrical principles.

Those skilled in the art will recognize that wireless device 300 is given by way of example and that for simplicity and clarity, only so much of the construction and operation of wireless device 300 as is necessary for an understanding of the present invention is shown and described. For example, wireless device 300 is capable of communicating using one or more of a number of conventional standards, including, but not limited to GSM/EDGE, CDMA, W-CDMA, or the like. In addition, or as an alternative, although an exemplary wireless device 300 is shown and described, embodiments of the present invention contemplate any suitable component or combination of components performing any suitable tasks in association with wireless device 300 , according to particular needs. Moreover, it is understood that wireless device 300 should not be construed to limit the types of devices in which embodiments of the present invention may be implemented.

In accordance with the principles of embodiments of the present invention, the RF power amplifier circuitry of transmitter 306 of wireless device 300 provides for maintaining certain parameters within the RF power amplifier circuitry above certain threshold levels, as described below in greater detail. In addition, or as an alternative, below the threshold levels, the RF power amplifier circuitry control-loop parameters are unchanged.

FIG. 4 illustrates a schematic diagram of an output power detection circuit 400 according to one embodiment of the present invention. Output power detection circuit 400 comprises RF amplifier circuit 402 , detection circuit 404 , a summing network 406 , a control circuit 408 , a mirror circuit 410 , a V RAMP signal, an RF IN signal, an RF OUT signal, and a battery voltage V BATT . RF amplifier circuit 402 comprises transistors Q 1 -Q 3 , resistors R 1 -R 3 , inductors L 1 -L 3 , and capacitors C 1 -C 3 . Although RF amplifier circuit 402 is shown and described as having only these components, any number of transistors, capacitors, resistors, inductors, or other components may be used.

Detection circuit 404 comprises a capacitor C 4 , a diode D 2 , and a coupler 412 . Although detection circuit 404 is shown and described as having a single capacitor C 4 , a single diode D 2 , and a single coupler 412 , embodiments of the present invention contemplate any circuit which detects the output power of RF amplifier circuit 402 and provides an output signal corresponding to that output power. Mirror circuit 410 comprises a transistor Q 4 and a resistor R 4 . Although mirror circuit 410 is shown and described as having a single transistor Q 4 and a single resistor R 3 , embodiments of the present invention contemplate any suitable transistor or components performing the same or substantially similar function as mirror circuit 410 .

In one embodiment of the present invention, transmitter 306 of wireless device 300 of FIG. 3 comprises RF power amplifier circuitry including output power detection circuit 400 . In addition, or as an alternative, transistors Q 1 -Q 3 of RF amplifier circuit 402 are RF amplifier stages associated with the RF power amplifier circuitry of wireless device 300 . RF amplifier circuit 402 may be driven by the RF IN signal via a RF driver stage or by TX/RX circuitry 310 of wireless device 300 . In addition, RF amplifier circuit 402 may transmit the RF OUT signal into a load. In one embodiment of the present invention, the load may be an antenna and may be, for example, antenna 302 of wireless device 300 . RF amplifier circuit 402 , and in particular transistor Q 3 , may experience a load mismatch of antenna 302 of wireless device 300 .

To further explain the operation of output power detection circuit 400 , an example is now given. In the following example, transistor Q 3 experiences a load mismatch condition, such as, for example, when antenna 302 of wireless device 300 comes in close proximity with objects, for example, a hand, in the near field of antenna 302 , or the like. Although a load mismatch condition of transistor Q 3 of RF amplifier circuit 402 is described as a load mismatch generated from an antenna mismatch condition, embodiments the present invention contemplate any suitable load mismatch condition. For example, a load mismatch condition may be any load mismatch condition that causes collector current I CC to increase in transistor Q 3 of RF amplifier circuit 402 , thereby increasing the power consumption and decreasing the battery life or exceeding the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) limits of wireless device 300 .

In an embodiment of the present invention, transistor Q 4 of mirror circuit 410 , is a current mirror transistor, and is coupled in parallel with transistor Q 3 of RF amplifier circuit 402 , such that the base of transistor Q 3 is coupled with the base of transistor Q 4 and the collector of transistor Q 3 is coupled with the collector of transistor Q 4 via a resistor R 4 . Since transistor Q 4 is configured as a current mirror transistor, transistor Q 4 senses a portion of the current flowing through transistor Q 3 , such that the current flowing through transistor Q 4 is proportional to the current flowing through transistor Q 3 .

In addition, because transistor Q 4 is configured as a current mirror transistor, transistor Q 4 may be sized smaller than, for example, the size of transistor Q 3 . As an example only and not by way of limitation, transistor Q 3 may be sized to handle several amps of current flowing through transistor Q 3 , wherein transistor Q 4 may be sized to handle only a hundredth of the current flowing through transistor Q 3 . However, even though transistor Q 4 may be sized smaller than transistor Q 3 , the current flowing through transistor Q 4 is still proportional to the current flowing through transistor Q 3 .

Furthermore, because, as discussed above, transistor Q 4 is a current mirror transistor, transistor Q 4 generates a voltage V 1 , which is representative of the current flowing through transistor Q 3 . In addition, or as an alternative, the value of resistor R 4 determines the ratio between the current flowing through transistor Q 3 and the current flowing through transistor Q 4 . Thus, in accordance with the principles of embodiments of the present invention, the current flowing through transistor Q 4 generates a voltage V 1 that is proportional to collector current I CC . Transistor Q 4 provides a voltage V 1 at one input of summing network 406 .

In an embodiment of the present invention, output coupler 412 detects the output power of RF amplifier circuit 402 . The detected output power of RF amplifier circuit 402 is rectified by diode D 2 to provide a voltage V 2 at another input of summing network 406 , wherein voltage V 2 is proportional to the output power of RF amplifier circuit 402 . Voltages V 1 and V 2 are then applied to summing network 406 .

Summing voltage V S of summing network 406 has the following dependence on voltages V 1 and V 2 :

V S =α×V 2+β×max(0 ,I CC −I T )  (1)

where α and β are fixed gains and threshold current I T is a threshold value that is set during the design phase of output power detection circuit 400 . In addition, α and β provide the ability to determine how aggressively collector current I CC is limited by the threshold value of threshold current I T .

To further explain the threshold value of threshold current I T , an example is now given. In the following example, the maximum current of RF amplifier circuit 402 may require a current limit, such as, for example, 2.3 Amps. The threshold value of threshold current I T may be set to any value below the current limit, such as, for example, 2.0 Amps. Although an example maximum current and an example threshold current I T is described, embodiments of the present invention contemplate using any maximum current or any threshold value of threshold current I T .

As shown and described in equation 1, when collector current I CC is below the threshold value of threshold current I T , the control-loop parameters of output power detection circuit 400 are unchanged. For example, when collector current I CC is below the threshold value of threshold current I T , 0 is the maximum as between 0 and (I CC −I T ). Thus, multiplying β by 0 eliminates β from the calculation of summing voltage V S , and summing voltage V S is proportional to the output power of RF amplifier circuit 402 because V 2 is proportional to the output power of RF amplifier circuit 402 . In addition, when collector current I CC is equal to the threshold value of threshold current I T , the control-loop parameters of output power detection circuit 400 are also unchanged because, collector current I CC minus threshold current I T is equal to zero, (i.e., (I CC −I T =0)).

However, when collector current I CC exceeds the threshold value of threshold current I T , there is excess current, and summing voltage V S is increased by an amount proportional to the excess current. For example, summing voltage V S is the output of summing network 406 , is input into control circuit 408 and results in a reduction of bias voltage V BIAS , thereby limiting the excess current.

The form of bias voltage V BIAS dependence is:

V BIAS =G 1 ×V RAMP −G 2×max(0 ,I CC −I T )  (2)

where G 1 and G 2 are fixed gains. It is important to note, with reference to equation (2), that below the threshold value of threshold current I T , bias voltage V BIAS is proportional to the V RAMP signal, with an essentially fixed gain G 1 . However, once collector current I CC exceeds the threshold value of threshold current I T , the dependence of bias voltage V BIAS on the V RAMP signal is progressively reduced with increasing current. Among other things, the continuity in bias voltage V BIAS coupled with the ability to adjust the gain about the threshold value of threshold current I T , provides control-loop stability for output power detection circuit 400 and minimizes any spurious emissions associated with RF amplifier circuit 402 .

Although control circuit 408 is shown and described as supplying the bias voltage V BIAS of transistors Q 1 -Q 3 of RF amplifier circuit 402 , embodiments of the present invention contemplate supplying transistor Q 3 , or transistor Q 1 and/or Q 2 , or any combination of transistors. In addition, although control circuit 408 is shown and described as comparing summing voltage V S and the V RAMP signal, embodiments of the present invention contemplate any circuit which detects a difference in two voltage levels and outputs a signal corresponding to this difference.

As described above, the threshold value of threshold current I T may be set to any value below a maximum current limit using output power detection circuit 400 . However, unlike in the prior art, no abrupt discontinuity occurs in bias voltage V BIAS as a function of the V RAMP signal at the threshold value of threshold current I T . Embodiments of the present invention use the threshold value of threshold current I T to progressively reduce the increasing current associated with RF amplifier circuit 402 as bias voltage V BIAS is increased in response to the V RAMP signal. Among other things, this reduces any spurious emissions and unwanted harmonics in the frequency domain of embodiments of the present invention, which enables embodiments of the present invention to provide control-loop stability of output power detection circuit 400 .

In addition, because the maximum current of RF amplifier circuit 402 is limited under load mismatch conditions, the battery life of, for example, battery 320 , of wireless device 300 is increased relative to prior art circuits that do not limit the maximum current. Among other things, this increases the talk time associated with wireless device 300 , improves the ruggedness of RF amplifier circuit 402 , and reduces any excessive heating associated with output power detection circuit 400 .

FIG. 5 illustrates a schematic diagram of an output power detection circuit 500 according to another embodiment of the present invention. Output power detection circuit 500 comprises RF amplifier circuit 402 , detection circuit 404 , summing network 406 , control circuit 408 , RF IN signal, RF OUT signal, and a bias voltage V BIAS signal. As discussed above, although RF amplifier circuit 402 is shown in FIG. 5 and described above as having only certain components, any number of transistors, capacitors, resistors, inductors, or other components may be used. In addition, although detection circuit 404 is shown in FIG. 5 and described above as having a single capacitor C 4 , a single diode D 2 , and a single coupler 412 , embodiments of the present invention contemplate any circuit which detects the output power and provides an output signal corresponding to that output power.

Output power detection circuit 500 is similar to output power detection circuit 400 , except that rather than using current mirror circuit 410 to generate voltage V 1 , embodiments of the present invention operate in conjunction with the bias network associated with RF amplifier circuit 402 to generate voltage V 1 . As an example only, and not by way of limitation, the bias network of RF amplifier circuit 402 generates a voltage V 1 that is proportional to collector current I CC flowing through transistor Q 3 .

In one embodiment of the present invention, voltage V 1 is generated from the bias network associated with transistor Q 3 of RF amplifier circuit 402 . Although voltage V 1 is shown and described as generated from the bias network associated with transistor Q 3 , embodiments of the present invention contemplate generating voltage V 1 from the bias network associated with transistor Q 1 , transistor Q 2 , transistor Q 3 or any combination of bias networks of RF amplifier circuit 402 . In addition, as described above, voltages V 1 and V 2 are applied to summing network 406 and therefore, equation 1 is likewise valid for output power detection circuit 500 .

In addition, as described above, when collector current I CC exceeds the threshold value of threshold current I T , there is excess current, and summing voltage V S is increased by an amount proportional to the excess current. For example, summing voltage V S , which is the output of summing network 406 , is input into control circuit 408 and results in a reduction of collector voltage V CC , thereby limiting the excess current.

The form of the collector voltage V CC dependence is:

V CC =G 1 ×V RAMP −G 2×max(0 ,I CC −I T )  (3)

where G 1 and G 2 are fixed gains. It is important to note, with reference to equation (3), that below the threshold value of threshold current I T , collector voltage V CC is proportional to the V RAMP signal, with an essentially fixed gain G 1 . However, once collector current I CC exceeds the threshold value of threshold current I T , the dependence of collector voltage V CC on the V RAMP signal is progressively reduced with increasing current. Among other things, the continuity in collector voltage V CC coupled with the ability to adjust the gain about the threshold value of threshold current I T , provides control-loop stability for output power detection circuit 500 and minimizes any spurious emissions associated with RF amplifier circuit 402 .

Although control circuit 408 is shown and described as supplying the collector voltage V CC of transistors Q 1 -Q 3 of RF amplifier circuit 402 , embodiments of the present invention contemplate supplying transistor Q 3 , or transistor Q 1 and/or Q 2 , or any combination of transistors. In addition, as described above, although control circuit 408 is shown and described as comparing summing voltage V S and the V RAMP signal, embodiments of the present invention contemplate any circuit which detects a difference in two voltage levels and outputs a signal corresponding to this difference.

As described above, the threshold value of threshold current I T may be set to any value below a maximum current limit using output power detection circuit 500 . However, unlike in the prior art, no abrupt discontinuity occurs in collector voltage V CC as a function of the V RAMP signal at the threshold value of threshold current I T . Embodiments of the present invention use the threshold value of threshold current I T to progressively reduce the increasing current associated with RF amplifier circuit 402 as collector voltage V CC is increased in response to the V RAMP signal. Among other things, this reduces any spurious emissions and unwanted harmonics in the frequency domain of embodiments of the present invention, which enables embodiments of the present invention to provide control-loop stability of output power detection circuit 500 .

In one embodiment of the present invention, transmitter 306 of wireless device 300 of FIG. 3 comprises RF power amplifier circuitry including output power detection circuit 500 . As discussed above, transistors Q 1 -Q 3 of RF amplifier circuit 402 are RF amplifier stages associated with the RF power amplifier circuitry of wireless device 300 and may be driven by the RF IN signal via a RF driver stage or by TX/RX circuitry 310 of wireless device 300 . In addition, RF amplifier circuit 402 may transmit the RF OUT signal into a load, which may be an antenna and may be, for example, antenna 302 of wireless device 300 . RF amplifier circuit 402 , and in particular transistor Q 3 , may experience a load mismatch of antenna 302 of wireless device 300 .

Thus, in accordance with the principles of embodiments of the present invention, when the current increases in the bias network associated with RF amplifier circuit 402 , collector voltage V CC is adjusted to limit the maximum collector current I CC of RF amplifier circuit 402 . Among other things, this decreases the power consumption and increases the battery life of, for example, battery 320 , of wireless device 300 relative to prior art circuits that do not limit the maximum current. In addition, among other things, this increases the talk time associated with wireless device 300 , improves the ruggedness of RF amplifier circuit 402 , and reduces any excessive heating associated with output power detection circuit 500 .

Reference in the foregoing specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

While the exemplary embodiments of the present invention have been shown and described, it will be understood that various changes and modifications to the foregoing embodiments may become apparent to those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, the invention is not limited to the embodiments disclosed, but rather by the appended claims and their equivalents.