System(s), and method(s) for non-linear scaling of source pictures to a destination screen

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A common problem occurs when attempting to display 4×3 (4:3) video on a 16:9 display screen. Linear scaling of the picture results in a black bar on either side of the picture. In order to utilize the entire screen, the picture can be non-linearly scaled.

However, non-linear scaling can result in a picture that has discontinuous scaling which is noticeable at the point of the discontinuity.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application.

The present invention is directed to systems and methods for non-linear scaling of 4:3 source material to a 16:9 display as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

These and other features and advantages of the present invention may be appreciated from a review of the following detailed description of the present invention, along with the accompanying figures in which like reference numerals refer to like parts throughout.

FIG. 1 is a block diagram describing an exemplary source picture displayed on a destination screen in accordance with an embodiment of the present invention;

FIG. 2 is an exemplary graph of the step value as a function of the column in accordance with an embodiment of the present invention;

FIG. 3 is a flow diagram for mapping columns of a destination screen to a source picture in accordance with an embodiment of the present invention;

FIG. 4 is a block diagram of an exemplary scalar in accordance with an embodiment of the present invention; and

FIG. 5 is a block diagram of an exemplary decoder system in accordance with an embodiment of the present invention.

Referring now to FIG. 1 , there is illustrated a block diagram of a monitor 102 for displaying a source picture 100 on a destination screen 105 , in accordance with an embodiment of the present invention. The source picture 100 comprises a two-dimensional grid(s) of pixels, 100 ( a,b ). The destination screen 105 comprises a two-dimensional grid, 105 ( x,y ).

It is noted that the dimensions of the source picture a:b and the dimensions of the destination screen 105 , x:y are not necessarily equal. Additionally, the ratio of the dimensions, a/b and x/y may also be different. Scaling the vertical dimension of the source picture, b by a factor, y/b will fit the source picture to the height of the destination. However, scaling the horizontal dimension by the same factor does not necessarily fit the source picture 100 to the width of the destination screen 105 . Either some columns in the destination screen are unused or some columns in the source picture 100 appear outside the destination screen 105 . Scaling the horizontal dimension by a constant factor to the width of the destination screen 105 results in a distorted appearance.

To display the source picture 100 to the destination screen 105 , a circuit 107 scales the width by using a step factor that continuously varies for each of the columns. Initially, the leftmost columns 100 (0,b) of the source picture 100 and the destination source 105 (0,y) are aligned. Each successive column of the destination source 105 (1 . . . , y) is mapped to a new column value by adding the step value to the column value of the previous column.

For example, the mapped column for column 105 (5,y)=the mapped column for column 105 (4,y)+step value for column 5 . In certain embodiments of the present invention, the step value varies for each of the columns and is continuous over each of the columns 105 ( ,y).

In certain embodiments of the present invention, where a column of the destination screen is mapped to a column value that includes a fractional portion, a pixel can be interpolated from pixels in the adjacent integer columns.

It is noted that although the destination screen 105 is longer than the monitor 102 in the horizontal direction, the invention can be used where the destination screen 105 is longer than the monitor 102 in the vertical direction, as well.

Referring now to FIG. 2 , there is illustrated a graph of the step factor, s, as a function of the destination column, 105 ( ,y), in accordance with an embodiment of the present invention. The destination columns 105 ( ,y) include left columns 105 l , at least one center column 105 c , and right columns 105 r . For the center columns, the step factor is constant. However, the step factor decreases for the left columns 105 l and right columns 105 r for the columns that are farther away from the at least one center column 105 c . In certain embodiments of the present invention, the step factor s can be linear in the left columns 105 l and right columns 105 r . If the step factor s is linear in the left columns 105 l and right columns 105 r , the step factor can be incremented by delta factors +d, −d in the left columns 105 l and right columns 105 r , respectively. For example, the step factor s for column 105 (5,y) can be the step factor for column 105 (4,y)+delta factor.

It is also noted that the foregoing can also be used with destination rows. For example, in the foregoing description, the left columns can correspond to top rows, the right columns can correspond to bottom rows, and the center column can correspond to center rows. The step factor can decreases for the top rows and bottom rows for the rows that are farther away from the at least one center row.

Referring now to FIG. 3 , there is illustrated a flow diagram for mapping columns 105 ( ,y) in the destination screen to columns in the source picture 100 . At 305 , column 105 (0,y) is mapped to column 100 (0,b), and phase accumulator=0, step factor s=0, and destination screen column=0. At 310 , the delta factor d for the left region is selected.

At 315 , the column number is increased by 1, the step factor s is incremented by the delta factor d. At 320 , the phase accumulator is incremented by the step value. At 325 , the destination screen column is mapped to the phase accumulator value.

At 330 , a determination is made whether the column was the last column of the left columns by examining the column number. If at 330 , the column is not the last column of the left columns, 315 is repeated.

If at 330 , the column is the last column of the left columns, the delta factor is set to zero and the column is incremented by 1 at 332 . At 335 , the phase accumulator is incremented by the step value and the column is mapped to the phase accumulator value. At 340 , a determination is made whether the column is the last column of the center columns. If the column is not the last column of the center columns, 332 is repeated.

At 345 , the delta factor −d for the right region is selected. At 350 , the column number is increased by 1, the step factor s is incremented by the delta factor −d. At 355 , the phase accumulator is incremented by the step value. At 360 , the destination screen column is mapped to the phase accumulator value. At 365 , a determination is made whether the last column of the destination screen is reached. If the last column of the destination screen is not reached, 350 is repeated. If the last column of the destination screen is reached at 365 , the process is completed.

In certain embodiments of the present invention, the circuit 107 can include a memory storing instructions for execution by processor, wherein execution of the instructions by the processor causes the performance of the flow chart described in FIG. 3 . It is also noted that the foregoing can be implemented with vary few programmed parameters, such as the delta values d, −d, and the number of columns in the left columns, center columns, and right columns.

It is also noted that the foregoing can also be used with destination rows. For example, in the foregoing description, the left columns can correspond to top rows, the right columns can correspond to bottom rows, and the center column can correspond to center rows. The step factor can decreases for the top rows and bottom rows for the rows that are farther away from the at least one center row.

Referring now to FIG. 4 , there is illustrated a block diagram of an exemplary circuit 400 for scaling a source picture 100 to a destination screen 105 . The circuit 400 comprises a vertical scalar 405 for vertically scaling the source picture 100 ( a,b ), thereby resulting in a horizontally scaled source picture 100 ( a,y ). The horizontally scaled source picture 100 ( a,y ) is stored in memory. In certain embodiments of the present invention, off-chip memory such as DRAM store the vertically scaled source picture.

Horizontal scalar 410 includes a line buffer for storing a particular line of the horizontally scaled source picture. The horizontal scalar 410 includes a first register 415 for storing the delta value, d, 0, −d, a second register 420 for storing the step value, and a phase accumulator 425 . Adder 430 adds the delta value to the step value stored in the second register 420 . Adder 435 adds the step value to the phase accumulator 425 .

A filter receives the value from the phase accumulator 425 and generates a pixel value for the line at a particular destination screen column by interpolating from the pixels in the columns of vertically scaled source picture that are indicated by the accumulator 425 . The output of the filter is stored in another line buffer 440 for output to a display device. A processor 445 can be used to control the foregoing components. The delta values, d, −d, and number of left columns and center columns can be stored in on-chip memory such as SRAM.

In certain embodiments of the present invention, the delta values can be varied by the user. Additionally, the number of center columns can also be varied by the user.

It is also noted that the foregoing can also be used with destination rows. For example, in the foregoing description, the left columns can correspond to top rows, the right columns can correspond to bottom rows, and the center column can correspond to center rows. The step factor can decreases for the top rows and bottom rows for the rows that are farther away from the at least one center row. The modifications to the horizontal scalar would apply instead to the vertical scalar.

It is noted that the circuit 400 can be used alongside among various compression standards and in other devices such as, but not limited to set top boxes and DVD players. Referring now to FIG. 5 , there is illustrated a block diagram of an exemplary decoder in accordance with an embodiment of the present invention.

Data is output from buffer 532 within SDRAM 530 . The data output from the buffer 532 is then passed to a data transport processor 535 . The data transport processor 535 demultiplexes the transport stream into packetized elementary stream constituents, and passes the audio transport stream to an audio decoder 560 and the video transport stream to a video transport decoder 540 and then to a MPEG video decoder 545 . The audio data is then sent to the output blocks, and the video is sent to a display engine 550 . The display engine 550 scales the video picture, renders the graphics, and constructs the complete display. Once the display is ready to be presented, it is passed to a video encoder 555 where it is converted to analog video using an internal digital to analog converter (DAC). The digital audio is converted to analog in an audio digital to analog (DAC) 565 . In certain embodiments of the present invention, the circuit 400 can form a portion of the display engine 550 .

The systems as described herein may be implemented as a board level product, as a single chip, application specific integrated circuit (ASIC), or with varying levels of the systems integrated with other portions of the system as separate components. The degree of integration of the decoder system will primarily be determined by the speed and cost considerations.

Because of the sophisticated nature of modern processors, it is possible to utilize a commercially available processor, which may be implemented external to an ASIC implementation. Alternatively, if the processor is available as an ASIC core or logic block, then the commercially available processor can be implemented as part of an ASIC device wherein various operations are implemented in firmware.

While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention.

In addition, many modifications may be made to adapt particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.