Embedded type multifunctional integrated structure for integrating protection components and method for manufacturing the same

1. Field of the Invention

The present invention relates to a multifunctional integrated structure and a method for manufacturing the same, and particularly relates to an embedded type multifunctional integrated structure for integrating protection components and a method for manufacturing the same.

2. Description of the Related Art

Future electronic products have the requirement of being light, thin, short, and small. Moreover, the size of passive electronic components in those products is becoming larger than that of the other components. Hence, if the passive components can be effectively integrated, the electronic product can achieve the quality of being light, thin, short and small.

However, each passive component only has a single function in the prior design. Hence, when a designer needs to use many different functions for protecting the electronic product, the designer only can place many passive components with a single function in the electronic product. Therefore, the method of the prior art wastes cost and occupies much space in the electronic product.

One particular aspect of the present invention is to provide an embedded type multifunctional integrated structure for integrating protection components and a method for manufacturing the same. The present invention utilizes the concept of multi-layer design to integrate more than two passive components on a component structure that is adhered onto a substrate and is applied to a USB terminal in order to protect an electronic device that uses the USB.

In order to achieve the above-mentioned aspects, the present invention provides an embedded type multifunctional integrated structure for integrating protection components that includes: a top cover insulating layer, an over-current protection layer, a middle insulating layer, a multifunctional protection layer, and a bottom cover insulating layer. The top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer are stacked together in sequence, and the multifunctional protection layer has a first functional unit and a second functional unit. Therefore, abnormal currents are transmitted to a grounding side through the over-current protection layer and the first functional unit of the multifunctional protection layer, and abnormal signals are transmitted to the grounding side through the second functional unit of the multifunctional protection layer.

In order to achieve the above-mentioned aspects, the present invention provides an embedded type multifunctional integrated structure for integrating protection components that includes: a top cover insulating layer, an over-current protection layer, a middle insulating layer, a multifunctional protection layer, and a bottom cover insulating layer.

The top cover insulating layer has a first power input portion and two first signal input portions. The over-current protection layer is disposed under the top cover insulating layer, and the over-current protection layer has a second power input portion and a first power output portion. The middle insulating layer is disposed under the over-current protection layer. The multifunctional protection layer is disposed under the middle insulating layer. The multifunctional protection layer has a third power input portion, a first grounding portion, a first functional unit electrically connected between the third power input portion and the first grounding portion, two second signal input portions, and a second functional unit electrically connected between each second signal input portion and the first grounding portion;

The bottom cover insulating layer is disposed under the multifunctional protection layer, and the bottom cover insulating layer has a second power output portion, a second grounding portion, and two first signal output portions. The lateral conductive unit has a first lateral conductive layer, a second lateral conductive layer, a third lateral conductive layer, a fourth lateral conductive layer, and a fifth lateral conductive layer insulated from each other. Each lateral conductive layer from top to bottom is formed on lateral sides of the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer in sequence. Moreover, the first power input portion and the second power input portion are electrically connected with each other via the first lateral conductive layer; the first power output portion, the third power input portion and the second power output portion are electrically connected with each other via the second lateral conductive layer; one of the first signal input portions, one of the two second signal input portions, and one of the first signal output portions are connected with each other via the third lateral conductive layer; the other first signal input portion, the other second signal input portion, and the other first signal output portion are connected with each other via the fourth lateral conductive layer; the first grounding portion and the second grounding portion are connected with each other via the fifth lateral conductive layer.

In order to achieve the above-mentioned aspects, the present invention provides a method for manufacturing an embedded type multifunctional integrated structure for integrating protection components, includes: providing a top cover insulating layer having a first power input portion and two first signal input portions; providing an over-current protection layer disposed under the top cover insulating layer, and the over-current protection layer having a second power input portion and a first power output portion; providing a middle insulating layer disposed under the over-current protection layer; and then providing a multifunctional protection layer disposed under the middle insulating layer, and the multifunctional protection layer having a third power input portion, a first grounding portion, a first functional unit electrically connected between the third power input portion and the first grounding portion, two second signal input portions, and a second functional unit electrically connected between each second signal input portion and the first grounding portion.

The method further includes: providing a bottom cover insulating layer disposed under the multifunctional protection layer, and the bottom cover insulating layer having a second power output portion, a second grounding portion, and two first signal output portions; making the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer stacked together in sequence; and then forming a first lateral conductive layer, a second lateral conductive layer, a third lateral conductive layer, a fourth lateral conductive layer, and a fifth lateral conductive layer insulated from each other, and each lateral conductive layer from top to bottom being formed on lateral sides of the top cover insulating layer, the over-current protection layer, the middle insulating layer, the multifunctional protection layer, and the bottom cover insulating layer in sequence.

Hence, the embedded type multifunctional integrated structure has an OCP (Over-Current Protection) function, an OVP (Over-Voltage Protection) function, and an anti-ESD (Anti-Electrostatic Discharge) function at the same time. Therefore, the present invention effectively integrates two or more than one passive components in order to increase functionality. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. Other advantages and features of the invention will be apparent from the following description, drawings and claims.

The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:

FIG. 1A is a perspective, exploded view of an embedded type multifunctional integrated structure for integrating protection components according to the first embodiment of the present invention;

FIG. 1B is a reversed, perspective view of an over-current protection layer according to the first embodiment of the present invention;

FIG. 1C is a perspective, assembled view of an embedded type multifunctional integrated structure for integrating protection components according to the first embodiment of the present invention;

FIG. 2A is a perspective view of an over-current protection layer according to the second embodiment of the present invention;

FIG. 2B is a reversed, perspective view of an over-current protection layer according to the second embodiment of the present invention;

FIG. 3A is a perspective view of a multifunctional protection layer according to the third embodiment of the present invention;

FIG. 3B is a reversed, perspective view of a bottom cover insulating layer according to the third embodiment of the present invention;

FIG. 4 is a perspective view of a multifunctional protection layer according to the fourth embodiment of the present invention;

FIG. 5 is a flowchart of a method for manufacturing an embedded type multifunctional integrated structure for integrating protection components according to the present; and

FIG. 6 is a perspective view of a stacked structure with five layers according to the present invention (before many embedded type multifunctional integrated structure are cut from the stacked structure).

Referring to FIGS. 1A to 1C , FIG. 1A shows a perspective, exploded view of an embedded type multifunctional integrated structure for integrating protection components according to the first embodiment of the present invention; FIG. 1B shows a reversed, perspective view of an over-current protection layer according to the first embodiment of the present invention; FIG. 1C shows a perspective, assembled view of an embedded type multifunctional integrated structure for integrating protection components according to the first embodiment of the present.

Referring to above-mentioned figures, the first embodiment of the present invention provides an embedded type multifunctional integrated structure for integrating protection components that includes a top cover insulating layer 1 , an over-current protection layer 2 , a middle insulating layer M, a multifunctional protection layer 3 , a bottom cover insulating layer 4 , and a lateral conductive unit 5 . Moreover, the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 are stacked together in sequence. The lateral conductive unit 5 has a first lateral conductive layer 51 , a second lateral conductive layer 52 , a third lateral conductive layer 53 , a fourth lateral conductive layer 54 , and a fifth lateral conductive layer 55 insulated from each other.

In addition, the top cover insulating layer 1 has a first half hole 10 a , a second half hole 10 b , a third half hole 10 c , a fourth half hole 10 d , and a fifth half hole 10 e distributively formed on four lateral sides thereof. Furthermore, the top cover insulating layer 1 has a first power input portion 10 P electrically connected with the first lateral conductive layer 51 , and two first signal input portions ( 10 S 1 , 10 S 2 ) respectively and electrically connected with the third and the fourth lateral conductive layers ( 53 , 54 ). Moreover, the first power input portion 10 P and the two first signal input-portions ( 10 S 1 , 10 S 2 ) are formed on a top surface of the top cover insulating layer 1 .

Furthermore, the over-current protection layer 2 is disposed under the top cover insulating layer 1 . The over-current protection layer 2 has a first half hole 20 a , a second half hole 20 b , a third half hole 20 c , a fourth half hole 20 d , and a fifth half hole 20 e distributively formed on four lateral sides thereof. In addition, the over-current protection layer 2 is composed of a first electrode layer 2 A, a second electrode layer 2 B, and a positive temperature coefficient material layer 2 C that is disposed between the first electrode layer 2 A and the second electrode layer 2 B. The positive temperature coefficient material layer 2 C can be a PPTC (Polymer Positive Temperature Coefficient) material layer, a resistance material layer, a capacitance material layer, or an inductance material layer.

In addition, the over-current protection layer 2 has a second power input portion 20 P electrically connected with the first lateral conductive layer 51 and a first power output portion 21 P (as shown in FIG. 1B ) electrically connected with the second lateral conductive layer 52 .

The second power input portion 20 P is one side of the first electrode layer 2 A, and the first power output portion 21 P is one side of the second electrode layer 2 B. The first electrode layer 2 A has a first insulating portion L 1 insulated from the second, third, fourth and fifth lateral conductive layers ( 52 , 53 , 54 , 55 ), and the second electrode layer 2 B has a second insulating portion L 2 (as shown in FIG. 2 ) insulated from the first, third, fourth and fifth lateral conductive layers ( 51 , 53 , 54 , 55 ). Hence, the first electrode layer 2 A is insulated from the second, third, fourth and fifth lateral conductive layers ( 52 , 53 , 54 , 55 ) via the first insulating portion L 1 , and the second electrode layer 2 B is insulated from the first, third, fourth and fifth lateral conductive layers ( 51 , 53 , 54 , 55 ) via the second insulating portion L 2 .

Moreover, the middle insulating layer M is disposed under the over-current protection layer 2 . The middle insulating layer M has an opening unit M 10 that includes a first opening M 100 and a second opening M 110 . In addition, the middle insulating layer M has a first half hole Ma, a second half hole Mb, a third half hole Mc, a fourth half hole Md, and a fifth half hole Me distributively formed on four lateral sides thereof.

Furthermore, the multifunctional protection layer 3 is disposed under the middle insulating layer M. The multifunctional protection layer 3 has a first half hole 30 a , a second half hole 30 b , a third half hole 30 c , a fourth half hole 30 d , and a fifth half hole 30 e distributively formed on four lateral sides thereof.

In addition, the multifunctional protection layer 3 has a third power input portion 30 P electrically connected with the second lateral conductive layer 52 , a first grounding portion 30 G electrically connected with the fifth lateral conductive layer 55 , a first functional unit C 1 electrically connected between the third power input portion 30 P and the first grounding portion 30 G, two second signal input portions ( 30 S 1 , 30 S 2 ) respectively and electrically connected with the third lateral conductive layer 53 and the fourth lateral conductive layer 54 , and a second functional unit C 2 electrically connected between each second signal input portion ( 30 S 1 or 30 S 2 ) and the first grounding portion 30 G.

Moreover, in the first embodiment, the first functional unit C 1 , the second functional unit C 2 , the third power input portion 30 P, the first grounding portion 30 G, and the two second signal input portions ( 30 S 1 , 30 S 2 ) are formed on a top surface of the multifunctional protection layer 3 . The first functional unit C 1 is a functional chip such as an OVP (Over-Voltage Protection) chip, and the second functional unit C 2 is a groove that has a width between 10 μm and 100 μm and a depth between 10 μm and 500 μm. In addition, the first opening M 100 is used to receive the first functional unit C 1 such as the functional chip and the second opening M 110 is used to expose one part of the second functional unit C 2 such as one part of the groove.

Moreover, the bottom cover insulating layer 4 is disposed under the multifunctional protection layer 3 . The bottom cover insulating layer 4 has a first half hole 40 a , a second half hole 40 b , a third half hole 40 c , a fourth half hole 40 d , and a fifth half hole 40 e distributively formed on four lateral sides thereof. In addition, the bottom cover insulating layer 4 has a second power output portion 40 P electrically connected with the second lateral conductive layer 52 , a second grounding portion 40 G electrically connected with the fifth lateral conductive layer 55 , and two first signal output portions ( 40 S 1 , 40 S 2 ) respectively and electrically connected with the third lateral conductive layer 53 and the fourth lateral conductive layer 55 . The second power output portion 40 P, the second grounding portion 40 G and the first signal output portions ( 40 S 1 , 40 S 2 ) are formed on a bottom surface of the bottom cover insulating layer 4 .

In addition, referring to FIG. 1C , each lateral conductive layer ( 51 , 52 , 53 , 54 or 55 ) from top to bottom is formed on lateral sides of the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 in sequence.

Furthermore, the first half hole 10 a of the top cover insulating layer 1 , the first half hole 20 a of the over-current protection layer 2 , the first half hole Ma of the middle insulating layer M, the first half hole 30 a of the multifunctional protection layer 3 , and the first half hole 40 a of the bottom cover insulating layer 4 are stacked together to form a first lateral through groove 61 . The second half hole 10 b of the top cover insulating layer 1 , the second half hole 20 b of the over-current protection layer 2 , the second half hole Mb of the middle insulating layer M, the second half hole 30 b of the multifunctional protection layer 3 , and the second half hole 40 b of the bottom cover insulating layer 4 are stacked together to form a second lateral through groove 62 . The third half hole 10 c of the top cover insulating layer 1 , the third half hole 20 c of the over-current protection layer 2 , the third half hole Mc of the middle insulating layer M, the third half hole 30 c of the multifunctional protection layer 3 , and the third half hole 40 c of the bottom cover insulating layer 4 are stacked together to form a third lateral through groove 63 . The fourth half hole 10 d of the top cover insulating layer 1 , the fourth half hole 20 d of the over-current protection layer 2 , the fourth half hole Md of the middle insulating layer M, the fourth half hole 30 d of the multifunctional protection layer 3 , and the fourth half hole 40 d of the bottom cover insulating layer 4 are stacked together to form a fourth lateral through groove 64 . The fifth half hole 10 e of the top cover insulating layer 1 , the fifth half hole 20 e of the over-current protection layer 2 , the fifth half hole Me of the middle insulating layer M, the fifth half hole 30 e of the multifunctional protection layer 3 , and the fifth half hole 40 e of the bottom cover insulating layer 4 are stacked together to form a fifth lateral through groove 65 .

Therefore, the first lateral through groove 61 is composed of the first half holes ( 10 a , 20 a , Ma, 30 a , 40 a ) that are respectively formed on the same sides of the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 . The second lateral through groove 62 is composed of the second half holes ( 10 b , 20 b , Mb, 30 b , 40 b ) that are respectively formed on the same sides of the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 . The third lateral through groove 63 is composed of the third half holes ( 10 c , 20 c , Mc, 30 c , 40 c ) that are respectively formed on the same sides of the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 . The fourth lateral through groove 64 is composed of the fourth half holes ( 10 d , 20 d , Md, 30 d , 40 d ) that are respectively formed on the same sides of the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 . The fifth lateral through groove 65 is composed of the fifth half holes ( 10 e , 20 e , Me, 30 e , 40 e ) that are respectively formed on the same sides of the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 .

Moreover, the first lateral through groove 61 , the second lateral through groove 62 , the third lateral through groove 63 , the fourth lateral through groove 64 , and the fifth lateral through groove 65 separated from each other are combined to formed a lateral through groove unit 6 . In addition, the first lateral conductive layer 51 is formed on an inner surface of the first lateral through groove 61 , the second lateral conductive layer 52 is formed on an inner surface of the second lateral through groove 62 , the third lateral conductive layer 53 is formed on an inner surface of the third lateral through groove 63 , the fourth lateral conductive layer 54 is formed on an inner surface of the fourth lateral through groove 64 , and the fifth lateral conductive layer 55 is formed on an inner surface of the fifth lateral through groove 65 .

Hence, the first power input portion 10 P and the second power input portion 20 P are electrically connected with each other via the first lateral conductive layer 51 . The first power output portion 21 P, the third power input portion 30 P and the second power output portion 40 P are electrically connected with each other via the second lateral conductive layer 52 . One first signal input portion 10 S 1 , one second signal input portion 30 S 1 , and one first signal output portion 40 S 1 are connected with each other via the third lateral conductive layer 53 . The other first signal input portion 10 S 2 , the other second signal input portion 30 S 2 , and the other first signal output portion 40 S 2 are connected with each other via the fourth lateral conductive layer 54 . The first grounding portion 30 G and the second grounding portion 40 G are connected with each other via the fifth lateral conductive layer 55 .

Referring to FIGS. 1A to 1C , the arrows mean the directions of current I 1 and signals (S 1 , S 2 ) in the above-mentioned figures. The main path of the current I 1 in each layer from the top cover insulating layer 1 to the bottom cover insulating layer 4 is shown as follows:

First layer (the top cover insulating layer 1 ): The current I 1 flows from the first power input portion 10 P of the top cover insulating layer 1 to the second power input portion 20 P via the first lateral conductive layer 51 .

Second layer (the over-current protection layer 2 ): The current I 1 flows through the first electrode layer 2 A, the positive temperature coefficient material layer 2 C, and the second electrode layer 2 B in sequence and flows from the second power input portion 20 P to the first power output portion 21 P. Hence, the present invention has the function of OCP (Over-Current Protection) due to the material property of the positive temperature coefficient material layer 2 C.

Third layer (the middle insulating layer M): The current I 1 flows from the first power output portion 21 P to the third power input portion 30 P of the multifunctional protection layer 3 via the second lateral conductive layer 52 .

Fourth layer (the multifunctional protection layer 3 ): The flowing direction of the current I 1 is determined according to the setting of the first functional unit C 1 . Hence, the normal current I 1 flows to next layer directly. The abnormal current I G flows from the third power input portion 30 P to the first grounding portion 30 G through the first functional unit C 1 . For example, the first functional unit C 1 is an OVP (Over-Voltage Protection) chip and the voltage load of the OVP chip is 5 volt. Hence, when the current is smaller than 5 volt, the current is outputted normally; when the current is larger than 5 volt, the current is transmitted to the grounding side through the OVP chip.

Fifth layer (the bottom cover insulating layer 4 ): The normal current I 1 flows to the second power output portion 40 P of the bottom cover insulating layer 4 via the second lateral conductive layer 52 . The abnormal current I G flows from the first grounding portion 30 G to the second grounding portion 40 G of the bottom cover insulating layer 4 and is transmitted to the grounding side via the fifth lateral conductive layer 55 .

The main path of two signals (S 1 , S 2 ) in each layer from the top cover insulating layer 1 to the bottom cover insulating layer 4 is shown as follows:

First layer (the top cover insulating layer 1 ): The two signals (S 1 , S 2 ) flow from the two first signal input portions ( 10 S 1 , 10 S 2 ) of the top cover insulating layer 1 to the two second signal input portions ( 30 S 1 , 30 S 2 ) of the multifunctional protection layer 3 via the third lateral conductive layer 53 and the fourth lateral conductive layer 54 , respectively.

Fourth layer (the multifunctional protection layer 3 ): The flowing directions of the two signals (S 1 , S 2 ) are determined according to the setting of the second functional unit C 2 . Hence, the two normal signals (S 1 , S 2 ) flow to next layer directly. The abnormal signal S G flows from the two second signal input portions ( 30 S 1 , 30 S 2 ) to the first grounding portion 30 G through the second functional unit C 2 .

Fifth layer (the bottom cover insulating layer 4 ): The two normal signals (S 1 , S 2 ) flow to the first signal output portions ( 40 S 1 , 40 S 2 ) of the bottom cover insulating layer 4 via the third lateral conductive layer 53 and the fourth lateral conductive layer 54 , respectively. The abnormal signal S G flows from the first grounding portion 30 G to the second grounding portion 40 G of the bottom cover insulating layer 4 and is transmitted to the grounding side via the fifth lateral conductive layer 55 .

Referring to FIGS. 2A and 2B , FIG. 2A shows a perspective view of an over-current protection layer according to the second embodiment of the present invention; FIG. 2B shows a reversed, perspective view of an over-current protection layer according to the second embodiment of the present. The difference between the second embodiment and the first embodiment is that: in the second embodiment, the second power input portion 20 P′ is one side of the second electrode layer 2 B′, the first power output portion 21 P′ is one side of the first electrode layer 2 A′, the first electrode layer 2 A′ has a first insulating portion L 1 ′ (as shown in FIG. 2A ) insulated from the first, third, fourth and fifth lateral conductive layers ( 51 , 53 , 54 , 55 ), and the second electrode layer 2 B′ has a second insulating portion L 2 ′ (as shown in FIG. 2B ) insulated from the second, third, fourth and fifth lateral conductive layers ( 52 , 53 , 54 , 55 ). Hence, the first electrode layer 2 A′ is insulated from the first, third, fourth and fifth lateral conductive layers ( 51 , 53 , 54 , 55 ) via the first insulating portion L 1 ′, and the second electrode layer 2 B′ is insulated from the second, third, fourth and fifth lateral conductive layers ( 52 , 53 , 54 , 55 ) via the second insulating portion L 2 ′.

Therefore, a current path of a second layer (the over-current protection layer 2 ′) of the second embodiment is that the current I 2 flows through the second electrode layer 2 B′, the positive temperature coefficient material layer 2 C′, and the first electrode layer 2 A′ in sequence and flows from the second power input portion 20 P′ to the first power output portion 21 P′.

Referring to FIGS. 3A and 3B , FIG. 3A shows a perspective view of a multifunctional protection layer according to the third embodiment of the present invention; FIG. 3B shows a reversed, perspective view of a bottom cover insulating layer according to the third embodiment of the present. The difference between the third embodiment and the first embodiment is that: in the third embodiment, the first functional unit C 1 ′, the second functional unit C 2 ′, the third power input portion 30 P′, the first grounding portion 30 G′, and the two second signal input portions ( 30 S 1 ′, 30 S 2 ′) are formed on a bottom surface of the multifunctional protection layer 3 ′, and the bottom cover insulating layer 4 ′ has an opening unit 41 ′. The opening unit 41 ′ has a first opening 410 ′ and a second opening 411 ′. The first opening 410 ′ is used to receive the first functional unit C 1 ′ such as a functional chip and the second opening 411 ′ is used to expose one part of the second functional unit C 2 ′ such as one part of a groove.

Furthermore, the present invention can combine the first embodiment and the third embodiment, so the first functional unit C 1 , the second functional unit C 2 , the third power input portion 30 P, the first grounding portion 30 G, and the two second signal input portions ( 30 S 1 , 30 S 2 ) are formed on the top surface of the multifunctional protection layer 3 (as shown in the first embodiment of FIG. 1A ), and the first functional unit C 1 ′, the second functional unit C 2 ′, the third power input portion 30 P′, the first grounding portion 30 G′, and the two second signal input portions ( 30 S 1 ′, 30 S 2 ′) are formed on the bottom surface of the multifunctional protection layer 3 ′ (as shown in the third embodiment of FIG. 3A ).

FIG. 4 shows a perspective view of a multifunctional protection layer according to the fourth embodiment of the present. The difference between the fourth embodiment and the first embodiment is that: in the fourth embodiment, the second functional unit C 2 ″ is two functional chips C 20 ″ such as two anti-ESD (anti-Electrostatic Discharge) chips, and a second opening (not shown) is used to receive the two functional chips.

FIG. 5 shows a flowchart of a method for manufacturing an embedded type multifunctional integrated structure for integrating protection components according to the present. The method for manufacturing the embedded type multifunctional integrated structure for integrating protection components includes:

Step S 100 is providing a top cover insulating layer 1 having a first power input portion 10 P and two first signal input portions ( 10 S 1 , 10 S 2 ).

Step S 102 is providing an over-current protection layer 2 disposed under the top cover insulating layer 1 , and the over-current protection layer 2 having a second power input portion 20 P and a first power output portion 21 P.

Step S 104 is providing a middle insulating layer M disposed under the over-current protection layer 2 .

Step S 106 is providing a multifunctional protection layer 3 disposed under the middle insulating layer M, and the multifunctional protection layer 3 having a third power input portion 30 P, a first grounding portion 30 G, a first functional unit C 1 electrically connected between the third power input portion 30 P and the first grounding portion 30 G, two second signal input portions ( 30 S 1 , 30 S 2 ), and a second functional unit C 2 electrically connected between each second signal input portion ( 30 S 1 , 30 S 2 ) and the first grounding portion 30 G.

Step S 108 is providing a bottom cover insulating layer 4 disposed under the multifunctional protection layer 3 , and the bottom cover insulating layer 4 having a second power output portion 40 P, a second grounding portion 40 G, and two first signal output portions ( 40 S 1 , 40 S 2 ).

Step S 110 is making the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 stacked together in sequence.

Step S 112 is forming a first lateral conductive layer 51 , a second lateral conductive layer 52 , a third lateral conductive layer 53 , a fourth lateral conductive layer 54 , and a fifth lateral conductive layer 55 insulated from each other, and each lateral conductive layer ( 51 , 52 , 53 , 54 , 55 ) from top to bottom formed on lateral sides of the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 in sequence.

Therefore, the first power input portion 10 P and the second power input portion 20 P are electrically connected with each other via the first lateral conductive layer 51 . The first power output portion 21 P, the third power input portion 30 P and the second power output portion 40 P are electrically connected with each other via the second lateral conductive layer 52 . One first signal input portion 10 S 1 , one second signal input portion 30 S 1 , and one first signal output portion 40 S 1 , are connected with each other via the third lateral conductive layer 53 . The other first signal input portion 10 S 2 , the other second signal input portion 30 S 2 , and the other first signal output portion 40 S 2 are connected with each other via the fourth lateral conductive layer 54 . The first grounding portion 30 G and the second grounding portion 40 G are connected with each other via the fifth lateral conductive layer 55 .

Moreover, before the step S 112 of forming the lateral conductive layers, the method further comprises: forming a first lateral through groove 61 , a second lateral through groove 62 , a third lateral through groove 63 , a fourth lateral through groove 64 , and a fifth lateral through groove 65 separated from each other. Each lateral through groove ( 61 , 62 , 63 , 64 , 65 ) is formed via drilling or punching the top cover insulating layer 1 , the over-current protection layer 2 , the middle insulating layer M, the multifunctional protection layer 3 , and the bottom cover insulating layer 4 in sequence. In addition, the first lateral conductive layer 51 is formed on an inner surface of the first lateral through groove 61 , the second lateral conductive layer 52 is formed on an inner surface of the second lateral through groove 62 , the third lateral conductive layer 53 is formed on an inner surface of the third lateral through groove 63 , the fourth lateral conductive layer 54 is formed on an inner surface of the fourth lateral through groove 64 , and the fifth lateral conductive layer 55 is formed on an inner surface of the fifth lateral through groove 65 .

FIG. 6 shows a perspective view of a stacked structure with five layers according to the present invention (before many embedded type multifunctional integrated structure for integrating protection components are cut from the stacked structure). Each top cover insulating layer 1 ″, each over-current protection layer 2 ″, each middle insulating layer M″, each multifunctional protection layer 3 ″, and each bottom cover insulating layer 4 ″ are drilled or punched in sequence to form a plurality of through holes H. Many conductive layers from top to bottom are respectively coated on inner surfaces of the through holes H of each top cover insulating layer 1 ″, each over-current protection layer 2 ″, each middle insulating layer M″, each multifunctional protection layer 3 ″, and each bottom cover insulating layer 4 ″. Finally, each embedded type multifunctional integrated structure P (as shown in FIG. 1C ) is cut from the stacked structure. Hence, the present invention can manufacture many embedded type multifunctional integrated structure P at the same time.

In conclusion, the present invention utilizes the concept of multi-layer design to integrate more than two passive components on a component structure that is adhered onto a substrate and is applied to a USB terminal in order to protect an electronic device that uses the USB. Hence, the present invention has an OCP function, an OVP function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrates two or more passive components in order to increase functionality. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.

Although the present invention has been described with reference to the preferred best molds thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.