Hard reset and manual reset circuit assembly

1. Field of the Invention

The present invention relates to a reset circuit and more particularly to a hard reset and manual reset circuit assembly.

2. Description of the Related Art

In a computer system, reset is an important function. In case of system hang up or execution error, reset the system can cause the system to boost again, returning to the normal operation status.

U.S. Pat. No. 5,935,254 discloses a reset circuit entitled “Computer system for cutting off power by key input signals or programming and having a reset switch for resetting and supplying power”. This design is capable of providing a signal to cause the system to reset. However, the circuit architecture of this design is complicated. Further, the manufacturing cost of this design is high because it uses a switching mode power supply (SMPS) for providing an operating power and a stand-by voltage to the main computer block, a power-on signal generator for generating a power-on signal to the SMPS.

Further, conventional reset devices do not consider the problem of delay. To certain electronic apparatus, starting all devices simultaneously may cause the problem that some devices start working and some other devices are not ready. In this case, an incorrect signal may exist or be produced, resulting in an accident.

The present invention has been accomplished under the circumstances in view. It is the main object of the present invention to provide a hard reset and manual reset circuit assembly, which has a simple and low-cost circuit structure, and provides effective reset function.

It is another object of the present invention to provide a hard reset and manual reset circuit assembly, which provides a delay on reset so that the matched external device has sufficient time to enter a ready status.

To achieve these and other objects of the present invention, the hard reset and manual reset circuit assembly comprises a power source; a first resistor, the first resistor having two opposite ends thereof respectively connected to the power source and a reset terminal; a first electric control switch, the first electric control switch comprising a control end and two bypasses, the two bypasses of the first electric control switch being respectively connected to the reset terminal and a grounding terminal; a second resistor, the second resistor having two opposite ends respectively connected to the power source and the control end of the first electric control switch; a second electric control switch, the second electric control switch comprising a control end and two bypasses, the two bypasses of the second electric control switch being respectively connected to the control end of the first electric control switch and the grounding terminal; a third resistor, the third resistor comprising two opposite ends respectively connected to the power source and the control end of the second electric control switch; a first capacitor, the first capacitor comprising two opposite ends respectively connected to the control end of the second electric control switch and the grounding terminal; a second capacitor, the second capacitor comprising a first end and a second end, the first end of the second capacitor being connected to the control end of the second electric control switch; a manual switch, the manual switch comprising two opposite ends respectively connected to the second end of the second capacitor and the grounding terminal; and a fourth resistor, the fourth resistor comprising two opposite ends respectively connected to the power source and the second end of the second capacitor. By means of the aforesaid arrangement, the hard reset and manual reset circuit assembly provides a delay time during reset, for enabling other matched electronic devices to have sufficient time to reach ready status.

FIG. 1 is a circuit diagram of a hard reset and manual reset circuit assembly in accordance with the present invention.

Referring to FIG. 1 a hard reset and manual reset circuit assembly 10 in accordance with the present invention is shown comprised of a power source Vin, a first resistor R 1 , a first electric control switch Q 1 , a second resistor R 2 , a second electric control switch Q 2 , a third resistor R 3 , a first capacitor C 1 , a second capacitor C 2 , a manual switch SW, and a fourth resistor R 4 .

The first resistor R 1 has its two opposite ends respectively connected to the power source Vin and a reset terminal RST.

The first electric control switch Q 1 is a semiconductor switch, for example, N-channel MOSFET (N-channel metal-oxide semiconductor field-effect transistor), having a control end (the gate G) and two bypasses (the drain D and the source S). The two bypasses (the drain D and the source S) are respectively connected to the reset terminal RST and a grounding terminal GND.

The second resistor R 2 has its two opposite ends respectively connected to power source Vin and the control end (the gate G) of the first electric control switch Q 1 .

The second electric control switch Q 2 is a semiconductor switch, for example, N-channel MOSFET (N-channel metal-oxide semiconductor field-effect transistor), having a control end (the gate G) and two bypasses (the drain D and the source S). The two bypasses (the drain D and the source S) of the second electric control switch Q 2 are respectively connected to the control end (the gate G) of the first electric control switch Q 1 and the aforesaid grounding terminal GND.

The third resistor R 3 has its two opposite ends respectively connected to the aforesaid power source Vin and the control end (the gate G) of the second electric control switch Q 2 .

The first capacitor C 1 has its two opposite ends respectively connected to the control end (the gate G) of the second electric control switch Q 2 and the aforesaid grounding terminal GND.

The second capacitor C 2 has a first end N 1 and a second end N 2 . The first end N 1 is connected to the control end (the gate G) of the second electric control switch Q 2 .

The manual switch SW has its two opposite ends respectively connected to the second end N 2 of the second capacitor C 2 and the aforesaid grounding terminal GND.

The fourth resistor R 4 has its two opposite ends respectively connected to the aforesaid power source Vin and the second end N 2 of the second capacitor C 2 .

The working status of the present invention is described hereinafter:

1. When the manual switch SW is off and the power source Vin is on, the power source Vin charges the first capacitor C 1 through the third resistor R 3 . At this time, the control end of the first electric control switch Q 1 is at high potential, and therefore the first electric control switch Q 1 is switched on, and the reset terminal RST is at a low-potential activation status. When the first capacitor C 1 is charged to high potential, the control end of the second electric control switch Q 2 becomes high, and therefore the second electric control switch Q 2 is switched on. At this time, the control end of the first electric control switch Q 1 is at low potential, and therefore the first electric control switch Q 1 is switched off, and the reset terminal RST is turned to a high-potential off status. This operation status explains that when the power source starts to supply power as the system is turned on, the reset terminal will be changed from the low-potential activation status to the high-potential off status after the period of the charging time of the first capacitor, so that the connected external devices will have sufficient time to reach the ready status.

2. When the power source Vin is on and the manual switch SW is switched on, the power source Vin charges the second capacitor C 2 through the third resistor R 3 . At this time, the control end of the first electric control switch Q 1 is at high potential, and therefore the first electric control switch Q 1 is switched on, and the reset terminal RST is at a low-potential activation status. When the second capacitor C 2 is charged to high potential, the control end of the second electric control switch Q 2 becomes high, and therefore the second electric control switch Q 2 is switched on. At this time, the control end of the first electric control switch Q 1 is at low potential, and therefore the first electric control switch Q 1 is switched off, and the reset terminal RST is turned to a high-potential off status. This operation status explains the manual switch executes the reset operation.

The aforesaid working status includes the delay reset operation of the power source Vin with the third resistor R 3 and the first capacitor C 1 and the delay reset operation of the manual switch SW with the power source Vin and the third resistor R 3 and the second capacitor C 2 . As illustrated in FIG. 1 , the first capacitor C 1 and the second capacitor C 2 both are installed in the circuit of the present invention, achieving hard reset function as well as manual reset functions.

As stated above, either the manual switch SW is on or off during supply of the power source Vin, the working status of the present invention causes the reset terminal RST to reset the system. During the resetting process, a delay time is provided subject to the charging time of the first capacitor C 1 or second capacitor C 2 , and therefore the connected external devices have sufficient time to reach the ready status. Further, the component parts used in the hard reset and manual reset circuit assembly of the present invention are cheap, and the circuit design of the present invention is simple, therefore the manufacturing cost of the hard reset and manual reset circuit assembly of the present invention is low.

Although a particular embodiment of the invention has been described in detail for purposes of illustration, various modifications and enhancements may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.