Semiconductor memory device including a write recovery time control circuit

This application claims priority under 35 USC § 119 to Korean Patent Application No. 2006-116743 filed on Nov. 24, 2006 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.

1. Field

The example embodiments relate to a semiconductor memory device, and more particularly to a semiconductor memory device including a write recovery time control circuit and a method of controlling a write recovery time of the semiconductor memory device.

2. Description

A synchronous semiconductor memory device may input and output data in synchronization with an external clock. Due to an increased operation speed of a Dynamic Random Access Memory (DRAM), a word line (WL) may be disabled by a pre-charge command before data is sufficiently written into a memory cell in response to a write command. A column selecting line (CSL) enable signal and a pre-charge command may be generated after a write command is generated, and the time period between the generation of the CSL enable signal. The generation of the pre-charge command may be referred to as a write recovery time (tWR).

A semiconductor memory device capable of controlling a write recovery time may help to ensure proper operation of a synchronous semiconductor memory device.

Accordingly, the example embodiments provided may substantially address one or more of the problems that exist due to limitations and disadvantages of the conventional art.

At least one example embodiment provides a semiconductor memory device including a write recovery time control circuit that may be capable of disabling a word line after data is sufficiently written into a memory cell in a write mode.

At least one example embodiment provides a method of controlling a write recovery time of a semiconductor memory device that may be capable of disabling a word line after data is sufficiently written into a memory cell in a write mode.

According to at least one example embodiment, a semiconductor memory device may include a clock buffer, a command decoder and a write recovery time control circuit. The clock buffer may generate an internal clock signal based on an external clock signal. The command decoder may generate a write command signal by decoding an external command signal. The write recovery time control circuit may gate a plurality of bank pre-charge control signals in a wave pipeline mode based on the internal clock signal. The write command signal and a write recovery time control signal may have a plurality of bits to generate a plurality of gated bank pre-charge control signals.

According to at least one example embodiment, the write recovery time control circuit may include a master circuit and a plurality of slave circuits. The master circuit may generate a first gate control signal which may have a plurality of bits and a second gate control signal which may have a plurality of bits based on the internal clock signal, the write command signal and the write recovery time control signal. The slave circuits may gate each of the bank pre-charge control signals in a wave pipeline mode in response to the first gate control signal and the second gate control signal to generate the gated bank pre-charge control signals.

Each of the slave circuits may include a pre-charge control signal generation circuit which may perform an AND operation on a bank address signal and an auto pre-charge address signal to generate the bank pre-charge control signal.

According to at least one example embodiment, the master circuit may include a first delay circuit, a write recovery time counter, a second delay circuit and a third delay circuit. The first delay circuit may generate a first signal by delaying the write command signal by a first time. The write recovery time counter may generate a second signal by delaying the first signal by a second time in response to the internal clock signal and the write recovery time control signal. The second delay circuit may generate the first gate control signal in response to the first signal. The first gate control signal may have a phase difference that may correspond to a period of the first signal and may have a plurality of bits. The third delay circuit may generate the second gate control signal in response to the second signal. The second gate control signal may have a phase difference which may correspond to a period of the second signal and may have a plurality of bits.

The second time may be set based on enabled bits of the write recovery time control signal.

The write recovery time counter may include a plurality of flip-flops which may be operated in response to the write recovery time control signal.

According to at least one example embodiment, the second delay circuit may include a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop and a sixth flip-flop. The first flip-flop may latch a signal of an input terminal in response to the first signal to generate a first bit of the first gate control signal. The second flip-flop may latch the first bit of the first gate control signal in response to the first signal to generate a second bit of the first gate control signal. The third flip-flop may latch the second bit of the first gate control signal in response to the first signal to generate a third bit of the first gate control signal. The fourth flip-flop may latch the third bit of the first gate control signal in response to the first signal to generate a fourth bit of the first gate control signal. The fifth flip-flop may latch the fourth bit of the first gate control signal in response to the first signal to generate a fifth bit of the first gate control signal. The sixth flip-flop may latch the fifth bit of the first gate control signal in response to the first signal to generate a sixth bit of the first gate control signal. The input terminal of the first flip-flop may be electrically connected to an output terminal of the sixth flip-flop.

According to at least one example embodiment, the third delay circuit may include a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop and a sixth flip-flop. The first flip-flop may latch a signal of an input terminal in response to the second signal to generate a first bit of the second gate control signal. The second flip-flop may latch the first bit of the second gate control signal in response to the second signal to generate a second bit of the second gate control signal. The third flip-flop may latch the second bit of the second gate control signal in response to the second signal to generate a third bit of the second gate control signal. The fourth flip-flop may latch the third bit of the second gate control signal in response to the second signal to generate a fourth bit of the second gate control signal. The fifth flip-flop may latch the fourth bit of the second gate control signal in response to the second signal to generate a fifth bit of the second gate control signal. The sixth flip-flop may latch the fifth bit of the second gate control signal in response to the second signal to generate a sixth bit of the second gate control signal. The input terminal of the first flip-flop may be electrically connected to an output terminal of the sixth flip-flop.

According to at least one example embodiment, the master circuit may include a first delay circuit, a second delay circuit, a third delay circuit and a fourth delay circuit. The first delay circuit may generate a first signal by delaying the write command signal by a first time. The second delay circuit may generate a second signal by delaying the first signal by a second time. The third delay circuit may generate the first gate control signal in response to the first signal. The first gate control signal may have a phase difference that may correspond to a period of the first signal and may have a plurality of bits. The fourth delay circuit may generate the second gate control signal in response to the second signal. The second gate control signal may have a phase difference that may correspond to a period of the second signal and have a plurality of bits.

A number of the slave circuits may correspond to a number of memory banks.

Each of the slave circuits may include a first gating circuit and a second gating circuit. The first gating circuit may latch a first bank pre-charge control signal in response to the first gate control signal to generate a third signal. The second gating circuit may latch the third signal in response to the second gate control signal to generate a first gated bank pre-charge control signal.

According to at least one example embodiment, the first gating circuit may include a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop and a sixth flip-flop. The first flip-flop may latch the first bank pre-charge control signal in response to a first bit of the first gate control signal to generate a first bit of the third signal. The second flip-flop may latch the first bank pre-charge control signal in response to a second bit of the first gate control signal to generate a second bit of the third signal. The third flip-flop may latch the first bank pre-charge control signal in response to a third bit of the first gate control signal to generate a third bit of the third signal. The fourth flip-flop may latch the first bank pre-charge control signal in response to a fourth bit of the first gate control signal to generate a fourth bit of the third signal. The fifth flip-flop may latch the first bank pre-charge control signal in response to a fifth bit of the first gate control signal to generate a fifth bit of the third signal. The sixth flip-flop may latch the first bank pre-charge control signal in response to a sixth bit of the first gate control signal to generate a sixth bit of the third signal.

According to at least one example embodiment, the second gating circuit may include a first latch, a second latch, a third latch, a fourth latch, a fifth latch and a sixth latch. The first latch may latch the first bit of the third signal in response to a first bit of the second gate control signal to generate the first gated bank pre-charge control signal. The second latch may latch the second bit of the third signal in response to a second bit of the second gate control signal to generate the first gated bank pre-charge control signal. The third latch may latch the third bit of the third signal in response to a third bit of the second gate control signal to generate the first gated bank pre-charge control signal. The fourth latch may latch the fourth bit of the third signal in response to a fourth bit of the second gate control signal to generate the first gated bank pre-charge control signal. The fifth latch may latch the fifth bit of the third signal in response to a fifth bit of the second gate control signal to generate the first gated bank pre-charge control signal. The sixth latch may latch the sixth bit of the third signal in response to a sixth bit of the second gate control signal to generate the first gated bank pre-charge control signal.

According to at least one example embodiment, the write recovery time control circuit may further include a pre-charge control circuit configured to generate a plurality of pre-charge enable signals in response to the gated bank pre-charge control signals to provide the pre-charge enable signals to a row address buffer.

According to at least one example embodiment, the write recovery time control circuit may include a master circuit and a plurality of slave circuits. The master circuit may generate a first gate control signal, a second gate control signal having a plurality of bits, a third gate control signal having a plurality of bits and a fourth gate control signal. The slave circuits may gate each of the bank pre-charge control signals in a wave pipeline mode in response to the first gate control signal, the second gate control signal, the third gate control signal and the fourth gate control signal to generate the gated bank pre-charge control signals.

According to at least one example embodiment, the master circuit may include a first delay circuit, a second delay circuit, a third delay circuit, a fourth delay circuit, a fifth delay circuit and a write recovery time counter. The first delay circuit may generate the first gate control signal by delaying the write command signal by a first time. The second delay circuit may generate a first signal by delaying the first gate control signal by a second time. The third delay circuit may generate the second gate control signal in response to the first signal. The second gate control signal may have a phase difference that may correspond to a period of the first signal and may have a plurality of bits. The fourth delay circuit may generate a second signal by delaying the first signal by a third time. The fifth delay circuit may generate the third gate control signal in response to the second signal. The third gate control signal may have a phase difference that may correspond to a period of the second signal and may have a plurality of bits. The write recovery time counter may generate the fourth gate control signal by delaying the second signal by a fourth time in response to the internal clock signal and the write recovery time control signal.

According to at least one example embodiment, the first delay circuit may generate the first gate control signal by delaying the write command signal by two cycles of the internal clock signal.

The fourth time may be set based on enabled bits of the write recovery time control signal.

According to at least one example embodiment, the third delay circuit may include a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop and a sixth flip-flop.

According to at least one example embodiment, the first flip-flop may latch a signal of an input terminal in response to the first signal to generate a first bit of the second gate control signal. The second flip-flop may latch the first bit of the second gate control signal in response to the first signal to generate a second bit of the second gate control signal. The third flip-flop may latch the second bit of the second gate control signal in response to the first signal to generate a third bit of the second gate control signal. The fourth flip-flop may latch the third bit of the second gate control signal in response to the first signal to generate a fourth bit of the second gate control signal. The fifth flip-flop may latch the fourth bit of the second gate control signal in response to the first signal to generate a fifth bit of the second gate control signal. The sixth flip-flop may latch the fifth bit of the second gate control signal in response to the first signal to generate a sixth bit of the second gate control signal. The input terminal of the first flip-flop may be electrically connected to an output terminal of the sixth flip-flop.

According to at least one example embodiment, the fifth delay circuit may include a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop and a sixth flip-flop. The first flip-flop may latch a signal of an input terminal in response to the second signal to generate a first bit of the third gate control signal. The second flip-flop may latch the first bit of the third gate control signal in response to the second signal to generate a second bit of the third gate control signal. The third flip-flop may latch the second bit of the third gate control signal in response to the second signal to generate a third bit of the third gate control signal. The fourth flip-flop may latch the third bit of the third gate control signal in response to the second signal to generate a fourth bit of the third gate control signal. The fifth flip-flop may latch the fourth bit of the third gate control signal in response to the second signal to generate a fifth bit of the third gate control signal. The sixth flip-flop may latch the fifth bit of the third gate control signal in response to the second signal to generate a sixth bit of the third gate control signal. The input terminal of the first flip-flop may be electrically connected to an output terminal of the sixth flip-flop.

A number of the slave circuits may correspond to a number of memory banks.

Each of the slave circuits may include a first gating circuit, a second gating circuit, a third gating circuit and a fourth gating circuit. The first gating circuit may latch a first bank pre-charge control signal in response to the first gate control signal to generate a third signal. The second gating circuit may latch the third signal in response to the second gate control signal to generate a fourth signal having a plurality of bits. The third gating circuit may latch the fourth signal in response to the third gate control signal to generate a fifth signal. The fourth gating circuit may latch the fifth signal in response to the fourth gate control signal to generate a first gated bank pre-charge control signal.

According to at least one example embodiment, the first gating circuit may include a flip-flop configured to latch the first bank pre-charge control signal in response to a first bit of the first gate control signal to generate the third signal.

According to at least one example embodiment, the second gating circuit may include a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop and a sixth flip-flop. The first flip-flop may latch the third signal in response to a first bit of the second gate control signal to generate a first bit of the fourth signal. The second flip-flop may latch the third signal in response to a second bit of the second gate control signal to generate a second bit of the fourth signal. The third flip-flop may latch the third signal in response to a third bit of the second gate control signal to generate a third bit of the fourth signal. The fourth flip-flop may latch the third signal in response to a fourth bit of the second gate control signal to generate a fourth bit of the fourth signal. The fifth flip-flop may latch the third signal in response to a fifth bit of the second gate control signal to generate a fifth bit of the fourth signal. The sixth flip-flop may latch the third signal in response to a sixth bit of the second gate control signal to generate a sixth bit of the fourth signal.

According to at least one example embodiment, the third gating circuit may include a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop and a sixth flip-flop. The first flip-flop may latch a first bit of the fourth signal in response to a first bit of the third gate control signal to generate the fifth signal. The second flip-flop may latch a second bit of the fourth signal in response to a second bit of the third gate control signal to generate the fifth signal. The third flip-flop may latch a third bit of the fourth signal in response to a third bit of the third gate control signal to generate the fifth signal. The fourth flip-flop may latch a fourth bit of the fourth signal in response to a fourth bit of the third gate control signal to generate the fifth signal. The fifth flip-flop may latch a fifth bit of the fourth signal in response to a fifth bit of the third gate control signal to generate the fifth signal. The sixth flip-flop may latch a sixth bit of the fourth signal in response to a sixth bit of the third gate control signal to generate the fifth signal.

According to at least one example embodiment, the fourth gating circuit may include a flip-flop configured to latch the fifth signal in response to the fourth gate control signal to generate the first gated bank pre-charge control signal.

According to at least one example embodiment, the semiconductor memory device may further include an input latency control circuit which may be configured to gate an address signal in a wave pipe line mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and a write latency signal.

In a method of controlling a write recovery time of a semiconductor memory device according to at least one example embodiment, a first gate control signal which may have a plurality of bits and a second gate control signal which may have a plurality of bits may be generated, based on an internal clock signal, a write command signal and a write recovery time control signal. A plurality of bank pre-charge control signals may be gated in a wave pipeline mode in response to the first gate control signal and the second gate control signal to generate a plurality of gated bank pre-charge control signals.

In a method of controlling a write recovery time of a semiconductor memory device according to at least one example embodiment, a first gate control signal, a second gate control signal which may have a plurality of bits, a third gate control signal which may have a plurality of bits and a fourth gate control signal may be generated in response to an internal clock signal, a write command signal and a write recovery time control signal. A plurality of bank pre-charge control signals may be gated in a wave pipeline mode in response to the first gate control signal, the second gate control signal, the third gate control signal and the fourth gate control signal to generate a plurality of gated bank pre-charge control signals.

Therefore, the semiconductor memory device including the write recovery time control circuit may decrease the number of flip-flops required to control a write recovery time.

The above and other features and advantages of example embodiments will become more apparent by describing in detail example embodiments with reference to the attached drawings. The accompanying drawings are intended to depict example embodiments and should not be interpreted to limit the intended scope of the claims. The accompanying drawings are not to be considered as drawn to scale unless explicitly noted.

FIG. 1 is a block diagram illustrating a semiconductor memory device according to at least one example embodiment.

FIG. 2 is a block diagram illustrating a write recovery time control circuit in the semiconductor memory device of FIG. 1 according to at least one example embodiment.

FIG. 3 is a block diagram an example of a master circuit in the write recovery time control circuit of FIG. 2 according to at least one example embodiment.

FIG. 4 is a circuit diagram illustrating a write recovery time counter in the master circuit of FIG. 3 according to at least one example embodiment.

FIG. 5 is a circuit diagram illustrating a second delay circuit in the master circuit of FIG. 3 according to at least one example embodiment.

FIG. 6 is a circuit diagram illustrating a third delay circuit in the master circuit of FIG. 3 according to at least one example embodiment.

FIG. 7 is a block diagram illustrating a master circuit in the write recovery time control circuit of FIG. 2 according to at least one example embodiment.

FIG. 8 is a circuit diagram illustrating a pre-charge control signal generation circuit in the slave circuit of FIG. 2 according to at least one example embodiment.

FIG. 9 is a circuit diagram illustrating a first slave unit in the slave circuit of FIG. 2 according to at least one example embodiment.

FIG. 10 is a circuit diagram illustrating an eighth slave unit in the slave circuit of FIG. 2 according to at least one example embodiment.

FIG. 11 is a block diagram illustrating a write recovery time control circuit in the semiconductor memory device of FIG. 1 according to at least one example embodiment.

FIG. 12 is a block diagram illustrating a master circuit in the write recovery time control circuit of FIG. 11 according to at least one example embodiment.

FIG. 13 is a circuit diagram illustrating a third delay circuit in the master circuit of FIG. 11 according to at least one example embodiment.

FIG. 14 is a circuit diagram illustrating a first slave unit in the slave circuit of FIG. 11 according to at least one example embodiment.

FIG. 15 is a timing diagram illustrating generation time points of a pre-charge command according to a write recovery time.

FIG. 16 is a timing diagram illustrating an operation of the write recovery time control circuit of FIG. 11 .

Detailed example embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but to the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of example embodiments. Like numbers refer to like elements throughout the description of the figures.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the relevant art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 is a block diagram illustrating a semiconductor memory device according to at least one example embodiment.

Referring to FIG. 1 , a semiconductor memory device 1000 may include a memory cell array 1100 , an address buffer 1800 , a row address buffer 1850 , a row decoder 1150 , a column decoder 1200 , a bank decoder 1250 , a data input circuit 1300 , a data output circuit 1350 , a clock buffer 1400 , a command decoder 1450 , a Mode Register Set (MRS) circuit 1500 , a write latency control circuit 1600 and a write recovery time control circuit 1700 .

The memory cell array 1100 may be a data storage space where a lot of memory cells may be arranged in a matrix configuration. The data input circuit 1300 may buffer an input data DIN and may write the buffered input data to the memory cell array 1100 . The data output circuit 1350 may buffer data read from the memory cell array 1100 and may output the buffered data as an output data DOUT. The address buffer 1800 may receive an external address signal XADDR, may buffer the external address signal XADDR and may generate an internal address signal ADDR. The row address buffer 1850 may buffer the internal address signal ADDR in response to a pre-charge enable signal PREC_EN and may generate a buffered row address signal RA. The row decoder 1150 may decode the buffered row address signal RA. The column decoder 1200 may receive a column address signal CA from the write latency control circuit 1600 , may decode the column address signal CA and may generate a decoded column address signal. The bank decoder 1250 may receive a bank address signal CBA from the write latency control circuit 1600 , may decode the bank address signal CBA and may generate a decoded bank address signal for selecting a memory bank.

The clock buffer 1400 may receive an external clock signal ECLK, may buffer the external clock signal ECLK and may generate an internal clock signal PCLK. The command decoder 1450 may receive a command signal CMD such as /WE, /CS, /RAS and /CAS etc., from an external device, may decode the command signal CMD and may output a decoded command signal (for example, PWA). The MRS circuit 1500 may set a mode set register (MSR) in response to the internal address signal ADDR and a MRS command MRS_CMD for designating an operation mode. A write latency signal WLi and a write recovery time control signal tWRi may be set in response to MRS command MRS_CMD and may be stored in the mode set register included in the MRS circuit 1500 .

The write latency control circuit 1600 may gate the internal address signal ADDR in a wave pipeline mode based on the internal clock signal PCLK, the write command signal PWA and the write latency signal WLi, and may generate the column address signal CA and the bank address signal CBA. The write latency control circuit 1600 may generate bank address signals CBAW_A through CBAW_H and an auto pre-charge address signal CA 8 .

The write recovery time control circuit 1700 may gate bank pre-charge control signals PWAPT_A through PWAPT_H in a wave pipeline mode based on the internal clock signal PCLK, the write command signal PWA and a write recovery time control signal tWRi. The write recovery time control circuit 1700 may generate a plurality of bank pre-charge control signals that may be gated, and may generate the pre-charge enable signal PREC_EN which may correspond to the bank pre-charge control signals PWAPT_A through PWAPT_H. The bank pre-charge control signals PWAPT_A through PWAPT_H may be generated based on the bank address signals CBAW_A through CBAW_H and the auto pre-charge address signal CA 8 as will be described with reference to FIG. 8 .

FIG. 2 is a block diagram illustrating a write recovery time control circuit in the semiconductor memory device of FIG. 1 according to at least one example embodiment. The write recovery time control circuit 1700 as illustrated in FIG. 2 may be included in the semiconductor memory device formed with eight memory banks A, B, C, D, E, F, G and H.

Referring to FIG. 2 , the write recovery time control circuit 1700 may include a master circuit 1710 , a slave circuit 1750 and a pre-charge control circuit 1755 .

The master circuit 1710 may generate a first gate control signal which may have bits PWA_DIS 1 through PWA_DIS 6 and a second gate control signal which may have bits PWAP_EN 1 through PWAP_EN 6 , based on the internal clock signal PCLK, the write command signal PWA and the write recovery time control signal tWRi.

The slave circuit 1750 may gate the bank pre-charge control signals PWAPT_A through PWAPT_H in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a plurality of gated bank pre-charge control signals PAPB_A through PAPB_H.

As illustrated in FIG. 8 , a pre-charge control signal generation circuit 1760 may perform an AND operation on the bank address signals CBAW_A through CBAW_H and the auto pre-charge address signal CA 8 , and may generate the bank pre-charge control signals PWAPT_A through PWAPT_H.

The slave circuit 1750 may include a first slave unit 1750 A, a second slave unit 1750 B, a third slave unit 1750 C, a fourth slave unit 1750 D, a fifth slave unit 1750 E, a sixth slave unit 1750 F, a seventh slave unit 1750 G and a eighth slave unit 1750 H.

Referring to FIGS. 2 and 8 , the first slave unit 1750 A may gates a bank pre-charge control signal PWAPT_A for a bank A in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generates a gated bank pre-charge control signal PAPB_A for the bank A. The second slave unit 1750 B may gate a bank pre-charge control signal PWAPT_B for a bank B in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a gated bank pre-charge control signal PAPB_B for the bank B. The third slave unit 1750 C may gate a bank pre-charge control signal PWAPT_C for a bank C in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a gated bank pre-charge control signal PAPB_C for the bank C. The fourth slave unit 1750 D may gate a bank pre-charge control signal PWAPT_D for a bank D in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a gated bank pre-charge control signal PAPB_D for the bank D. The fifth slave unit 1750 E may gate a bank pre-charge control signal PWAPT_E for a bank E in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a gated bank pre-charge control signal PAPB_E for the bank E. The sixth slave unit 1750 F may gate a bank pre-charge control signal PWAPT_F for a bank F in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a gated bank pre-charge control signal PAPB_F for the bank F. The seventh slave unit 1750 G may gate a bank pre-charge control signal PWAPT_G for a bank G in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a gated bank pre-charge control signal PAPB_G for the bank G. The eighth slave unit 1750 H may gate a bank pre-charge control signal PWAPT_H for a bank H in a wave pipeline mode in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and the second gate control signal PWAP_EN 1 through PWAP_EN 6 , and may generate a gated bank pre-charge control signal PAPB_H for the bank H.

The pre-charge control circuit 1755 may include a plurality of pre-charge control units (not shown) which may operate for the memory banks A through H, respectively; may generate pre-charge enable signals PREC_EN 1 through PREC_EN 6 in response to the gated bank pre-charge control signals PAPB_A, PAPB_B, PAPB_C, PAPB_D, PAPB_E, PAPB_F, PAPB_G and PAPB_H; and may provide the pre-charge enable signals PREC_EN 1 through PREC_EN 6 to the row address buffer 1850 in FIG. 1 .

The write recovery time control circuit 1700 may control a generation time point of the gated bank pre-charge control signals PAPB_A, PAPB_B, PAPB_C, PAPB_D, PAPB_E, PAPB_F, PAPB_G and PAPB_H in response to the write recovery time control signal tWRi (i is a natural number). That is, the write recovery time control circuit 1700 may control an activation time point of gated bank pre-charge control signals PAPB_A, PAPB_B, PAPB_C, PAPB_D, PAPB_E, PAPB_F, PAPB_G and PAPB_H for pre-charging the memory banks A through H by delaying the bank pre-charge control signals PWAPT_A through PWAPT_H, with reference to the activation time point of the write command signal PWA, by clock cycles, where the clock cycles may be determined based on the write recovery time control signal tWRi.

FIG. 3 is a block diagram of a master circuit in the write recovery time control circuit of FIG. 2 according to at least one example embodiment.

Referring to FIG. 3 , the master circuit 1710 A may include a first delay circuit 1711 , a write recovery time counter 1713 , a second delay circuit 1715 and a third delay circuit 1717 .

The first delay circuit 1711 may generate a first signal PWA_DIS by delaying the write command signal PWA by a first time. The write recovery time counter 1713 may generate a second signal PWAP_EN by delaying the first signal PWA_DIS by a second time in response to the internal clock signal PCLK and a write recovery time control signal tWR 1 through tWR 11 . The second delay circuit 1715 may generate the first gate control signal PWA_DIS 1 through PWA_DIS 6 in response to the first signal PWA_DIS. The first gate control signals PWA_DIS 1 through PWA_DIS 6 may have a phase difference which may correspond to a period of the first signal PWA_DIS and may have a plurality of bits. The third delay circuit 1717 may generate the second gate control signal PWAP_EN 1 through PWAP_EN 6 in response to the second signal PWAP_EN. The second gate control signal PWAP_EN 1 through PWAP_EN 6 may have a phase difference corresponding to a period of the second signal PWAP_EN and may have a plurality of bits.

FIG. 4 is a circuit diagram illustrating a write recovery time counter in the master circuit of FIG. 3 according to at least one example embodiment. The write recovery time counter 1713 may include flip-flops F 1 through F 11 which may be operated in response to the write recovery time control signal tWR 1 through tWR 11 . Each of the flip-flops F 1 through F 11 may be a D flip-flop.

Referring to FIG. 4 , a first flip-flop F 1 may latch the first signal PWA_DIS in response to the internal clock signal PCLK. A second flip-flop F 2 may latch one of the first signal PWA_DIS and an output signal of the first flip-flop F 1 in response to the internal clock signal PCLK. A third flip-flop F 3 may latch one of the first signal PWA_DIS and an output signal of the second flip-flop F 2 in response to the internal clock signal PCLK. A fourth flip-flop F 4 may latch one of the first signal PWA_DIS and an output signal of the third flip-flop F 3 in response to the internal clock signal PCLK. A fifth flip-flop F 5 may latch one of the first signal PWA_DIS and an output signal of the fourth flip-flop F 4 in response to the internal clock signal PCLK. A sixth flip-flop F 6 may latch one of the first signal PWA_DIS and an output signal of the fifth flip-flop F 5 in response to the internal clock signal PCLK. A seventh flip-flop F 7 may latch one of the first signal PWA_DIS and an output signal of the sixth flip-flop F 6 in response to the internal clock signal PCLK. An eighth flip-flop F 8 may latch one of the first signal PWA_DIS and an output signal of the seventh flip-flop F 7 in response to the internal clock signal PCLK. A ninth flip-flop F 9 may latch one of the first signal PWA_DIS and an output signal of the eighth flip-flop F 8 in response to the internal clock signal PCLK. A tenth flip-flop F 10 may latch one of the first signal PWA_DIS and an output signal of the ninth flip-flop F 9 in response to the internal clock signal PCLK. An eleventh flip-flop F 11 may latch one of the first signal PWA_DIS and an output signal of the tenth flip-flop F 10 in response to the internal clock signal PCLK. An output signal of the eleventh flip-flop F 11 may be the second signal PWAP_EN.

Hereinafter, an operation of the write recovery time counter 1713 is described.

The number of flip-flops included in the write recovery time counter 1713 may be determined according to a maximum value of a write recovery time. That is, when the maximum value of the write recovery time is M (M is a natural number), M numbers of flip-flops may be included in the write recovery time counter 1713 . In FIG. 4 , the maximum value of the write recovery time is 11 tCK, where 1 tCK is one clock cycle (one period) of the internal clock signal PCLK.

When the write recovery time is 11 tCK, the first signal PWA_DIS may be inputted to an input terminal of the first flip-flop F 1 and the first signal PWA_DIS may be sequentially passed from the first flip-flop F 1 to the eleventh flip-flop F 1 . Therefore, the output signal PWAP_EN of the write recovery time counter 1713 may be delayed by 11 tCK in comparison with the first signal PWA_DIS.

When the write recovery time is 6 tCK, the first signal PWA_DIS may be inputted to an input terminal of the sixth flip-flop F 6 and the first signal PWA_DIS may be sequentially passed from the sixth flip-flop F 6 to the eleventh flip-flop F 1 . Therefore, the output signal PWAP_EN of the write recovery time counter 1713 may be delayed by 6 tCK in comparison with the first signal PWA_DIS.

FIG. 5 is a circuit diagram illustrating a second delay circuit in the master circuit of FIG. 3 according to at least one example embodiment.

Referring to FIG. 5 , the second delay circuit 1715 may include a first flip-flop F 12 , a second flip-flop F 13 , a third flip-flop F 14 , a fourth flip-flop F 15 , a fifth flip-flop F 16 and a sixth flip-flop F 17 .

The first flip-flop F 12 may latch a signal of an input terminal in response to the first signal PWA_DIS and may generate a first bit PWA_DIS 1 of the first gate control signal. The second flip-flop F 13 may latch the first bit PWA_DIS 1 of the first gate control signal in response to the first signal PWA_DIS and may generate a second bit PWA_DIS 2 of the first gate control signal. The third flip-flop F 14 may latch the second bit PWA_DIS 2 of the first gate control signal in response to the first signal PWA_DIS and may generate a third bit PWA_DIS 3 of the first gate control signal. The fourth flip-flop F 15 may latch the third bit PWA_DIS 3 of the first gate control signal in response to the first signal PWA_DIS and may generate a fourth bit PWA_DIS 4 of the first gate control signal. The fifth flip-flop F 16 may latch the fourth bit PWA_DIS 4 of the first gate control signal in response to the first signal PWA_DIS and may generate a fifth bit PWA_DIS 5 of the first gate control signal. The sixth flip-flop F 17 may latch the fifth bit PWA_DIS 5 of the first gate control signal in response to the first signal PWA_DIS and may generate a sixth bit PWA_DIS 6 of the first gate control signal. The input terminal of the first flip-flop F 12 may be electrically connected to an output terminal of the sixth flip-flop F 17 .

FIG. 6 is a circuit diagram illustrating a third delay circuit in the master circuit of FIG. 3 according to at least one example embodiment.

Referring to FIG. 6 , the third delay circuit 1717 may include a first flip-flop F 18 , a second flip-flop F 19 , a third flip-flop F 20 , a fourth flip-flop F 21 , a fifth flip-flop F 22 and a sixth flip-flop F 23 .

The first flip-flop F 18 may latch a signal of an input terminal in response to the second signal PWAP_EN and may generate a first bit PWAP_EN 1 of the second gate control signal. The second flip-flop F 19 may latch the first bit PWAP_EN 1 of the second gate control signal in response to the second signal PWAP_EN and may generate a second bit PWAP_EN 2 of the second gate control signal. The third flip-flop F 20 may latch the second bit PWAP_EN 2 of the second gate control signal in response to the second signal PWAP_EN and may generate a third bit PWAP_EN 3 of the second gate control signal. The fourth flip-flop F 21 may latch the third bit PWAP_EN 3 of the second gate control signal in response to the second signal PWAP_EN and may generate a fourth bit PWAP_EN 4 of the second gate control signal. The fifth flip-flop F 22 may latch the fourth bit PWAP_EN 4 of the second gate control signal in response to the second signal PWAP_EN and may generate a fifth bit PWAP_EN 5 of the second gate control signal. The sixth flip-flop F 23 may latch the fifth bit PWAP_EN 5 of the second gate control signal in response to the second signal PWAP_EN and may generate a sixth bit PWAP_EN 6 of the second gate control signal. The input terminal of the first flip-flop F 18 may be electrically connected to an output terminal of the sixth flip-flop F 23 .

FIG. 7 is a block diagram illustrating a master circuit in the write recovery time control circuit of FIG. 2 according to at least one example embodiment.

Referring to FIG. 7 , the master circuit 1710 B may include a fourth delay circuit 1712 , a fifth delay circuit 1714 , a sixth delay circuit 1716 and a seventh delay circuit 1718 .

The fourth delay circuit 1712 may generate a first signal PWA_DIS by delaying the write command signal PWA by a first time. The fifth delay circuit 1714 may generate a second signal PWAP_EN by delaying the first signal PWA_DIS by a second time. The sixth delay circuit 1716 may generate the first gate control signal PWA_DIS 1 through PWA_DIS 6 in response to the first signal PWA_DIS. The first gate control signals PWA_DIS 1 through PWA_DIS 6 may have a phase difference which may correspond to a period of the first signal PWA_DIS and may have a plurality of bits. The seventh delay circuit 1718 may generate the second gate control signal PWAP_EN 1 through PWAP_EN 6 in response to the second signal PWAP_EN. The second gate control signal PWAP_EN 1 through PWAP_EN 6 may have a phase difference which may correspond to a period of the second signal PWAP_EN and may have a plurality of bits.

The master circuit 1710 B of FIG. 7 may include the fifth delay circuit 1714 instead of the write recovery time counter 1713 which was illustrated as being included in the master circuit 1710 A in FIG. 3 . That is, the master circuit 1710 B may not use the write recovery time control signal tWR 1 through tWR 11 and may generate the second signal PWAP_EN by delaying the first signal PWA_DIS using a delay circuit.

FIG. 8 is a circuit diagram illustrating a pre-charge control signal generation circuit in the slave circuit of FIG. 2 according to at least one example embodiment.

Referring to FIG. 8 , the pre-charge control signal generation circuit 1760 may be included in the slave circuit 1750 , and the pre-charge control signal generation circuit 1760 may generate the bank pre-charge control signals PWAPT_A through PWAPT_H for memory banks A through H, based on the bank address signals CBAW_A through CBAW_H and the auto pre-charge address signal CA 8 .

The pre-charge control signal generation circuit 1760 may include a first pre-charge control signal generation unit 1760 A, a second pre-charge control signal generation unit 1760 B, a third pre-charge control signal generation unit 1760 C, a fourth pre-charge control signal generation unit 1760 D, a fifth pre-charge control signal generation unit 1760 E, a sixth pre-charge control signal generation unit 1760 F, a seventh pre-charge control signal generation unit 1760 G and a eighth pre-charge control signal generation unit 1760 H.

The first pre-charge control signal generation unit 1760 A may include a first NAND gate 1761 and a first inverter 1769 . The first NAND gate 1761 may perform a NAND operation on a first bank address signal CBAW_A and the auto pre-charge address signal CA 8 . The first inverter 1769 may invert an output signal of the first NAND gate 1761 . The second pre-charge control signal generation unit 1760 B may include a second NAND gate 1762 and a second inverter 1770 . The second NAND gate 1762 may perform a NAND operation on a second bank address signal CBAW_B and the auto pre-charge address signal CA 8 . The second inverter 1770 may invert an output signal of the second NAND gate 1762 . The third pre-charge control signal generation unit 1760 C may include a third NAND gate 1763 and a third inverter 1771 . The third NAND gate 1763 may perform a NAND operation on a third bank address signal CBAW_C and the auto pre-charge address signal CA 8 . The third inverter 1771 may invert an output signal of the third NAND gate 1763 . The fourth pre-charge control signal generation unit 1760 D may include a fourth NAND gate 1764 and a fourth inverter 1772 . The fourth NAND gate 1764 may perform a NAND operation on a fourth bank address signal CBAW_D and the auto pre-charge address signal CA 8 . The fourth inverter 1772 may invert an output signal of the fourth NAND gate 1764 . The fifth pre-charge control signal generation unit 1760 E may include a fifth NAND gate 1765 and a fifth inverter 1773 . The fifth NAND gate 1765 may perform a NAND operation on a fifth bank address signal CBAW_E and the auto pre-charge address signal CA 8 . The fifth inverter 1773 may invert an output signal of the fifth NAND gate 1765 . The sixth pre-charge control signal generation unit 1760 F may include a sixth NAND gate 1766 and a sixth inverter 1774 . The sixth NAND gate 1766 may perform a NAND operation on a sixth bank address signal CBAW_F and the auto pre-charge address signal CA 8 . The sixth inverter 1774 may invert an output signal of the sixth NAND gate 1766 . The seventh pre-charge control signal generation unit 1760 G may include a seventh NAND gate 1767 and a seventh inverter 1775 . The seventh NAND gate 1767 may perform a NAND operation on a seventh bank address signal CBAW_G and the auto pre-charge address signal CA 8 . The seventh inverter 1775 may invert an output signal of the seventh NAND gate 1767 . The eighth pre-charge control signal generation unit 1760 H may include an eighth NAND gate 1768 and an eighth inverter 1776 . The eighth NAND gate 1768 may perform a NAND operation on an eighth bank address signal CBAW_H and the auto pre-charge address signal CA 8 . The eighth inverter 1776 may invert an output signal of the eighth NAND gate 1768 .

The bank address signals CBAW_A through CBAW_H may represent information about the memory banks A, B, C, D, E, F, G and H, which may form a memory cell array, and the auto pre-charge address signal CA 8 may represent information about an auto pre-charge. Therefore, the bank pre-charge control signals PWAPT_A through PWAPT_H, which may be generated by performing a NAND operation on the bank address signals CBAW_A through CBAW_H and the auto pre-charge address signal CA 8 , may represent information about a memory bank that is pre-charged.

FIG. 9 is a circuit diagram illustrating a first slave unit in the slave circuit of FIG. 2 according to at least one example embodiment, and FIG. 10 is a circuit diagram illustrating an eighth slave unit in the slave circuit of FIG. 2 according to at least one example embodiment.

FIG. 9 illustrates the first slave unit 1750 A generating a first gated bank pre-charge control signal PAPB_A for a bank A and FIG. 10 illustrates the eighth slave unit 1750 H generating an eighth gated bank pre-charge control signal PAPB_H for a bank H.

Referring to FIG. 9 , the first slave unit 1750 A may include a first gating circuit and a second gating circuit. The first gating circuit may latch the first bank pre-charge control signal PWAPT_A in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and may generate a third signal having a plurality of bits. The second gating circuit may latch each bit of the third signal and may generate the first gated bank pre-charge control signal PAPB_A.

The first gating circuit may include a first flip-flop F 24 , a second flip-flop F 25 , a third flip-flop F 26 , a fourth flip-flop F 27 , a fifth flip-flop F 28 and a sixth flip-flop F 29 .

The first flip-flop F 24 may latch the first bank pre-charge control signal PWAPT_A in response to the first bit PWA_DIS 1 of the first gate control signal and may generate a first bit of the third signal. The second flip-flop F 25 may latch the first bank pre-charge control signal PWAPT_A in response to the second bit PWA_DIS 2 of the first gate control signal and may generate a second bit of the third signal. The third flip-flop F 26 may latch the first bank pre-charge control signal PWAPT_A in response to the third bit PWA_DIS 3 of the first gate control signal and may generate a third bit of the third signal. The fourth flip-flop F 27 may latch the first bank pre-charge control signal PWAPT_A in response to the fourth bit PWA_DIS 4 of the first gate control signal and may generate a fourth bit of the third signal. The fifth flip-flop F 28 may latch the first bank pre-charge control signal PWAPT_A in response to the fifth bit PWA_DIS 5 of the first gate control signal and may generate a fifth bit of the third signal. The sixth flip-flop F 29 may latch the first bank pre-charge control signal PWAPT_A in response to the sixth bit PWA_DIS 6 of the first gate control signal and may generate a sixth bit of the third signal.

The second gating circuit may include a first latch LA 1 , a second latch LA 2 , a third latch LA 3 , a fourth latch LA 4 , a fifth latch LA 5 and a sixth latch LA 6 .

The first latch LA 1 may latch the first bit of the third signal in response to the first bit PWAP_EN 1 of the second gate control signal and may generate the first gated bank pre-charge control signal PAPB_A. The second latch LA 2 may latch the second bit of the third signal in response to the second bit PWAP_EN 2 of the second gate control signal and may generate the first gated bank pre-charge control signal PAPB_A. The third latch LA 3 may latch the third bit of the third signal in response to the third bit PWAP_EN 3 of the second gate control signal and may generate the first gated bank pre-charge control signal PAPB_A. The fourth latch LA 4 may latch the fourth bit of the third signal in response to the fourth bit PWAP_EN 4 of the second gate control signal and may generate the first gated bank pre-charge control signal PAPB_A. The fifth latch LA 5 may latch the fifth bit of the third signal in response to the fifth bit PWAP_EN 5 of the second gate control signal and may generate the first gated bank pre-charge control signal PAPB_A. The sixth latch LA 6 may latch the sixth bit of the third signal in response to the sixth bit PWAP_EN 6 of the second gate control signal and may generate the first gated bank pre-charge control signal PAPB_A. Output terminals of the latches LA 1 through LA 6 may be electrically connected to each other.

Referring to FIG. 10 , the eighth slave unit 1750 H may include a third gating circuit and a fourth gating circuit. The third gating circuit may latch an eighth bank pre-charge control signal PWAPT_H in response to the first gate control signal PWA_DIS 1 through PWA_DIS 6 and may generate the third signal having a plurality of bits. The fourth gating circuit may latch each bit of the third signal in response to the second gate control signal PWAP_EN 1 through PWAP_EN 6 and may generate an eighth gated bank pre-charge control signal PAPB_H.

The third gating circuit may include a seventh flip-flop F 31 , an eighth flip-flop F 32 , a ninth flip-flop F 33 , a tenth flip-flop F 34 , an eleventh flip-flop F 35 and a twelfth flip-flop F 36 .

The seventh flip-flop F 31 may latch the eighth bank pre-charge control signal PWAPT_H in response to the first bit PWA_DIS 1 of the first gate control signal and may generate a first bit of the third signal. The eighth flip-flop F 32 may latch the eighth bank pre-charge control signal PWAPT_H in response to the second bit PWA_DIS 2 of the first gate control signal and may generate a second bit of the third signal. The ninth flip-flop F 33 may latch the eighth bank pre-charge control signal PWAPT_H in response to the third bit PWA_DIS 3 of the first gate control signal and may generate a third bit of the third signal. The tenth flip-flop F 34 may latch the eighth bank pre-charge control signal PWAPT_H in response to the fourth bit PWA_DIS 4 of the first gate control signal and may generate a fourth bit of the third signal. The eleventh flip-flop F 35 may latch the eighth bank pre-charge control signal PWAPT_H in response to the fifth bit PWA_DIS 5 of the first gate control signal and may generate a fifth bit of the third signal. The twelfth flip-flop F 36 may latch the eighth bank pre-charge control signal PWAPT_H in response to the sixth bit PWA_DIS 6 of the first gate control signal and may generate a sixth bit of the third signal.

The fourth gating circuit may include a seventh latch LA 7 , an eighth latch LA 8 , a ninth latch LA 9 , a tenth latch LA 10 , an eleventh latch LA 11 and a twelfth latch L 12 .

The seventh latch LA 7 may latch the first bit of the third signal in response to the first bit PWAP_EN 1 of the second gate control signal and may generate the eighth gated bank pre-charge control signal PAPB_H. The eighth latch LA 8 may latch the second bit of the third signal in response to the second bit PWAP_EN 2 of the second gate control signal and may generate the eighth gated bank pre-charge control signal PAPB_H. The ninth latch LA 9 may latch the third bit of the third signal in response to the third bit PWAP_EN 3 of the second gate control signal and may generate the eighth gated bank pre-charge control signal PAPB_H. The tenth latch LA 10 may latch the fourth bit of the third signal in response to the fourth bit PWAP_EN 4 of the second gate control signal and may generate the eighth gated bank pre-charge control signal PAPB_H. The eleventh latch LA 11 may latch the fifth bit of the third signal in response to the fifth bit PWAP_EN 5 of the second gate control signal and may generate the eighth gated bank pre-charge control signal PAPB_H. The twelfth latch LA 12 may latch the sixth bit of the third signal in response to the sixth bit PWAP_EN 6 of the second gate control signal and may generate the eighth gated bank pre-charge control signal PAPB_H. Output terminals of the latches LA 7 through LA 12 may be electrically connected to each other.

As such, the second slave unit 1750 B, the third slave unit 1750 C, the fourth slave unit 1750 D, the fifth slave unit 1750 E, the sixth slave unit 1750 F and the seventh slave unit 1750 G may be equally implemented as the first slave unit 1750 A of FIG. 9 .

The write recovery time control circuit 1700 described with reference to FIG. 2 through FIG. 10 may gate the bank pre-charge control signals PWAPT_A through PWAPT_H in a wave pipeline mode, based on the internal clock signal PCLK, the write command signal PWA and the write recovery time control signal tWRi; may generate the gated bank pre-charge control signals; and may generate the pre-charge enable signal PREC_EN which may correspond to the bank pre-charge control signals PWAPT_A through PWAPT_H. Therefore, a semiconductor memory device including a write recovery time control circuit according to the present invention may decrease a number of flip-flops required to control a write recovery time.

FIG. 11 is a block diagram illustrating a write recovery time control circuit in the semiconductor memory device of FIG. 1 according to at least one example embodiment. The write recovery time control circuit 1900 as illustrated in FIG. 11 may be included in the semiconductor memory device formed with eight memory banks A, B, C, D, E, F, G and H.

Referring to FIG. 11 , the write recovery time control circuit 1900 may include a master circuit 1910 , a slave circuit 1950 and a pre-charge control circuit 1955 .

The master circuit 1910 may generate a first gate control signal PWA_CSL, a second gate control signal which may have bits PWA_D 1 through PWA_D 6 , a third gate control signal PWA_DIS 1 through PWA_DIS 6 and a fourth gate control signal PWAP_EN, based on the internal clock signal PCLK, the write command signal PWA and the write recovery time control signal tWRi.

The slave circuit 1950 may gate each of bank pre-charge control signals PWAPT_A through PWAPT_H in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN; and may generate a plurality of gated bank pre-charge control signals PAPB_A through PAPB_H.

As illustrated in FIG. 8 , the pre-charge control signal generation circuit 1760 may perform an AND operation on the bank address signals CBAW_A through CBAW_H and the auto pre-charge address signal CA 8 , and may generate the bank pre-charge control signals PWAPT_A through PWAPT_H.

The slave circuit 1950 may include a first slave unit 1950 A, a second slave unit 1950 B, a third slave unit 1950 C, a fourth slave unit 1950 D, a fifth slave unit 1950 E, a sixth slave unit 1950 F, a seventh slave unit 1950 G and an eighth slave unit 1950 H.

Referring to FIGS. 8 and 11 , the first slave unit 1950 A may gate a bank pre-charge control signal PWAPT_A for a bank A in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN, and may generate a gated bank pre-charge control signal PAPB_A for the bank A. The second slave unit 1950 B may gate a bank pre-charge control signal PWAPT_B for a bank B in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN; and may generate a gated bank pre-charge control signal PAPB_B for the bank B. The third slave unit 1950 C may gate a bank pre-charge control signal PWAPT_C for a bank C in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN, and may generate a gated bank pre-charge control signal PAPB_C for the bank C. The fourth slave unit 1950 D may gate a bank pre-charge control signal PWAPT_D for a bank D in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN; and may generate a gated bank pre-charge control signal PAPB_D for the bank D. The fifth slave unit 1950 E may gate a bank pre-charge control signal PWAPT_E for a bank E in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN; and may generate a gated bank pre-charge control signal PAPB_E for the bank E. The sixth slave unit 1950 F may gate a bank pre-charge control signal PWAPT_F for a bank F in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN; and may generate a gated bank pre-charge control signal PAPB_F for the bank F. The seventh slave unit 1950 G may gate a bank pre-charge control signal PWAPT_G for a bank G in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN, and may generate a gated bank pre-charge control signal PAPB_G for the bank G. The eighth slave unit 1950 H may gate a bank pre-charge control signal PWAPT_H for a bank H in a wave pipeline mode in response to the first gate control signal PWA_CSL, the second gate control signal PWA_D 1 through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN, and may generate a gated bank pre-charge control signal PAPB_H for the bank H.

The pre-charge control circuit 1955 may include a plurality of pre-charge control units (not shown) respectively operating for the memory banks A through H; may generate pre-charge enable signals PREC_EN 1 through PREC_EN 6 in response to the gated bank pre-charge control signals PAPB_A, PAPB_B, PAPB_C, PAPB_D, PAPB_E, PAPB_F, PAPB_G and PAPB_H; and may provide the pre-charge enable signals PREC_EN 1 through PREC_EN 6 to the row address buffer 1850 .

The write recovery time control circuit 1900 may control a generation time point of the gated bank pre-charge control signals PAPB_A, PAPB_B, PAPB_C, PAPB_D, PAPB_E, PAPB_F, PAPB_G and PAPB_H in response to the write recovery time control signal tWRi (i is a natural number). That is, the write recovery time control circuit 1900 may control an activation time point of gated bank pre-charge control signals PAPB_A, PAPB_B, PAPB_C, PAPB_D, PAPB_E, PAPB_F, PAPB_G and PAPB_H for pre-charging the memory banks A through H by delaying the bank pre-charge control signals PWAPT_A through PWAPT_H by clock cycles with reference to an activation time point of the write command signal PWA, where the clock cycles may be determined based on the write recovery time control signal tWRi.

FIG. 12 is a block diagram illustrating a master circuit in the write recovery time control circuit of FIG. 11 according to at least one example embodiment.

Referring to FIG. 12 , the master circuit 1910 includes a first delay circuit 1721 , a second delay circuit 1722 , a third delay circuit 1723 , a fourth delay circuit 1724 , a fifth delay circuit 1725 and a write recovery time counter 1726 .

The first delay circuit 1721 may generate the first gate control signal PWA_CSL by delaying the write command signal PWA by a first time. The second delay circuit 1722 may generate a first signal PWA_D by delaying the first gate control signal PWA_CSL by a second time. The third delay circuit 1723 may generate the second gate control signal PWA_D 1 through PWA_D 6 in response to the first signal PWA_D. The second gate control signal PWA_D 1 through PWA_D 6 may have a phase difference which may correspond to a period of the first signal PWA_D and may have a plurality of bits. The fourth delay circuit 1724 may generate a second signal PWA_DIS by delaying the first signal PWA_D by a third time. The fifth delay circuit 1725 may generate the third gate control signal PWA_DIS 1 through PWA_DIS 6 in response to the second signal PWA_DIS. The third gate control signals PWA_DIS 1 through PWA_DIS 6 may have a phase difference which may correspond to a period of the second signal PWA_DIS and may have a plurality of bits. The write recovery time counter 1726 may generate the fourth gate control signal PWAP_EN by delaying the second signal PWA_DIS by a fourth time in response to the internal clock signal PCLK and the write recovery time control signal tWR 1 through tWR 11 .

For example, the first delay circuit 1721 may generate the first gate control signal PWA_CSL by delaying the write command signal PWA by 2 tCK. The second delay circuit 1722 may generate the first signal PWA_D by delaying the first gate control signal PWA_CSL by 1 tCK. The fourth delay circuit 1724 may generate the second signal PWA_DIS by delaying the first signal PWA_D by 1 tCK.

The fifth delay circuit 1725 may be equally formed as the second delay circuit 1715 of FIG. 3 , and the write recovery time counter 1726 may be equally formed as the write recovery time counter 1713 of FIG. 3 .

FIG. 13 is a circuit diagram illustrating a third delay circuit in the master circuit of FIG. 11 according to at least one example embodiment.

The third delay circuit 1723 may include a first flip-flop F 37 , a second flip-flop F 38 , a third flip-flop F 39 , a fourth flip-flop F 40 , a fifth flip-flop F 41 and a sixth flip-flop F 42 .

The first flip-flop F 37 may latch a signal of an input terminal in response to the first signal PWA_D and may generate a first bit of the second gate control signal PWA_D 1 . The second flip-flop F 38 may latch the first bit PWA_D 1 of the second gate control signal in response to the first signal PWA_D and may generate a second bit PWA_D 2 of the second gate control signal. The third flip-flop F 39 may latch the second bit PWA_D 2 of the second gate control signal in response to the first signal PWA_D and may generate a third bit PWA_D 3 of the second gate control signal. The fourth flip-flop F 40 may latch the third bit PWA_D 3 of the second gate control signal in response to the first signal PWA_D and may generate a fourth bit PWA_D 4 of the second gate control signal. The fifth flip-flop F 41 may latch the fourth bit PWA_D 4 of the second gate control signal in response to the first signal PWA_D and may generate a fifth bit PWA_D 5 of the second gate control signal. The sixth flip-flop F 42 may latch the fifth bit PWA_D 5 of the second gate control signal in response to the first signal PWA_D and may generate a sixth bit PWA_D 6 of the second gate control signal. The input terminal of the first flip-flop F 37 may be electrically connected to an output terminal of the sixth flip-flop F 42 .

FIG. 14 is a circuit diagram illustrating a first slave unit in the slave circuit of FIG. 11 according to at least one example embodiment.

Referring to FIG. 14 , the first slave unit 1950 A may include a first gating circuit F 43 , a second gating circuit 1952 , a third gating circuit 1953 and a fourth gating circuit F 44 . The second gating circuit 1952 and the third gating circuit 1953 may form a parallel gating circuit 1951 .

The first gating circuit F 43 may include a first flip-flop F 43 , may latch the first bank pre-charge control signal PWAPT_A in response to the first gate control signal PWA_CSL and may generate a third signal.

The second gating circuit 1952 may include a second flip-flop F 45 , a third flip-flop F 46 , a fourth flip-flop F 47 , a fifth flip-flop F 48 , a sixth flip-flop F 49 and a seventh flip-flop F 50 ; may latch the third signal in response to the second gate control signal which may have bits PWA_D 1 through PWA_D 6 ; and may generate the fourth signal having a plurality of bits.

The second flip-flop F 45 may latch the third signal in response to the first bit PWA_D 1 of the second gate control signal and may generate a first bit of the fourth signal. The third flip-flop F 46 may latch the third signal in response to the second bit PWA_D 2 of the second gate control signal and may generate a second bit of the fourth signal. The fourth flip-flop F 47 may latch the third signal in response to the third bit PWA_D 3 of the second gate control signal and may generate a third bit of the fourth signal. The fifth flip-flop F 48 may latch the third signal in response to the fourth bit PWA_D 4 of the second gate control signal and may generate a fourth bit of the fourth signal. The sixth flip-flop F 49 may latch the third signal in response to the fifth bit PWA_D 5 of the second gate control signal and may generate a fifth bit of the fourth signal. The seventh flip-flop F 50 may latch the third signal in response to the sixth bit PWA_D 6 of the second gate control signal and may generate a sixth bit of the fourth signal.

The third gating circuit 1953 may include an eighth flip-flop F 51 , a ninth flip-flop F 52 , a tenth flip-flop F 53 , an eleventh flip-flop F 54 , a twelfth flip-flop F 55 and a thirteenth flip-flop F 56 , and may latch the fourth signal in response to the third gate control signal having a plurality of bits and may generate a fifth signal.

The eighth flip-flop F 51 may latch the first bit of the fourth signal in response to a first bit PWA_DIS 1 of the third gate control signal and may generate the fifth signal. The ninth flip-flop F 52 may latch the second bit of the fourth signal in response to a second bit PWA_DIS 2 of the third gate control signal and may generate the fifth signal. The tenth flip-flop F 53 may latch the third bit of the fourth signal in response to a third bit PWA_DIS 3 of the third gate control signal and may generate the fifth signal. The eleventh flip-flop F 54 may latch the fourth bit of the fourth signal in response to a fourth bit PWA_DIS 4 of the third gate control signal and may generate the fifth signal. The twelfth flip-flop F 55 may latch the fifth bit of the fourth signal in response to a fifth bit PWA_DIS 5 of the third gate control signal and may generate the fifth signal. The thirteenth flip-flop F 56 may latch the sixth bit of the fourth signal in response to a sixth bit PWA_DIS 6 of the third gate control signal and may generate the fifth signal. Output terminals of the flip-flops F 51 through F 56 may be electrically connected to each other.

The fourth gating circuit F 44 may include a fourteenth flip-flop F 44 , may latch the fifth signal in response to the fourth gate control signal PWAP_EN and may generate a first gated bank pre-charge control signal PAPB_A.

The write recovery time control circuit 1900 illustrated in FIG. 11 through FIG. 14 may gate the bank pre-charge control signals PWAPT_A through PWAPT_H in a wave pipeline mode, based on the internal clock signal PCLK, the write command signal PWA, and the write recovery time control signal tWRi; may generate the gated bank pre-charge control signals; and may generate the pre-charge enable signal PREC_EN which may correspond to the bank pre-charge control signals PWAPT_A through PWAPT_H. The write recovery time control circuit 1900 of FIG. 11 may gate the bank pre-charge control signals in a wave pipeline mode using the first gate control signal PWA_CSL, the second gate control signal PWA_DL through PWA_D 6 , the third gate control signal PWA_DIS 1 through PWA_DIS 6 and the fourth gate control signal PWAP_EN. Each of the slave units 1950 A through 1950 H may include an input terminal formed by the one flip-flop F 43 and an output terminal formed by the one flip-flop F 44 .

Therefore, the bank pre-charge control signals PWAPT_A through PWAPT_H may be serially inputted to the slave units 1950 A through 1950 H, the bank pre-charge control signals PWAPT_A through PWAPT_H may be processed in parallel, and the bank pre-charge control signals PWAPT_A through PWAPT_H may be serially outputted. Therefore, the write recovery time control circuit illustrated in FIG. 11 may decrease the instability of a set-up time and a hold time of the bank pre-charge control signals PWAPT_A through PWAPT_H which may exist due to a skew between control signals, and may decrease a skew of the gated bank pre-charge control signals PAPB_A through PAPB_H.

Furthermore, a semiconductor memory device including a write recovery time control circuit according to at least one example embodiment may decrease a number of flip-flops required to control a write recovery time.

FIG. 15 is a timing diagram illustrating generation time points of a pre-charge command according to a write recovery time.

Referring to FIG. 15 , a data strobe signal DQS is generated synchronized with a clock signal CLK, after a write command is generated data DATA is generated at a rising edge and a falling edge of the data strobe signal DQS. The DATA includes odd-numbered data F 0 and F 1 and even-numbered data S 0 and S 1 . When a write recovery time tWR is 3 tCK, a pre-charge command PRE is generated at a time point of 3 tCK after a column selection signal CSL is enabled. When a write recovery time tWR is 4 tCK, a pre-charge command PRE is generated at a time point of 4 tCK after a column selection signal CSL is enabled.

FIG. 16 is a timing diagram illustrating an operation of the write recovery time control circuit of FIG. 11 .

Referring to FIG. 16 , write commands AWR, BWR, CWR, DWR, EWR, FWR, GWR and HWR may be generated per two clock cycles. The first gate control signal PWA_CSL may be generated in response to a clock signal CLK, a first signal PWA_D may be generated later than the first gate control signal PWA_CSL by 1 tCK, the second signal PWA_DIS may be generated later than the first signal PWA_D by 1 tCK. The bank address signals CBAW_A through CBAW_H may be generated synchronized with the first gate control signal PWA_CSL, and the auto pre-charge address signal CA 8 may be generated synchronized with the second signal PWA_DIS.

In the above, the write recovery time control circuit used in the semiconductor memory device formed by eight memory banks is illustrated. It will be easily understood, however, the present invention may be applied to a write recovery time control circuit in a semiconductor memory device having an arbitrary number of memory banks.

As described above, a semiconductor memory device including a write recovery time control circuit according to the present invention gates bank pre-charge control signals in a wave pipeline mode and may generate gated bank pre-charge control signals. Therefore, the semiconductor memory device including the write recovery time control circuit may decrease the number of flip-flops required to control a write recovery time and may increase a margin between input control signals and bank pre-charge control signals. The semiconductor memory device including the write recovery time control circuit may decrease power consumption and a size of a semiconductor integrated circuit. The memory device according to the present invention may accurately control a set-up time and a hold time of bank pre-charge control signals, and may decrease a skew of the bank pre-charge control signals.

Example embodiments having thus been described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the intended spirit and scope of example embodiments, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.