Manufacturing method for forming an integrated circuit device and corresponding integrated circuit device

The present invention relates to a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. Although in principle applicable to arbitrary integrated circuit devices, the following invention and the underlying problems will be explained with respect to integrated memory circuits in silicon technology.

Memory circuits of today usually comprise fuses in order provide redundancy elements. Said fuses are e.g. used in order to activate said redundancy elements, e.g. by irradiation of laser energy. Said fuses may be located in a process level which is below a contact pad metal level. Both for the fuse level and the contact pad metal level, contact holes are formed during the fabrication process.

It has been attempted to open the contact holes for the fuse window and the pad simultaneously. If the fuses are located in a metal level one layer below the pad metal level, such a simultaneous etching step would use the metal pad as an etch stop.

For pads made of copper-containing materials or copper, a simultaneous etching step may lead to corrosion of the exposed copper comprising pad. Additionally, copper damascene layers usually have a cap layer (top barrier) in order to prevent copper diffusion and achieve the electro-migration and stress migration performance needed for reliability purposes. E.g. silicon nitride or silicon carbide films are used as cap layer material. It would be desirable that the etching steps of opening the fuse-window and the contact pads could be made simultaneously without having the problem of pad corrosion.

Various aspects of the invention are listed in independent claims 1 , 14 , and 20 , respectively.

Further aspects are listed in the respective dependent claims.

In the Figures:

FIGS. 1A-F show schematic layouts for illustrating a manufacturing method for an integrated circuit device according to a first embodiment of the present invention; and

FIGS. 2A-D show schematic layouts for illustrating a manufacturing method for an integrated circuit device according to a second embodiment of the present invention.

In the Figures, identical reference signs denote equivalent or functionally equivalent components.

FIGS. 1A-E show schematic layouts for illustrating a manufacturing method for an integrated circuit device according to a first embodiment of the present invention.

In FIG. 1A reference sign 1 denotes an integrated circuit substrate, e.g. a wafer including a (not shown) integrated circuit. In a first metal level M 1 , fuses F 1 , F 2 , F 3 made of copper or a copper comprising material (e.g. AlCu), especially a copper rich material, are embedded in a first insulating layer I 1 , e.g. a silicon oxide layer. The first metal level M 1 may be formed by a damascene process. A copper damascene process is well known in the art and does need to be explained here in detail.

Said fuses F 1 , F 2 , F 3 are formed in a fuse region FU of said integrated circuit device. Above said first metal level M 1 an optional first cap layer C 1 made of silicon carbide or silicon nitride is deposited.

Above said first protective layer C 1 , a second metal level M 2 is formed in copper damascene technique. This second metal level M 2 comprises a contact pad P 1 in a pad area PA made of a copper-containing material or a copper comprising material, especially a copper rich material, embedded in a second insulating layer I 2 , e.g. another silicon oxide layer. The pad is connected to (not shown) wiring lines in the metal level M 1 and/or other levels.

Other metal levels may also be formed between the levels M 1 , M 2 .

After fabrication of the second metal level M 2 , a second cap layer C 2 , which may comprise silicon carbide or silicon nitride, is deposited on the second metal level M 2 . This leads to the process status shown in FIG. 1B .

Having regard to FIG. 1B , a first photo-resist mask is formed on the second cap layer C 2 such that it includes a window O in said fuse region FU. This window O is arranged such that the second cap layer C 2 can be removed from above the fuses F 1 , F 2 , F 3 in said fuse region FU.

After a corresponding etching step for removing the exposed part of the second cap layer C 2 in said window O, the first photo-resist mask PR 1 is removed and a first protective layer S 1 , which may comprise silicon oxide, and second protective layer S 2 , which may comprise silicon nitride, are deposited above the fuse region FU and the pad region PA. This leads to the process state shown in FIG. 1C .

As depicted in FIG. 1D , a second photo-resist mask PR 2 is formed on the second protective layer S 2 , such that it exhibits openings O 1 and O 2 . Opening O 1 defines a first contact hole CL 1 to be etched in the fuse area, whereas opening O 2 defines a second contact hole CL 2 to be etched in the pad area.

In order to form these contact holes CL 1 , CL 2 using the second photo-resist layer PR 2 as a mask, a selective etching of nitride and oxide with respect to the material of the second cap layer C 2 is performed.

Therefore, said etching step simultaneously etches the first contact hole CL 1 in said fuse region FU and the second contact hole CL 2 in said pad region PA. However, the etching in the pad region PA is stopped on said second cap layer C 2 and the etching in said fuse region FU proceeds to a deeper level and is stopped at a certain remaining depth of said second insulating layer I 2 made of silicon oxide. This can be achieved by controlling the etching time. The remaining depth of the second insulating layer I 2 in said first contact hole CL 1 is determined in accordance with the irradiation procedure to break the fuses F 1 , F 2 , F 3 .

Finally, as depicted in FIG. 1E , a further etch step is performed in order to at least partially remove the second cap layer C 2 from said second contact hole CL 2 thus exposing the contact pad P 1 in said pad region PA.

As becomes clear from the above description, the first embodiment involves an etch step to open the first contact hole CL 1 in the fuse area FU which is seld aligned to the second cap layer C 2 . At the same time, protection of the contact pad P 1 made of copper-containing material is assured by the cap layer C 2 .

Optionally, as depicted in FIG. 1F , a third cap layer C 3 , e.g. made of CuWP or NiPdAu, can be selectively formed on the contact pad P 1 .

FIGS. 2A-D show schematic layouts for illustrating a manufacturing method for an integrated circuit device according to a second embodiment of the present invention.

Having regard to FIG. 2A , the second embodiment starts after the formation of the second metal level M 2 . Here, the second cap layer C 2 ′, e.g. made of CuWP or NiPdAu, is not deposited on the entire structure, but selectively formed exclusively on the contact pad P 1 made of a copper-containing material or a copper comprising material, especially a copper rich material.

As shown in FIG. 2B , the first protective layer S 1 , which may comprise silicon oxide, and the second protective layer S 2 , which may comprise silicon nitride, are formed on the entire structure in the fuse area FU and pad area PA.

As depicted in FIG. 2C , the second photo-resist layer PR 2 having the openings O 1 , O 2 is then formed on the second protective layer S 2 . As mentioned above, opening O 1 corresponds to the first contact hole CL 1 in the fuse area FU and opening O 2 corresponds to the second contact hole CL 2 in the pad area PA.

The etching of the first and second contact holes CL 1 , CI 2 is simultaneously performed like in the first embodiment and particular stops on the second cap layer C 2 ′ arranged on the contact pad P 1 in the pad region PA. In the fuse region FU, the etching proceeds to the above-mentioned desired remaining depth of the second insulating layer I 2 above said fuses F 1 , F 2 , F 3 .

In contrast to the first embodiment, the second cap layer C 2 ′, is conductive. Therefore, the selectively formed second cap layer C 2 ′ may be used as protection layer during wafer testing. On the other hand, the second cap layer C 2 ′ may also be removed or partially removed from the second contact hole CL 2 , as depicted in FIG. 2D .

If the second cap layer C 2 ′ is left on the contact pad P 1 , it may still be intact after wafer probing and provide oxidation/corrosion protection of the contact pad P 1 until packaging. Whether this is the case, depends on material properties and layer thickness of the cap layer and process parameters during wafer testing. In case that the second cap layer C 2 ′ is retained during wafer testing, an additional needle with self-cleaning effect is expected.

Since the material of the second cap layer C 2 ′ is conductive, capacitive coupling between neighbouring metal lines is reduced, because standard dielectric cap materials such as silicon nitride or silicon carbide have higher dielectric constants compared to said cap layer material.

Both the first and second embodiments allow simultaneous etching of the contact holes for the fuse windows and pads which results in process simplification.

Although the present invention has been described with reference to specific embodiments, it is not limited thereto, but can be modified in various manners which are obvious for a person skilled in the art. Thus, it is intended that the present invention is only limited by the scope of the claims attached herewith.

In particular, the present invention is not limited to the material combinations referred to in the above embodiments. Moreover, the invention is applicable for any kind of integrated circuit devices that use fuses and contact pads.