High CMR amplifier topology

1. Field of the Invention

This invention relates generally to operational amplifiers, and, more particularly, to means for improving the common mode (CMR) and power supply (PSR) rejection characteristics of such amplifiers.

2. Description of the Related Art

Operational amplifiers typically include an input stage built around a differential transistor pair biased with a tail current. The tail current, as well as other input stage bias currents, are typically provided with respective transistors, each of which is controlled with a drive voltage provided by a bias generator circuit.

However, the output impedances of the bias current transistors may not be particularly high. As such, variations in the amplifier's supply voltage and in the input common-mode voltage can cause the bias currents to vary, which serves to degrade the amplifier's CMR and PSR characteristics.

One method by which CMR and PSR can be improved is by connecting a cascode transistor or an output impedance boost amplifier in series with the bias current transistors; cascode transistors can also be added within the bias generator and/or the input stage. However, these added components require additional headroom, thereby increasing the amplifier's minimum supply voltage.

Many other biasing methods are known; several are described, for example, in “Analysis and Design of Analog Integrated Circuits”; Gray and Meyer, 3 rd ed., pp. 310-311, 322-333, 422. However, most of these methods also exhibit less than ideal CMR/PSR characteristics, or require a considerable amount of headroom.

An amplifier topology is presented which overcomes the problems noted above, providing good CMR and PSR characteristics without requiring excessive headroom.

The present amplifier includes an input stage comprising first and second transistors arranged as a differential pair; the pair is biased with a tail current and conducts respective output currents in response to a differential input signal. The input stage includes bias current sources which provide respective bias currents for the input stage in response to a drive voltage, with one of the bias currents being the tail current. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current I sum .

The amplifier also includes a feedback loop. The loop includes a bias generator circuit which is connected to receive I sum , and is arranged to provide the drive voltage to the bias current sources such that I sum is maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.

FIG. 1 is a schematic diagram illustrating the principles of a high CMR operational amplifier per one possible embodiment of the present invention.

FIG. 2 is a schematic diagram of another embodiment of a high CMR operational amplifier per the present invention.

The present amplifier topology includes an input stage biasing means which stabilizes the input stage bias currents by incorporating them into the bias generator through the use of a feedback loop, thereby improving the stage's CMR and PSR characteristics.

FIG. 1 is a schematic diagram of an operational amplifier input stage which illustrates the basic principles of the invention. The input stage includes first and second transistors MP 1 and MP 2 connected as a differential pair 10 . A current source 12 provides a tail current I tail to pair 10 in response to a drive voltage 14 ; current source 12 is typically implemented with a p-type transistor such as the PMOS FET shown in FIG. 1 , though any circuit arrangement which provides an output current in response to a drive voltage could be used. Pair 10 is arranged to receive a differential input signal at respective inputs 16 , 18 , and to conduct respective output currents I MP1 , I MP2 in response.

The amplifier is connected between a supply voltage (VCC) and a circuit common point (GND) (which is typically at ground potential but may also may be non-zero). The present input stage topology includes a summing node 20 at which most or all of the input stage bias currents are summed after flowing through the input stage; summing node 20 is required to be at a different potential than the GND node. In the exemplary embodiment shown in FIG. 1 , differential pair output currents I MP1 , I MP2 drive an active load 22 , here comprising a current mirror. The current mirror is referred to summing node 20 , such that all of the input stage bias currents—which in this example consists solely of I tail —are returned to node 20 after flowing through the input stage. The resulting current at summing node 20 is referred to herein as I sum .

The amplifier also includes a feedback loop; in this example, the loop comprises a bias generator circuit 23 arranged to receive I sum , and to provide drive voltage 14 to the input stage bias current source ( 12 ) such that I sum is maintained approximately constant; bias generator circuit 23 may comprise, for example, a single or multi-stage amplifier with an offset voltage. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

The feedback loop preferably operates by providing a fixed voltage across a resistance which is connected in series between I sum and GND, thereby maintaining I sum approximately constant. In the example shown in FIG. 1 , resistance R is connected in series with I sum such that it conducts I sum to GND. A fixed voltage is provided across resistance R by means of two transistors conducting fixed currents, which may be equal or unequal. In the exemplary embodiment shown, first and second fixed currents I 1 and I 2 are provided to transistors Q 1 and Q 2 , with resistance R connected between their respective bases, as well as between I sum and GND. Here, I 1 and I 2 are provided by the means shown; note that there are many other ways in which fixed currents could be generated.

Q 1 and Q 2 are connected such that Q 1 conducts I 1 and Q 2 conducts I 2 . Q 1 and Q 2 have emitter areas x and n*x, respectively. When so arranged, the current I R through resistance R is given by:

I R = V ⁢ ⁢ t R ⁢ ln ⁡ ( I ⁢ ⁢ 1 I ⁢ ⁢ 2 ⁢ n ) ,

where Vt is the thermal voltage. The voltage V R across R is then given by I R *R. To ensure that a non-zero voltage is applied across R, bias generator circuit 23 is arranged such that

( I ⁢ ⁢ 1 I ⁢ ⁢ 2 ⁢ n ) > 0.

Since I 1 and I 2 are fixed, V R will also be fixed. In this way I R , and thereby I sum , is maintained approximately constant and independent of input common-mode voltage or supply voltage, thereby improving the amplifier's CMR and PSR characteristics.

When the bias generator is arranged as shown in FIG. 1 , it is preferably arranged such that I 1 ≈I 2 and n>1. For example, if I 1 =I 2 and n=8, I R is given by:

I R = V ⁢ ⁢ t R ⁢ ln ⁡ ( 8 ) ≈ 54 ⁢ mv R .

Resistance R can thus be selected to provide a desired value for I R , and thus for I sum .

Note that it is not required that I 1 =I 2 or that n>1. To provide a fixed voltage across R, it is only required that

( I ⁢ ⁢ 1 I ⁢ ⁢ 2 ⁢ n )

be greater than zero. Also note that, though transistors Q 1 and Q 2 are shown as bipolar transistors, FETs could also be used. Similarly, though MP 1 , MP 2 , current source 12 and active load 22 are shown implemented with FETs, bipolar transistors could also be used.

The feedback loop as implemented in FIG. 1 operates as follows: assume that the voltage applied to differential inputs 16 and 18 falls, causing MP 1 and MP 2 to pull down on their common source node. This increases the voltage across current source 12 , causing the current source to provide the increased current demanded by MP 1 and MP 2 . This increases I sum , which is fed back to resistance R causing I R and the voltage V R across R to increase, thereby raising the voltage at the base of Q 2 . Q 2 acts as a voltage follower, so that an increase at its base results in an increase at its emitter; this increase decreases the current in FET 32 . As a result, drive voltage 14 increases, thereby causing the current from current source 12 —i.e., I tail —to decrease, thereby stabilizing the input stage's bias currents. The gain of the loop is given by g m12 *R*g mQ2(eff) *r out , where g m12 is the transconductance of current source 12 , g mQ2(eff) is the effective transconductance of Q 2 , and r out is the output resistance of node 14 .

Another possible embodiment of an operational amplifier input stage per the present invention is shown in FIG. 2 . Here, bias generator 23 includes an additional level of cascode transistors to better isolate the generator from power supply variations. The amplifier also includes a second stage 40 , to provide additional gain. The second stage is driven by a drive signal 42 , the voltage of which decreases when I sum increases, and vice versa. Drive signal 42 drives an NMOS FET 44 , the drain of which provides drive voltage 14 . FET 44 is biased such that, when I sum increases, FET 44 conducts less, causing drive voltage 14 to increase and I tail to fall, thereby stabilizing the input stage's bias currents.

In addition to driving the current source ( 12 ) which provides tail current to MP 1 and MP 2 , drive voltage 14 can be used to drive additional input stage bias current sources, such as PMOS FETs 46 and 48 , which bias additional input stage circuits ( 50 , 52 ). To ensure that all the input stage bias currents are stabilized, the input stage should be arranged so that all of its bias currents are returned to summing node 20 and to resistance R, as shown in FIG. 2 .

Some prior art bias generators also employ a fixed voltage across a resistance to generate bias currents. However, these schemes required a relatively large resistance to develop a voltage large enough to generate adequate bias currents. The present invention mitigates this problem by essentially recycling the input stage bias currents via the feedback loop. With this additional current (I sum ) contributing to the voltage developed across R, its resistance value can be much smaller than was previously needed. This is desirable, as a smaller resistance requires less die area.

Note that the invention does not require the use of a bias generator circuit implemented as shown in FIGS. 1 and 2 . There are many other ways in which the bias generator could be implemented, as well as other ways in which a fixed voltage could be developed across a resistance.

Also note that, though the input stage is shown driving a current mirror used as an active load 22 in FIGS. 1 and 2 , this is not required. However, a current mirror is preferred to avoid any other errors that might arise with other types of loads, such as a folded cascode.

The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.