Thermal shunt for active devices on silicon-on-insulator wafers

Embodiments of the present invention are directed to heat management for silicon-on-insulator wafers and, more particularly, to thermal shunts compatible with hybrid silicon lasers.

Hybrid silicon laser have been developed that can produce terabit-level optical computer data pipes for high-performance computing applications. Using standard silicon manufacturing processes, the light-emitting properties of Indium Phosphide (InP) may be combined with the light-routing capabilities of silicon into a single hybrid chip. When voltage is applied, light generated in the InP enters the silicon waveguide to create a continuous laser beam that can be used to drive other silicon photonic devices.

Generally, silicon-on-insulator (SOI) devices produce heat when operating which should be managed. FIG. 1 shows a simple diagram of a typical SIO wafer. Silicon-on-insulator wafers may include a basic three layer structure. The top silicon epitaxial layer acts as a waveguide 100 , with the SiO 2 buried oxide layer 102 acting as a lower cladding confining the optical mode and stopping it leaking into the lower silicon substrate 104 . Typical thicknesses for this buried oxide layer 102 is 0.35 μm for waveguides taller than 2.5 μm and 1 μm for waveguides shorter than 1.5 μm in height.

For optical devices that generate heat when they operate, e.g. hybrid lasers or amplifiers, the thermal resistance between the heat source and heat sink is a key device parameter as it dictates the actual working temperature of the active area of the device. Typically for devices built on SOI the heat sink is placed underneath the silicon substrate 104 and typically is a thermoelectric cooler (TEC) device (not shown). For small waveguides (<1.5 μm) that use this thermal architecture, the SiO 2 buried oxide layer is the dominant source of thermal resistance (compare the thermal conductivity of SiO 2 (1.1-1.4 W/m.K) to that of Silicon (130 W/m.K)).

FIG. 2A shows a typical cross-section of a hybrid laser structure. As above, it may include an SOI structure comprising a silicon epitaxial layer that as a waveguide 200 , with the SiO 2 buried oxide layer 202 acting as a lower cladding confining the optical mode and stopping it leaking into the lower silicon substrate 204 . The laser may comprise a InP p-cladding 208 , an active region 210 , an InP—H+ implant region 212 over a InGaAsP n-contact layer 214 and an Au contact 216 .

FIG. 2B shows a simulation of the temperature profile in this same device when 1.5 W of electrical power is dissipated. Current in the device flows from the p-contact, through the p-InP cladding layer 208 to the active region 210 , then through the n-contact layer 210 to the n-metal. As can be seen in FIG. 2B significant device heating occurs in the active region of the laser. This leads to degraded device performance, such as reduced output power and increased threshold currents. The thermal impedance of this device is about 44.3 0C/W

The foregoing and a better understanding of the present invention may become apparent from the following detailed description of arrangements and example embodiments and the claims when read in connection with the accompanying drawings, all forming a part of the disclosure of this invention. While the foregoing and following written and illustrated disclosure focuses on disclosing arrangements and example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and the invention is not limited thereto.

FIG. 1 is a diagram of a simple silicon on insulator (SOI) wafer;

FIG. 2A is a diagram of a cross-section of a hybrid laser on an SOI wafer;

FIG. 2B shows a simulation of the temperature profile of the device shown in FIG. 2A when about 1.5 W of electrical power is dissipated;

FIGS. 3A and 3B are a cross sectional side view and a top view, respectively, of an SOI wafer having a thermal shunt according to one embodiment of the invention;

FIG. 4A is a diagram of a cross-section of a hybrid laser on an SOI wafer including thermal shunts according to one embodiment of the invention; and

FIG. 4B shows a simulation of the temperature profile of the device shown in FIG. 4A when about 1.5 W of electrical power is dissipated

Described is a thermal shunt compatible with SOI devices, including hybrid silicon lasers, which allows the thermal resistance of the laser structure to be reduced from about 44 C/W (current value without thermal shunt) to as low as about 18.6 C/W. Reducing the devices' thermal resistance is desirable for obtaining both high optical output power and high temperature laser sources on silicon.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIGS. 3A and 3B shows a simplified view side view and top view, respectively, of an SOI wafer according to one embodiment of the invention. The wafer may include an SiO 2 structure comprising a silicon epitaxial layer that as a waveguide 300 , with the SiO 2 buried oxide layer 302 acting as a lower cladding confining the optical mode and stopping it leaking into the lower silicon substrate 304 . In addition, a via 306 may be etched through the buried oxide layer 302 to the silicon substrate 304 adjacent to the waveguide 300 and filling it with a high thermal conductance material to provide a thermal shunt 308 reduce the thermal resistance of an optoelectronic the device 310 .

Examples of materials that can be used to provide this thermal shunt 308 are poly, amorphous or crystalline silicon, almost any metal, for example, aluminum, copper or other high thermal conductivity materials.

FIG. 4A shows a cross-section of a hybrid laser structure with thermal shunts according to one embodiment of the invention. It may include an SOI structure comprising a silicon epitaxial layer that as a waveguide 400 , with the SiO 2 buried oxide layer 402 acting as a lower cladding confining the optical mode and stopping it leaking into the lower silicon substrate 404 . The laser may comprise a InP p-cladding 408 , an active region 410 , an InP—H+ implant region 412 and an Au contact 416 .

The structure further may include two types of thermal shunts. The first thermal shunt employed involves using p-metal contact layer 420 and n-metal contact layer 422 to conduct heat away from the active region 410 and into the silicon substrate 404 .

The second type of thermal shunt involves etching a via and backfilling a portion of the silicon wafer with a heat conductive material. Here poly-silicon has been used for the backfill material to form a poly-Si thermal shunt 424 . As noted above examples of materials that can be used to provide this thermal shunt 424 may include poly, amorphous or crystalline silicon, almost any metal, for example, aluminum, copper or other high thermal conductivity materials.

FIG. 4B shows the resultant temperature distribution with both of these types of thermal shunts included in the device. The combination of both the Poly-Si shunt 423 and p/n metal shunts, 420 and 422 reduces the operating temperature of the laser for 1.45 W of dissipated electrical power by greater than a factor of two. The maximum temperature rise in the structure is now about 26.9 degrees C. which gives a thermal impedance of about 18.6 0C/W.

Various electrically driven lasers and flip chipped lasers on silicon-on-insulator substrates show similar temperature related limitations. The thermal shunt described herein may lower the intrinsic thermal resistance of such devices and can be used in conjunction with other thermal management schemes.

The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.