Phase-shifted bridge with auxiliary circuit to maintain zero-voltage-switching

The phase-shifted resonant bridge has become a mainstay in the dc-to-dc power converter field, because it can provide low switching losses by virtue of zero-voltage switching (ZVS) at constant switching frequency. The low losses are very desirable, in that they allow the switching frequency to be high without undesirable heating of the switches. The high switching frequencies which ZVS allows in turn allows power converters to be made with physically small reactors such as capacitors and inductors.

FIG. 1 is a simplified schematic diagram of a dc-to-dc switching converter, similar to that described in “ a 1 kW 500 kHz Front - End Converter for a Distributed Power Supply System ,” by Mweene et al, published in the IEEE Transactions on Power Electronics, Vol 6, No 3, July 1991. In FIG. 1 , a first source of direct energizing voltage (or electrical potential) is illustrated by a conventional battery symbol and is designated 12 . Direct energizing voltage is often referred to as direct current (dc). The dc voltage of source 12 is designated as an input voltage or Vi. Input voltage Vi is applied as +Ed to a first bus 14 relative to RTN, the second bus 16 . A first inverter switching leg is designated A and includes first and second controllable switching devices, illustrated as field-effect transistors Q 1 and Q 2 , respectively. A second inverter switching leg is designated B and includes third and fourth controllable switching devices, illustrated as field-effect transistors Q 3 and Q 4 , respectively. The salient characteristics of the controllable switching devices is that each includes a controlled current path, which in the case of a FET is the drain-to-source path, and a control electrode, which is the gate electrode. Thus, FET Q 1 is marked with the letters s, d and g to represent the source, drain, and gate electrodes. The other FETs are similarly marked. In FIG. 1 , leg A is illustrated as including the “serial” or “series” combination of the drain-to-source current paths of FETs Q 1 and Q 2 . Those skilled in the art will recognize that control of the gates of the FETs may result in lack of simultaneous current flow through both current paths, but for purposes of explanation the “serial” connection as illustrated in FIG. 1 will be understood. Leg A is illustrated as being connected “between” the buses 14 and 16 . Those skilled in the art will recognize that the term “between” as used in electrical descriptions differs from the general physical meaning, in that the connection of leg A “between” buses 14 and 16 means that the legs are electrically connected to receive electric energy therefrom, not that they are physically situated between the buses. Similarly, leg B is coupled “between” buses 14 and 16 . The connection of the two legs defines a “bridge” circuit designated 11 .

In normal operation of a dc-to-dc converter such as that of FIG. 1 , square-wave gate control signals are generated, as by a control block 18 , and applied to the gates of switches Q 1 , Q 2 , Q 3 , and Q 4 with phases selected, generally speaking, to turn ON or render conductive the controlled current paths of diagonally opposite switches of the bridge circuit 11 . Thus, for example, switches Q 1 and Q 4 are rendered conductive while switches Q 2 and Q 3 are rendered nonconductive, and shortly thereafter switches Q 2 and Q 3 are rendered conductive while switches Q 1 and Q 4 are rendered nonconductive. This has the effect of alternately connecting to bus 14 and to bus 16 the A leg “tap point” At, which lies “between” switches Q 1 and Q 2 , while simultaneously connecting to bus 14 and to bus 16 , respectively, the B leg tap point Bt. This, in turn, causes tap points At and Bt to alternate, at the switching frequency, between the +Ed bus voltage and the -RTN bus voltage. The alternation of the voltages appearing at tap points At and Bt effectively produces an alternating voltage “between” the tap points.

The alternating voltage appearing between tap points At and Bt in FIG. 1 is applied to the primary winding Tip of a transformer T 1 . More particularly, tap point At is connected by way of a transformer primary winding connection point or terminal T 1 p 1 . Similarly, tap point Bt is connected to a terminal by way of a transformer primary winding connection point or terminal T 1 p 2 . As illustrated, an inductance designated Lt is connected between terminal T 1 p 1 . Inductance Lt does not necessarily represent a discrete inductive element, but rather can represent, at least in part, the leakage inductance of transformer T 1 . Similarly, an inductance Lm is illustrated as being coupled “across” or in parallel with terminals T 1 p 1 and T 1 p 2 . Inductance Lm represents at least the magnetizing inductance of transformer T 1 .

When an alternating voltage is applied from tap points At and Bt to the primary winding of transformer T 1 , an alternating voltage is induced or produced across secondary winding T 1 s . The alternating voltage appearing across the output or secondary winding terminals of transformer T 1 is applied to a full-wave bridge rectifier designated generally as 30 , which produces pulsating direct voltage on a pair of buses 31 , 33 . The pulsating direct voltage is applied by way of an output filter inductor Lo and “across” an output filter capacitor Co. Filter inductor Lo and filter capacitor Co filter ripple, in known fashion, to produce generally ripple-free direct output direct voltage Vo.

The dc-to-dc converter 10 of FIG. 1 thus receives direct voltage from a source 12 , converts the direct voltage to alternating voltage in the bridge 11 , and converts the alternating voltage to a secondary alternating voltage by way of transformer T 1 . The magnitude of the secondary alternating voltage is be selected by the primary-to-secondary winding or turns ratio of transformer T 1 , as known in the art. The secondary alternating voltage at the secondary winding of transformer T 1 is rectified and filtered to produce an output direct voltage Vo. The dc-to-dc converter 10 thus provides, by virtue of interwinding insulation of transformer T 1 , electrical isolation between the source of direct voltage 12 and the output direct voltage Vo. It also allows the output voltage Vo to be selected to be different from (either greater than or less than) the source voltage.

Those skilled in the art know that control of the relative phases of the control signals applied to the various controllable switches of dc-to-dc converter 10 of FIG. 1 allows the voltage generated between tap points At and Bt to be varied. This variation as a function of phase is often used as part of a feedback control system for controlling the output direct voltage Vo.

It is desirable to cause the controllable switches of the dc-to-dc converter circuit of FIG. 1 to “soft switch” or to switch from the conductive state to the nonconductive state such that, during the switching transient, high voltage and current are not simultaneously applied to the switching device. Soft switching is described generally in U.S. Pat. No. 4,864,479, issued Sep. 5, 1989 in the name of Steigerwald et al. In the arrangement of FIG. 1 , the presence of transformer leakage inductance Lt aids in causing current circulation which tends to promote soft switching. Mweene et al. describe switching converter operation as phase-shifted PWM, in which either the two upper or two lower controllable switches are left conductive or ON during the free-wheeling period, so that the load and magnetizing currents can continue to flow in the primary winding Tip. The Mweene et al. switching operation is described in conjunction with the amplitude-time waveforms of FIGS. 2A , 2 B, 2 C, 2 D, 2 E, 2 F, and 2 H. FIGS. 2A and 2B illustrate the voltages at tap points At and Bt, respectively, of FIG. 1 , for approximately a 70% duty ratio or cycle, as periodically taking on the value of +Vin (corresponding to +Ed) or zero (corresponding to -RTN).

Some periods exist during which both tap points At and Bt are at the same voltage, both +Ed and zero (corresponding to -RTN). FIG. 2C plots the voltage V AB (or ν A -ν B ) “between” nodes or taps At and Bt, which energizes the primary winding of the transformer T 1 . FIG. 2D plots the pulsating direct voltage VX, which appears at the rectifier bridge output point X (relative to the negative terminal of output capacitor Co) of FIG. 1 as a result of the application of V AB to the transformer T 1 . FIG. 2E plots the magnetizing current I M of transformer T 1 . The magnetizing current increases (becomes more positive) substantially linearly during those intervals in which V AB is positive, remains substantially constant when V AB is zero, and decreases (becomes more negative) during those intervals in which V AB takes on a negative value. FIG. 2F plots the primary winding current IP of transformer T 1 . FIG. 2G plots as a solid line the gate-to-source voltage of controllable switch Q 1 , and as a dotted line the gate-to-source voltage of controllable switch Q 2 . FIG. 2H plots as a solid line the gate-to-source voltage of controllable switch Q 4 , and as a dotted line the gate-to-source voltage of controllable switch Q 3 .

As described by Mweene et al., zero-voltage switching results from operation in which, if Q 1 and Q 4 are ON (the controllable current paths are conductive), and then Q 1 is turned OFF (controllable current path rendered nonconductive), the load and magnetizing current (referred to the transformer primary and together designated Ip) that had been flowing in through the channel or controllable current path of Q 1 commutate to the parasitic capacitance of node or tap At. This capacitance is the parallel combination of output capacitances of switches Q 1 and Q 2 , of the transformer, and the reflected junction capacitances of two OFF-state rectifiers, namely rectifiers D 2 and D 3 . The voltage at node At falls as the current Ip discharges the combined capacitance until the capacitance voltage reaches the voltage of the bottom rail or bus 16 , at which time the capacitance voltage is clamped to the bottom rail 16 voltage by the inherent antiparallel diode of switch Q 2 . This transition is essentially lossless. At any time during the freewheeling period, switch Q 2 can be turned ON losslessly with zero volts across its controlled current path (the drain-to-source path), so long as the transition of Q 2 takes place after the turn-OFF of Q 1 , so as to avoid disrupting the lossless discharge of the capacitance of node At. At the end of the freewheeling interval, switch Q 4 is turned OFF, and current flowing in the primary winding Tip commutates to the parasitic capacitances of node Bt. As the voltage across the transformer becomes negative, the secondary-side currents commutate from the diode D 1 -D 4 path to the diode D 2 -D 3 path. For a period of time, all the diodes D 1 through D 4 are ON, and the voltage across the transformer secondary winding T 1 s is essentially zero. The voltage at node Bt, and therefore the transformer voltage, appear across the transformer leakage inductance Lt. The leakage inductance is illustrated as being on the primary side for ease of explanation.

As can be seen from the timing diagrams of FIGS. 2A through 2H , all four controllable switches Q 1 through Q 4 are driven with close to a 50% duty cycle or ratio. The drives for Q 1 and Q 2 are opposite square-waves, with sufficient dead time at each transition to permit completion of the lossless charging of node At. Similarly, the drives Q 3 and Q 4 are also opposite square-waves with dead times. Control of the duty cycle of the H-bridge 11 , the drives for the A and B legs are mutually shifted in time. During those intervals in which the two drives are 180° out-of-phase (meaning that Q 4 is ON whenever Q 1 is ON), the duty ratio is 100%. When the two drives are in-phase (Q 3 is ON whenever Q 1 is ON), the duty ratio is zero. Control of the relative drive phase of the legs allows control of the output direct voltage, and the abovementioned feedback control senses the output voltage and compares it with a reference to generate an error signal, which in turn is used to control the output voltage in a degenerative manner.

As described by Mweene et al., a resonance between the magnetizing inductance of the transformer T 1 and the node Bt capacitance takes place, and with proper selection of values can achieve peak voltages greater than the applied or bus voltage. When the voltage of the parasitic capacitance at node Bt exceeds the applied voltage Vi, the inherent antiparallel diode of switch Q 3 turns ON and clamps the resonant voltage until the leakage inductance current falls below zero. During this clamping interval, switch Q 3 can be turned ON losslessly.

Mweene et al. further indicate that the choice of the sum of the magnetizing and load current can affect the loss of the switching transitions. The magnetizing current always has the same value, which depends upon the applied voltage Vi and the amount of phase shift between legs A and B. The load current, however, can vary by large amounts, which can adversely affect the ability to zero-voltage switch (ZVS) at low or zero load currents. Zero-voltage switching is very desirable both to maintain low losses in the power switches and in the inverse-parallel diodes of FETs when used as power switches, and tends to reduce electromagnetic interference (EMI) attributable to the switching of significant currents. The power converter regulates the output voltage. At light load the power converter has a small duty ratio, so the magnetizing current is also small, thus there is not sufficient energy for zero-voltage switching under light load operation. The loss of zero-voltage switching leads to greatly increased switching loss, and a corresponding decrease in power converter efficiency. This loss of zero-voltage switching also is electrically noisy, and leads to EMI difficulties.

Improved or alternative dc-to-dc converters are desired.

A dc-to-dc converter according to an aspect of the invention comprises first and second controllable switches. Each controllable switch includes a controllable current path, (which can be the drain-to-source path in the case of a FET switch) and a control input port. The controllable current paths of the first and second controllable switches are connected as a first half-bridge with a first tap, a first connection node adjacent the first controllable switch and remote from the first tap and a second connection node adjacent the second controllable switch and remote from the first tap. The first connection node is connected to energizing voltage of a first polarity from a first terminal of a source of direct energizing voltage, and the second connection node is connected to energizing voltage of a second polarity from the source of direct energizing voltage. The dc-to-dc converter includes third and fourth controllable switches, each including a controllable current path and a control input port. The controllable current paths of the third and fourth controllable switches are connected as a second half-bridge with a second tap, a third connection node adjacent the third controllable switch and remote from the second tap and a fourth connection node adjacent the fourth controllable switch and remote from the second tap. The third connection node is connected to energizing voltage of the first polarity from a first terminal of the source of direct energizing voltage, and the fourth connection node is connected to energizing voltage of the second polarity from the source of direct energizing voltage. A phase-shift pulse-width-modulated controller is coupled to the control input port of the first, second, third, and fourth controllable switches, for switching the first, second, third, and fourth controllable switches so that a fixed-frequency alternating voltage appears between the first and second taps. An output transformer includes primary and secondary windings. At least one inductance, which may be inherent in the output transformer or associated with a discrete inductor, connects the primary winding to the first and second taps of the half-legs, so that the alternating voltage is applied to the primary winding of the output transformer. A full-wave rectifier is connected to the secondary winding, for rectifying secondary winding current flowing under the impetus of the alternating voltage. A filter is coupled to the full-wave rectifier for producing output direct voltage for application to a load. A second transformer includes first and second mutually coupled windings. The first mutually coupled winding defines first and second terminals and the second mutually coupled winding defines first and second terminals. The mutually coupled windings of the second transformer are poled or coupled so that a voltage applied to the first terminal of the first mutually coupled winding relative to the second terminal of the first mutually coupled winding induces a voltage of the same relative polarity at the second terminal of the second mutually coupled winding relative to the first terminal of the second mutually coupled winding. The first mutually coupled winding is serially connected with a capacitor to thereby define a first serial dc-blocked circuit defining first and second ends. The second coupled winding is serially connected with another capacitor and with a circulating current inductance to thereby define a second serial dc-blocked circuit including first and second ends. The second ends of the first and second serial dc-blocked circuits are coupled to one of the first and second terminals of the source of direct energizing voltage. The first end of the first serial dc-blocked circuits is connected to one of the first and second taps of the half-bridges, and the first end of the second serial dc-blocked circuits is connected to the other one of the first and second taps.

A particular embodiment of this converter further comprises first and second resistive voltage dividers, each defining a tap at which half the applied voltage appears. The first and second resistive voltage dividers are coupled across the first and second terminals of the source of direct energizing voltage. The tap of the first resistive voltage divider is connected to the first tap of the first half-bridge, and the tap of the second resistive voltage divider is connected to the second tap of the second half-bridge. A further embodiment comprises a first damping resistance serially coupled with the first serial dc-blocked circuit and a second damping resistance serially coupled with the second serial dc-blocked circuit, wherein at least a portion of the first and second damping resistance includes the internal resistance of the first and second mutually coupled windings.

A dc-to-dc converter according to another aspect of the invention comprises first and second controllable switches, each including a controllable current path and a control input port. The controllable current paths of the first and second controllable switches are connected as a half-bridge with a first tap. A first connection node lies adjacent the first controllable switch and remote from the first tap and a second connection node lies adjacent the second controllable switch and remote from the first tap. The first connection node is connected to energizing voltage of a first polarity from a first terminal of a source of direct energizing voltage, and the second connection node is connected to energizing voltage of a second polarity from the source of direct energizing voltage. The dc-to-dc converter also includes third and fourth controllable switches, each including a controllable current path and a control input port. The controllable current paths of the third and fourth controllable switches are connected as a half-bridge with a second tap. A third connection node lies adjacent the third controllable switch and remote from the second tap and a fourth connection node lies adjacent the fourth controllable switch and remote from the second tap. The third connection node is connected to energizing voltage of the first polarity from a second terminal of the source of direct energizing voltage, and the fourth connection node is connected to energizing voltage of the second polarity from the source of direct energizing voltage. A controller is coupled to the control input port of the first, second, third, and fourth controllable switches, for switching the first, second, third, and fourth controllable switches so that an alternating voltage appears between the first and second taps. An output transformer includes primary and secondary windings. At least one inductance connects the primary winding to the first and second taps, so that the alternating voltage is applied to the primary winding of the output transformer. A full-wave rectifier, which may be a bridge rectifier, is connected to the secondary winding, for rectifying current flowing in the secondary winding under the impetus of the alternating voltage. A filter is coupled to the full-wave rectifier for producing output direct voltage for application to a load. The filter may include the combination of an inductor and a capacitor. A second transformer includes first and second mutually coupled windings. The first coupled winding defines first and second terminals, and the second coupled winding defines first and second terminals. The coupled windings of the second transformer are coupled so that a voltage applied to the first terminal of the first coupled winding relative to the second terminal of the first coupled winding induces a voltage of the same relative polarity at the second terminal of the second coupled winding relative to the first terminal of the second coupled winding. The first coupled winding is serially connected with a capacitor to thereby define a first serial dc-blocked circuit defining first and second ends, and the second coupled winding is serially connected with another capacitor to thereby define a second serial dc-blocked circuit including first and second ends. The first end of the first serial dc-blocked circuit is coupled to the first tap and the second end of the first serial dc-blocked circuit is coupled to a selected terminal of the source of direct energizing voltage. The second serial dc-blocked circuit is coupled at the second end to the selected terminal of the source of direct energizing voltage. An inductor connects the first end of the second serial dc-blocked circuit to the second tap. In one embodiment of this aspect of the invention, the converter further includes first and second resistive voltage dividers, each defining a tap at which half the applied voltage appears. The first and second resistive voltage dividers are coupled across the first and second terminals of the source of direct energizing voltage. The tap of the first resistive voltage divider is connected to the first tap, and the tap of the second resistive voltage divider is connected to the second tap. In yet another embodiment of this aspect of the invention, the dc-to-dc converter further includes a first damping resistance serially coupled with the first serial dc-blocked circuit and a second damping resistance serially coupled with the second serial dc-blocked circuit, and the damping resistances may include the internal resistance of the first and second mutually coupled windings.

FIG. 1 is a simplified diagram in block and schematic form of a prior-art fixed- or constant-frequency dc-to-dc phase-shifted PWM switching converter;

FIGS. 2A , 2 B, 2 C, 2 D, 2 E, 2 F, 2 G, and 2 H are plots of voltages and currents associated with the converter of FIG. 1 ;

FIG. 3 is a simplified diagram in block and schematic form illustrating a dc-to-dc converter according to an aspect of the invention;

FIGS. 4A , 4 B, 4 C, and 4 D illustrate ideal voltages appearing in the arrangement of FIG. 3 during operation, and FIGS. 4E , 4 F, 4 G, and 4 H illustrate ideal currents; and

FIG. 5 is a graph that demonstrates the ZVS operating region of the auxiliary circuit.

The phase-shifted PWM dc-to-dc converter of FIG. 1 , and many other bridge-type dc-to-dc converters, has/have the disadvantage of tending to lose zero-voltage switching (ZVS) of the switches at reduced or zero load current. As known, this tends to decrease the efficiency of the conversion and undesirably causes heating of the switches. In the arrangement of FIG. 1 , the energy necessary for ZVS is stored in the leakage inductance Lt of the output transformer T 1 . The leakage inductance Lt is ultimately in series with the load (R L ) current. Consequently, the energy stored in the leakage inductance Lt is reduced at reduced load current, and in principle becomes zero at zero load current. Thus, the available ZVS energy is reduced at light load. ZVS switching can also use energy stored in the magnetizing inductance (not illustrated) of the output transformer T 1 . The magnetizing inductance current is in parallel with the load current, but this has the disadvantage that, as the duty cycle is reduced at light or no load, the magnetizing current is also reduced, as with the leakage inductance. Use of the magnetizing inductance to provide zero-voltage switching (ZVS) has the further disadvantage that the magnetizing current increases at heavy load as the duty cycle increases, thus placing additional thermal or power-handling stress on the power switches or FETs.

According to an aspect of the invention, a passive auxiliary circuit is provided that increases the effective magnetizing current as the duty cycle decreases. This auxiliary circuit can be used alone, or in conjunction with a properly dimensioned magnetizing inductance of the output transformer to maintain substantially constant effective magnetizing current over a range of duty cycles and loads. Similarly, the passive auxiliary circuit can be used without significant output transformer magnetizing current, and provide necessary energy for zero-voltage switching at light load and no load operation. This in turn means that ZVS can be maintained from no load to full load range of operation.

The dc-to-dc converter 100 of FIG. 3 is generally similar to that of FIG. 1 , but further includes a circulating current compensator circuit illustrated within dash lines 310 , and also further includes resistive voltage dividers 312 and 314 . Circulating current compensator 310 of FIG. 3 includes a second transformer T 2 with first and second windings T 2 1 and T 2 2 having the same number of turns, which is to say a turns ratio of unity. As suggested by the dot notation, the windings T 2 1 and T 2 2 are poled “oppositely,” although this depends in practice upon the winding connections. The dot-illustrated poling means that a positive voltage instantaneously applied to transformer terminal T 2 11 relative to bus 16 results in an induced negative voltage at terminal T 2 21 relative to bus 16 . Those skilled in the art will fully understand this polarization. Transformer winding T 2 1 is serially connected (for alternating currents) at a terminal T 2 12 with a dc blocking capacitor Cb 1 to thereby form a serial combination T 2 11 /Cb 1 which has end terminals T 2 11 and 301 . As illustrated in FIG. 3 , transformer terminal T 2 11 of one end of serial combination T 2 11 /Cb 1 is connected to tap point At of switch leg A, and the other end point of serial combination T 2 11 /Cb 1 , namely node 301 , is connected to a reference potential which is illustrated as being bus 16 , although it could as easily be bus 14 .

In FIG. 3 , the second winding T 2 2 of transformer T 2 of the circulating current compensator 310 includes terminals T 2 21 and T 2 22 . Transformer winding T 2 2 of transformer T 2 is serially coupled at terminal T 2 22 with a dc blocking capacitor Cb 2 , and is serially coupled at a terminal T 2 21 with an inductance designated Lcc. The inductance represented by Lcc may be provided by a discrete inductor, or by leakage inductance of transformer T 2 , or both. Thus, transformer winding T 2 2 , capacitor Cb 2 , and inductance Lcc are effectively in series for alternating currents. The end points of the serial combination of transformer winding T 2 2 , capacitor Cb 2 , and inductance Lcc are designated 302 and 303 , with 302 being adjacent capacitor Cb 2 and 303 being adjacent winding Lcc. End point 302 of the serial combination of transformer winding T 2 2 , capacitor Cb 2 , and inductance Lcc is connected to reference potential, which is illustrated as being bus 16 , although it could as easily be bus 14 . End point 303 of the serial combination of transformer winding T 2 2 , capacitor Cb 2 , and inductance Lcc is connected to leg B tap point Bt.

In operation of the arrangement of FIG. 3 , the two inverter legs A and B are operated at a constant frequency, 50% duty cycle, with leg B shifted in phase relative to leg A to achieve control of the output pulse width, which in turn controls the output voltage of the dc-to-dc converter 100 . This mode of operation is identical to the mode of operation of the Mweene et al. arrangement. As illustrated in FIG. 3 , the voltage at half-leg A tap point At relative to reference potential is applied to winding T 21 of transformer T 2 in series with the DC blocking capacitor Cb 1 , and is coupled to a point A′ out-of-phase (or in reverse phase), relative to reference potential, by transformer T 2 . Thus, the voltage at point A′ of FIG. 3 is ν A′ .

FIGS. 4A , 4 B, 4 C, and 4 D illustrate the ideal voltage ν A at tap At relative to reference potential, voltage at tap Bt relative to the reference potential, V A −ν B , and ν A′ −ν B , respectively. FIG. 4E illustrates the ideal current i Lcc , into both nodes At and Bt, FIG. 4F illustrates the magnetizing current i Lm in transformer T 1 , FIG. 4G represents the sum of currents i Lcc and i Lm , designated i Lcc +i Lm flowing into tap point or node Bt, and FIG. 4H represents the current i Lcc −i Lm , into node At. Phase angle Φ represents the phase angle between the voltages at half-leg tap points At and Bt. The phase angle is set by the controller 18 in the same manner as for the prior-art arrangement of FIG. 1 .

As can be seen from the plot of ν A of FIG. 4A , the voltage at leg A tap point At switches between values of zero (0) and +E d , which is the voltage of bus 14 . Similarly, the voltage ν B at leg B tap point Bt is illustrated in FIG. 4B , and also switches between values of zero (0) and +E d , although with a phase angle that differs by Φ from that of voltage ν A . FIG. 4C plots the difference voltage ν A −ν B . Difference voltage ν A −ν E takes on one three values: +E d , −E d , or zero. It should be noted from FIG. 3 that transformer T 2 of circulating current compensator 310 inverts the AC component of voltage ν A and applies it as ν A′ to point V′. FIG. 4D plots the voltage difference ν A′ −ν B , which represents the voltage applied across inductance L cc . Difference voltage ν A′ −ν B also takes on one of three values: +E d , −E d or zero.

As a result of the application of difference voltage ν A′ −ν B across inductance L cc , a trapezoidal current i Lcc with sloped sides flows in the inductance, which is represented by the plot of FIG. 4E . The maximum values of current i Lcc flowing in the inductance Lcc are ±I Lcc . FIG. 4F plots the trapezoidal, with sloped sides, magnetizing current i Lm of output transformer T 1 , which takes on maximum values of ±I LM . Both the current i Lcc of inductance L cc and the magnetizing current i LM of magnetizing inductance L M flow into node or tap point Bt. FIG. 4G plots the sum current i Lcc +i LM flowing into tap point Bt. The sum current i Lcc +i LM is a triangular wave that takes on maximum values of ±(I Lcc +i LM ). FIG. 4H plots the sum current i Lcc −i LM flowing into tap point At.

The output transformer T 1 of FIG. 3 receives alternating drive voltage from tap points At and Bt. When phase angle Φ is 0°, the duty cycle is 50%, and the frequency is constant, the dc-to-dc converter 310 of FIG. 3 produces or generates minimum output voltage, because ν A and ν B are in-phase, and the voltage difference ν A −ν B is zero. Thus, the primary winding of output transformer T 1 receives no applied energizing potential, and consequently produces no output or secondary voltage which might be rectified to produce output voltage Vo. When the phase angle Φ is 180°, the voltages ν A and ν B are out-of-phase, and the voltage difference ν A −ν B is maximum. The phase angle Φ is modified within the range of 0° and 180° to effectuate output voltage control. Those skilled in the art will recognize that corresponding ranges of phase other than from 0° and 180° will have the same effect.

In order to attain zero voltage switching (ZVS), sufficient energy must be stored and made available in order to charge and discharge the capacitances of the solid-state switches Q 1 , Q 2 , Q 3 , and Q 4 . In the prior-art arrangement of FIG. 1 , the load current flows through leakage inductance L t of output transformer T 1 . When the load current is high, the energy stored in leakage inductance L t is at a maximum, and ZVS can be accomplished. At or near minimum load, however, the current through leakage inductance L t is minimized or zero, with the result that little energy is available for ZVS, and the switching may become lossy.

By contrast, in the arrangement of FIG. 3 , the addition of the inverting transformer T 2 of circulating current compensator 310 maximizes ν A′ −ν B when the phase angle Φ is 0°, corresponding to zero output load current. The maximized value of ν A′ −ν B for a phase angle of 0°, in turn, applies maximum voltage or volt-seconds across inductance L cc , and the larger volt-seconds results in storage of maximum energy in inductance L cc during those intervals in which the load current is least. Consequently, during those times in which the energy storage in leakage inductance L t is least, the energy storage in circulating current compensator inductance L cc is maximized. Conversely, during those times in which the energy storage in leakage inductance L t is maximized at high load power, the energy storage in circulating current compensator inductance L cc is minimized. It is desirable that the energy storage in circulating current compensator inductance L cc is minimized at high load current, since at that time the energy storage in leakage inductance Lt is maximum, so that energy is available for ZVS from that source. At zero voltage across the load, when the voltages at tap points At and Bt are transitioning from zero volts to the dc bus or rail voltage together, there is a full square wave ν A′ −ν B across inductance L cc , giving maximum circulating current. In short, the circulating current attributable to the circulating current compensator 310 increases at small load duty cycles and decreases at large load duty cycles, which is exactly the desired effect.

It should be noted that the blocking capacitors Cb 1 , and Cb 2 “bias up” to the average voltages of nodes or tap points At and Bt, respectively, which should be Vi/2. To aid in biasing the tap points to the correct voltage, a first resistive voltage divider 312 , including equal-value resistors R 1 and R 3 , is coupled across buses 14 and 16 , with the tap point between the resistors connected to tap point At. Similarly, a second resistive voltage divider 314 , including equal-value resistors R 2 and R 4 , is coupled across buses 14 and 16 , with the tap point between the resistors connected to tap point Bt.

The analysis so far has assumed that the load current and the inductance L cc current both flow into node Bt. The transformer T 1 magnetization current L m can also be used to assist with the zero-voltage switching. The inductance circulating current compensator inductance L cc and the transformer T 1 magnetizing inductance L M can be considered or viewed as injecting a constant “effective” magnetizing current into nodes At and Bt, if the inductance value of L m and L cc are the same. Since magnetizing inductance L m and Lcc are both much larger than leakage inductance Lt, they are assumed to be constant during the resonant transitions.

As mentioned, the currents in both magnetizing inductance L m and in inductance L cc of FIG. 3 are trapezoidal with sloped sides. The peak current in L m increases with increasing duty cycle, and the peak current in L cc decreases with increasing duty cycle. These advantageously mutually compensate such that the effective magnetizing current can be maintained substantially constant over all duty cycles and loads, so that zero-voltage switching is maintained under all power converter load conditions, no-load to full load. This situation occurs when

L m = L cc = E d 4 ⁢ ⁢ f sw ⁢ I m ⁡ ( eff ) ( 1 )

where:

I m(eff) =IL ccpk =IL mpk =constant

For example, the inductances can be set to give the critical value of effective magnetizing current, in which case zero-voltage switching is maintained over all duty cycles and loads.

The effective magnetizing current ILm of transformer T 1 which is injected into nodes or tap points At and Et of FIG. 3 is in parallel with the current in leakage inductance Lt. Depending upon the magnitudes of current in Lt and also upon the amount of effective magnetizing current injected into node or tap point Bt, ZVS may or may not be achieved. FIG. 5 illustrates the ZVS regions as a function of load current. In FIG. 5 , the units of the abscissa are Io, the output load current referred to the primary winding of transformer T 1 . The units of the ordinate are I m , the effective magnetizing current of transformer T 1 . The plot of FIG. 5 is divided into three regions, the lowermost of which is designated as a “No ZVS region” 510 . The other two are the left-most region 512 and the last region is designated 516 . Region 512 is one in which the magnetizing current L m exceeds the leakage current through L t , I m >I o , and gives rise to commutation that takes place in two intervals (or topological modes). Region 516 is one in which the sum of the magnetizing current L m and the load current Io referred to the primary is given by

I M + I o > E d Z 0

where:

I M is the magnetizing current;

I o is the output or load current Io referred to the primary winding;

E d is the bus voltage; and

Z o is the square root of the leakage inductance divided by the capacitance of the switching device which is to be commutated.

Region 516 also corresponds with ZVS operation, and more particularly with one-stage ZVS commutation in which the commutation takes place in one transient interval (one topological mode). The junction of regions 510 , 512 , and 516 occurs at a “critical point,” at which ZVS is guaranteed under all load conditions. The critical point is defined by

I m = E d 2 ⁢ ⁢ Z 0 ( 2 )

where

Z 0 = L r 2 ⁢ ⁢ C j

where:

L r is the output transformer T 1 leakage inductance Lt, and Cj is the capacitance of a switch (e.g., Q 1 ) in parallel with any reflected output diode capacitance and any other parasitic capacitance (such as transformer-winding-to-ground capacitance); and

C j is the total capacitance across each power FET, including the FET output capacitance, C oss , diode junction capacitance, and any external capacitance.

While second transformer T 2 has been described as having the same number of turns on its primary and secondary windings, the turns ratio is not believed to be critical.

A dc-to-dc converter ( 100 ) according to an aspect of the invention comprises first (Q 1 ) and second (Q 2 ) controllable switches. Each controllable switch includes a controllable current path (drain-to-source) and a control input port (gate). The controllable current paths (drain-to-source) of the first (Q 1 ) and second (Q 2 ) controllable switches are connected as a half-bridge (A) with a first tap (At), a first connection node ( 13 ) adjacent the first controllable switch (Q 1 ) and remote from the first tap (At) and a second connection node ( 15 ) adjacent the second controllable switch (Q 2 ) and remote from the first tap (At). The first connection node ( 12 ) is connected to energizing voltage of a first polarity from a first (+) terminal of a source ( 12 ) of direct energizing voltage, and the second connection node ( 15 ) is connected to energizing voltage of a second polarity from the source ( 12 ) of direct energizing voltage. The dc-to-dc converter includes third (Q 3 ) and fourth (Q 4 ) controllable switches, each including a controllable current (drain-to-source) path and a control input port (gate). The controllable current (drain-to-source) paths of the third (Q 3 ) and fourth (Q 4 ) controllable switches are connected as a half-bridge (B) with a second tap (Bt), a third connection node ( 17 ) adjacent the third controllable switch (Q 3 ) and remote from the second tap (Bt) and a fourth connection node ( 19 ) adjacent the fourth controllable switch (Q 4 ) and remote from the second tap (Bt). The third connection node ( 17 ) is connected to energizing voltage of the first polarity from a first (+) terminal of the source ( 12 ) of direct energizing voltage, and the fourth connection node ( 18 ) is connected to energizing voltage of the second polarity from the source ( 12 ) of direct energizing voltage. A phase-shift pulse-width-modulated (PWM) controller ( 18 ) is coupled to the control input port (g) of the first (Q 1 ), second (Q 2 ), third (Q 3 ), and fourth (Q 4 ) controllable switches, for switching the first, second, third, and fourth controllable switches so that a fixed-frequency alternating voltage (V AB ) appears between the first (At) and second (Bt) taps. An output transformer (T 1 ) includes primary (T 1 p ) and secondary (T 1 s ) windings. At least one inductance (Lt), which may be inherent in the output transformer or part of a discrete inductor, connects the primary winding to the first (At) and second (Bt) taps, so that the alternating voltage (V AB ) is applied to the primary winding (T 1 p ) of the output transformer (T 1 ). A full-wave rectifier ( 30 ), which may be a bridge rectifier, current doubler, or voltage doubler, is connected to the secondary winding (T 1 s ), for rectifying secondary winding (T 1 s ) current flowing under the impetus of the alternating voltage (V AB ). A filter is coupled to the full-wave rectifier ( 30 ) for producing output direct voltage (Vo) for application to a load ( 32 ). The filter may include the serial combination of an inductor (Lo) and a capacitor (Co) across which the output direct voltage is generated. A second transformer (T 2 ) includes first (T 2 1 ) and second (T 2 2 ) mutually coupled windings. The first mutually coupled winding (T 2 1 ) defines first (T 2 11 ) and second terminals (T 2 12 ) and the second mutually coupled winding (T 2 2 ) defines first (T 2 21 ) and second (T 2 22 ) terminals. The mutually coupled windings of the second transformer (T 2 ) are poled or coupled so that a voltage applied to the first (T 2 11 ) terminal of the first mutually coupled winding (T 2 1 ) relative to the second (T 2 12 ) terminal of the first mutually coupled winding (T 2 1 ) induces a voltage of the same relative polarity at the second terminal (T 2 22 ) of the second mutually coupled winding (T 2 2 ) relative to the first terminal (T 2 21 ) of the second mutually coupled winding (T 2 2 ). The first mutually coupled winding (T 2 1 ) is serially connected with a capacitor (Cb 1 ) to thereby define a first serial dc-blocked circuit (T 2 1 , Cb 1 ) defining first (T 2 11 ) and second ( 301 ) ends. The second coupled winding (T 2 2 ) is serially connected with another capacitor (Cb 2 ) and with a circulating current inductance (Lcc) to thereby define a second serial dc-blocked circuit (T 2 2 , Cb 2 , L cc ) including first ( 303 ) and second ( 302 ) ends. The second ends ( 301 , 302 ) of the first and second serial dc-blocked circuits (T 2 1 , Cb 1 ; T 2 2 , Cb 2 , L cc ) are coupled to one of the first (+Ed) and second (-RTN) terminals of the source ( 12 ) of direct energizing voltage. The first end (T 2 11 ) of the first serial dc-blocked circuits (T 2 1 , Cb 1 ) is connected to one of the first (At) and second (Bt) taps, and the first end ( 303 ) of the second serial dc-blocked circuits (T 2 2 , Cb 2 , L cc ) is connected to the other one (Bt) of the first (At) and second (Bt) taps.

A particular embodiment of this converter further comprises first ( 312 ) and second ( 314 ) resistive voltage dividers, each defining a tap ( 312 t ; 314 t ) at which half the applied voltage appears. The first ( 312 ) and second ( 314 ) resistive voltage dividers are coupled across the first (+Ed) and second (-RTN) terminals of the source ( 12 ) of direct energizing voltage. The tap ( 312 t ) of the first resistive voltage divider ( 312 ) is connected to the first tap (At) of the first half-bridge (A), and the tap ( 314 t ) of the second resistive voltage divider ( 312 ) is connected to the second tap (Bt) of the second half-bridge (B). A further embodiment comprises a first damping resistance serially coupled with the first serial dc-blocked circuit (T 2 1 , Cb 1 ) and a second damping resistance serially coupled with the second serial dc-blocked circuit (T 2 2 , Cb 2 ), wherein at least a portion of the first and second damping resistance includes the internal resistance of the first (T 2 1 ) and second (T 2 2 ) mutually coupled windings.

A particular embodiment of this converter further comprises first ( 312 ) and second ( 314 ) resistive voltage dividers, each defining a tap ( 312 t ; 314 t ) at which half the applied voltage appears. The first ( 312 ) and second ( 314 ) resistive voltage dividers are coupled across the first (+) and second (−) terminals of the source ( 12 ) of direct energizing voltage. The tap ( 312 t ) of the first resistive voltage divider ( 312 ) is connected to the first tap (At) of the first half-bridge (A), and the tap ( 314 t ) of the second resistive voltage divider ( 312 ) is connected to the second tap (Bt) of the second half-bridge (B). A further embodiment comprises a first damping resistance serially coupled with the first serial dc-blocked circuit (T 2 1 , Cb 1 ) and a second damping resistance serially coupled with the second serial dc-blocked circuit (T 2 2 , Cb 2 ), wherein at least a portion of the first and second damping resistance includes the internal resistance of the first (T 2 1 ) and second (T 2 2 ) mutually coupled windings.

A dc-to-dc converter according to another aspect of the invention comprises first (Q 1 ) and second (Q 2 ) controllable switches, each including a controllable current path (drain-to-source) and a control input port (gate). The controllable current paths of the first (Q 1 ) and second (Q 2 ) controllable switches are connected as a half-bridge (A) with a first tap (At). A first connection node ( 15 ) lies adjacent the first controllable switch (Q 1 ) and remote from the first tap (At) and a second connection node ( 15 ) lies adjacent the second controllable switch and remote from the first tap (At). The first connection node ( 13 ) is connected ( 14 ) to energizing voltage of a first polarity from a first (+) terminal of a source ( 12 ) of direct energizing voltage, and the second connection node ( 15 ) is connected ( 16 ) to energizing voltage of a second polarity from the source ( 12 ) of direct energizing voltage. The dc-to-dc converter also includes third (Q 3 ) and fourth (Q 4 ) controllable switches, each including a controllable current path (drain-to-source) and a control input port (gate). The controllable current paths of the third (Q 3 ) and fourth (Q 4 ) controllable switches are connected as a half-bridge with a second tap (Bt). A third connection node ( 17 ) lies adjacent the third controllable switch (Q 3 ) and remote from the second tap (Bt) and a fourth connection node ( 19 ) lies adjacent the fourth controllable switch (Q 4 ) and remote from the second tap (Bt). The third connection node ( 17 ) is connected to energizing voltage of the first polarity from a second (+Ed) terminal of the source ( 12 ) of direct energizing voltage, and the fourth connection node ( 19 ) is connected to energizing voltage of the second polarity from the source ( 12 ) of direct energizing voltage. A controller ( 18 ) is coupled to the control input port (g) of the first (Q 1 ), second (Q 2 ), third (Q 3 ), and fourth (Q 4 ) controllable switches, for switching the first, second, third, and fourth controllable switches so that an alternating voltage appears between the first (At) and second (Bt) taps. An output transformer (T 1 ) includes primary (T 1 p ) and secondary (T 1 S) windings. At least one inductance (Lt) connects the primary winding (T 1 p ) to the first (At) and second (Bt) taps, so that the alternating voltage is applied to the primary winding (Tip) of the output transformer. A full-wave rectifier ( 30 ) is connected to the secondary winding (T 1 s ), for rectifying current flowing in the secondary winding (T 1 s ) under the impetus of the alternating voltage. A filter ( 390 ) is coupled to the full-wave bridge rectifier ( 30 ) for producing output direct voltage for application to a load ( 32 ). The filter ( 390 ) may include the combination of an inductor (Lo) and a capacitor (Co). A second transformer (T 2 ) includes first (T 2 1 ) and second (T 2 2 ) mutually coupled windings. The first coupled winding (T 2 1 ) defines first (T 2 11 ) and second terminals (T 2 12 ), and the second coupled winding (T 2 2 ) defines first (T 2 21 ) and second (T 2 22 ) terminals. The coupled windings (T 2 1 T 2 2 ) of the second transformer (T 2 ) are coupled so that a voltage applied to the first (T 2 11 ) terminal of the first coupled winding (T 2 1 ) relative to the second (T 2 12 ) terminal of the first coupled winding (T 2 1 ) induces a voltage of the same relative polarity at the second terminal (T 2 22 ) of the second coupled winding (T 2 2 ) relative to the first terminal (T 2 21 ) of the second coupled winding (T 2 2 ). The first coupled winding (T 2 1 ) is serially connected with a capacitor (Cb 1 ) to thereby define a first serial dc-blocked circuit (T 2 1 , Cb 1 ) defining first (T 2 11 ) and second ( 301 ) ends, and the second coupled winding (T 2 2 ) is serially connected with another capacitor (Cb 2 ) to thereby define a second serial dc-blocked circuit (T 2 2 , Cb 2 ) including first (T 2 21 ) and second ( 302 ) ends. The first end (T 2 11 ) of the first serial dc-blocked circuit (T 2 1 , Cb 1 ) is coupled to the first tap (At) and the second end ( 301 ) of the first serial dc-blocked circuit (T 2 1 , Cb 1 ) is coupled to a selected terminal (-RTN) of the source ( 12 ) of direct energizing voltage. The second serial dc-blocked circuit (T 2 2 , Cb 2 ) is coupled at the second end ( 302 ) to the selected terminal (RTN) of the source ( 12 ) of direct energizing voltage. An inductor (L cc ) connects the first end (T 2 21 ) of the second serial dc-blocked circuit (T 2 2 , Cb 2 ) to the second tap (Bt). In one embodiment of this aspect of the invention, the converter further includes first ( 312 ) and second ( 314 ) resistive voltage dividers, each defining a tap ( 312 t ; 314 t ) at which half the applied voltage appears. The first and second resistive voltage dividers are coupled across the first (+Ed) and second (-RTN) terminals of the source ( 12 ) of direct energizing voltage. The tap ( 312 t ) of the first resistive voltage divider ( 312 ) is connected to the first tap (At), and the tap ( 314 t ) of the second resistive voltage divider ( 314 ) is connected to the second tap (Bt). In yet another embodiment of this aspect of the invention, the dc-to-dc converter further includes a first damping resistance serially coupled with the first serial dc-blocked circuit (T 2 1 , Cb 1 ) and a second damping resistance serially coupled with the second serial dc-blocked circuit (T 2 2 , Cb 2 ), and the damping resistances may include the internal resistance of the first (T 2 1 ) and second (T 2 2 ) mutually coupled windings.