Voltage regulator module control circuit

1. Field of the Invention

The present invention relates to control circuits, and particularly to a voltage regulator module control circuit.

2. Description of Related Art

In order to deliver a highly accurate supply voltage to microprocessors, a dedicated DC/DC converter is usually placed in close physical and electrical proximity to the processor or other chip or module having such requirements. Such a converter is often provided in a modular form and is referred to as a voltage regulator module (VRM). Most common of the currently used VRM circuit topologies are multiphase (e.g. two or more phases) buck converters, the principal benefits of which are ripple voltage cancellation effect, efficiency, relatively small module size, and the ability to use relatively inexpensive components. More specifically, the ripple cancellation effect between the phases allows use of small inductances to improve transient response and minimization of output filter capacitance.

Use of more than two phases can interleave the conductor currents between the individual phase channels and thereby greatly reduce the total ripple currents flowing into the output capacitors. Such further reduction of ripple current by use of three or more phases allows use of even smaller inductors to improve transient response and allows for a small capacitance to meet transient requirements. Reduced ripple voltage also allows for more voltage deviation during transients because the ripple voltage will consume less of the voltage tolerance budget.

However, a three phase VRM can work normally when one phase thereof is not available. Therefore, the remaining two phases of the VRM which are provided to the microprocessor draw more current. It is dangerous for the VRM to drive the microprocessor with only two phases, because the heavy current may damage the VRM or reduce stability of the VRM.

What is needed, therefore, is a VRM control circuit which can solve the above problem.

An exemplary voltage regulator module (VRM) control circuit comprises a VRM providing a plurality of phases, each of the phases connected to a control terminal of a corresponding electric switch; a comparator comprising a non-inverting terminal connected to a first power source and grounded via the electric switches, an inverting terminal connected to a reference voltage, and an output terminal; and a control switch connected between an enable terminal of the VRM and ground, the control switch comprising a control terminal connected to the output terminal of the comparator, wherein, if one of the phases of the VRM is lost, the corresponding electric switch is turned off, and a voltage of the non-inverting terminal of the comparator is higher than the reference voltage, the comparator outputs a control signal to the control switch for turning on the control switch, thus turning off the VRM.

Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawing, in which:

The drawing is a circuit diagram of a VRM control circuit in accordance with a embodiment of the present invention.

Referring to the drawing, a voltage regulator module (VRM) control circuit in accordance with an embodiment of the present invention includes six NMOS transistors Q 1 ˜Q 6 functioning as electric switches and a comparator U. The gates of the NMOS transistors Q 1 ˜Q 3 are connected to three phases PHASE 1 ˜PHASE 3 of a VRM respectively. The sources of the NMOS transistors Q 1 ˜Q 3 are grounded. Each one of the drains of the NMOS transistors Q 1 ˜Q 3 is connected to a 5V power source and a non-inverting terminal + of the comparator U. An inverting terminal − of the comparator U is connected to a reference voltage VREF. The output terminal OUT of the comparator U is connected to the gate of the NMOS transistor Q 4 . The source of the NMOS transistor Q 4 is grounded, and the drain of the NMOS transistor Q 4 is connected to a power source VCC and an enable terminal VRM_EN of the VRM.

The comparator U further comprises a power terminal connected to a 12V power source and the drain of the NMOS transistor Q 5 . The source of the NMOS transistor Q 5 is grounded, and the gate of the NMOS transistor Q 5 is connected to the 5V power source and the drain of the NMOS transistor Q 6 . The source of the NMOS transistor Q 6 is grounded, and the gate of the NMOS transistor Q 6 is connected to a power supply to receive a power-good signal PWROK.

When the computer is turned off, the power-good signal PWEROK is at a low level to turn off the NMOS transistor Q 6 . Therefore, the NMOS transistor Q 5 is turned on for turning off the comparator U.

When the computer is turned on, the power-good signal is at a high level to turn on the NMOS transistor Q 6 . Therefore, the NMOS transistor Q 5 is turned off for turning on the comparator U. If the phases PHASE 1 ˜PHASE 3 of the VRM are working normally, the NMOS transistors Q 1 ˜Q 3 are turned on. Therefore, the output terminal OUT of the comparator U is at a low level to turn off the NMOS transistor Q 4 . That is, the enable terminal VRM_EN of the VRM is connected to the power source VCC for turning on the VRM.

If one of the phases PHASE 1 ˜PHASE 3 of the VRM is lost, the corresponding NMOS transistor is turned off. For example, if the phase PHASE 1 is lost, the NMOS transistor Q 1 will be turned off. Therefore, the output terminal OUT of the comparator U is at a high level to turn on the NMOS transistor Q 4 for grounding the enable terminal VRM_EN of the VRM to turn off the VRM.

The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to explain the principles of the invention and their practical application so as to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains without departing from its spirit and scope. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.