Memory power supply circuit

1. Field of the Invention

The present invention relates to power supply circuits, and particularly to a memory power supply circuit which supplies power to memories.

2. Description of Related Art

Generally speaking, memories of the computer have two types double data rate (DDR) SDRAM and double data rate 2 (DDR 2 ) SDRAM. However, the two types of memories have different interfaces (namely DDR has 180 pins, DDR 2 has 240 pins) and different work voltages (namely DDR is 2.6V, DDR 2 is 1.8V), thereby, they cannot use a same memory slot.

Nowadays, some motherboards integrate DDR and DDR 2 SDRAM slots therein. However, the two types of memories slots usually each have a memory power supply circuits for supplying power thereto, which increases the costs and occupies a lot of space of the motherboard.

What is needed is to provide a memory power supply circuit which can support the two types of memories slots.

An embodiment of a memory power supply circuit configured for supplying power to two types of memories slots of a motherboard includes a slot detecting terminal configured to connect with a detecting pin of the motherboard which is used to detect the memory slots, an electrical switch element, a first resistor, a second resistor, a third resistor, and a voltage output terminal connected to power input pins of the two types of memories slots. The second resistor and third resistor are connected in series between a first power supply and ground. The slot detecting terminal is connected to a first terminal of the electrical switch element. A second terminal of the electrical switch element is grounded. A third terminal of the electrical switch element is connected to the voltage output terminal via the first resistor and connected to a node between the second and third resistors.

Other advantages and novel features of the present invention will become more apparent from the following detailed description of an embodiment when taken in conjunction with the accompanying drawing, in which:

The drawing is a circuit diagram of a memory power supply circuit in accordance with an embodiment of the present invention.

Referring to the drawing, a memory power supply circuit in accordance with an embodiment of the present invention is configured for supplying power to two types of memories slots of a motherboard. The memory power supply circuit includes a slot detecting terminal X, an electrical switch element Q, a current-limiting resistor R, a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a voltage negative feedback circuit 10 , a porcelain capacitor C 1 , an electrolytic capacitor C 2 , and a voltage output terminal Y.

The voltage negative feedback circuit 10 includes an operational amplifier (op-amp) U, a first field-effect transistor (FET) Q 1 , and a second FET Q 2 . The op-amp U includes a non-inverting input terminal 3 , an inverting input terminal 2 , a power terminal 8 , a ground terminal 4 , and an output terminal 1 . In this embodiment, the electrical switch element Q is a PNP transistor. The two types of memories slots are respectively DDR SDRAM slot and DDR 2 SDRAM slot. The resistance of the first resistor R 1 is 1.75 KΩ. The resistance of the second resistor R 2 is 1 KΩ. The resistance of the third resistor R 3 is 3.7 KΩ.

The slot detecting terminal X is configured to connect with a detecting pin of the motherboard which is used to detect the memory slots. The slot detecting terminal X is connected to a first terminal (base) of the electrical switch element Q via the current-limiting resistor R. A second terminal (collector) of the electrical switch element Q is grounded. A third terminal (emitter) of the electrical switch element Q is connected to the non-inverting input terminal 3 of the op-amp U via the first resistor R 1 . The second and third resistors R 2 and R 3 are connected in series between a 3.3V first power supply VCC and ground. A node between the second and third resistors R 2 and R 3 is connected to the non-inverting input terminal 3 of the op-amp U. The inverting input terminal 2 of the op-amp U is connected to the voltage output terminal Y, and connected to ground via the porcelain capacitor C 1 , and connected to ground via the electrolytic capacitor C 2 . The power terminal 8 of the op-amp U is connected to a 12V second power supply VDD. The ground terminal 4 of the op-amp U is grounded. The output terminal 1 of the op-amp U is connected to the gates of the first and second FETs Q 1 and Q 2 . The drains of the first and second FETs Q 1 and Q 2 are connected to the first power supply VCC. The sources of the first and second FETs Q 1 and Q 2 are connected to the inverting input terminal 2 of the op-amp U. The voltage output terminal Y is connected to power input pins of the two types of memories slots.

The negative feedback circuit 10 is configured to steady the voltage from the node between the second and third resistors R 2 and R 3 . In other embodiments, the negative feedback circuit 10 can be deleted as a cost saving measure. That is the voltage output terminal Y is connected to the node between the second and third resistors R 2 and R 3 after deleting the negative feedback circuit 10 .

In working, if a DDR SDRAM is mounted in the DDR SDRAM slot, and the DDR SDRAM 2 slot is empty, the detecting pin of the motherboard transmits a high level voltage signal to the slot detecting terminal X, thereby the electrical switch element Q is turned off. The voltage of the non-inverting input terminal 3 of the op-amp U can be calculated as: V+=[3.7/(3.7+1)]*3.3=2.6V. The negative feedback circuit 10 can steady the 2.6V voltage. The 2.6V voltage of the non-inverting input terminal 3 of the op-amp U is supplied to the DDR SDRAM slot via the voltage output terminal Y.

If a DDR SDRAM 2 is mounted in the DDR SDRAM 2 slot, and the DDR SDRAM slot is empty, the detecting pin of the motherboard transmits a low level voltage signal to the slot detecting terminal X, thereby the electrical switch element Q is turned on. The voltage of the non-inverting input terminal 3 of the op-amp U can be calculated as: V+={[(3.7*1.75)/(3.7+1.75)]/[1+(3.7*1.75)/(3.7+1.75)]}*3.3=1.8V. The negative feedback circuit 10 can steady the 1.8V voltage. The 1.8V voltage of the non-inverting input terminal 3 of the op-amp U is supplied to the DDR SDRAM 2 slot via the voltage output terminal Y.

If a DDR SDRAM is mounted in the DDR SDRAM slot, and the DDR SDRAM 2 slot is mounted in the DDR SDRAM 2 slot, the detecting pin of the motherboard transmits a low level voltage signal to the slot detecting terminal X. The non-inverting input terminal 3 of the op-amp U is supplied 1.8V to the DDR SDRAM slot and DDR SDRAM 2 slot via the voltage output terminal Y. At this time, the DDR SDRAM cannot work, but the DDR SDRAM 2 will work, so that the motherboard can also work normally.

The memory power supply circuit can supply power to the two types of memories slots of the motherboard, which can reduce the costs and save space of the motherboard.

It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.