Electric circuit with protection against overvoltages

The present invention relates to an electric circuit, supplied by a voltage regulator, which employs protection modes against electrostatic discharges.

Some electric circuits such as the circuits employed in mobile telephones and made in semiconductor material can undergo damages caused by overvoltages deriving from electrostatic charges which can be generated by contacts (also simply by hand) with terminals of the same circuits which are accessible from the outside.

Prior approaches provide both the supply and the input/output terminals with electrostatic discharge devices, such as the ESD (Electrostatic Discharge) devices, which ensure the protection thereof against overvoltages.

The electric circuits to be protected can include, beside a voltage regulator, an amplifier provided with at least one output terminal for one voltage (for example, an audio signal) to be supplied to a using circuit. It is possible that the employment modes of the amplifier, or of another type of circuit, which supplies the voltage on the output terminal, provide for the latter to be brought to an inactive state—for example, either turned-off, or in stand-by—when the user circuit does not require its operation. In the inactive state, the amplifier may have its output terminal floating, not inducing it to any preset voltage values; however, in order that this happens, it is helpful if the circuit is supplied, that is, the voltage regulator is turned on.

On the contrary, if the voltage regulator is turned off, both the amplifier output devices and the devices employed for the protection do not allow for the output terminal to remain floating.

It shall be noted that it is possible to have applications in which it is important to be able to have an effectively floating output terminal, when both the circuit and the voltage regulator are in an inactive state.

In accordance with the present approach, an electric circuit includes a supply terminal to receive an outer supply voltage and a voltage regulator coupled to the supply terminal and to provide supply and resting voltages. A lock-out circuit is switchable between active and inactive states and receives the supply voltage at a supply node to generate, in the active state, an output voltage on a output terminal thereof. A protection circuit protects against electrostatic discharge, having at least one first diode coupled between the supply node and the output terminal. A cut-off electronic lock couples, in the inactive state, the supply node to the supply terminal by reverse biasing the at least one first diode to make a voltage of the output terminal float.

An apparatus embodiment includes the electronic circuit described above and a control device coupled to said output terminal to impose at least first and second voltage values to said output terminal, when said lock-out circuit of the electric circuit is in the inactive state. Moreover, a measurement device measures the at least one first and second voltage values on said output terminal.

In order to better understand the invention and appreciate the advantages thereof, some embodiments thereof are described herein below, by way of non-limiting example, with reference to the appended drawings, in which:

FIG. 1 shows a scheme of an example of an electric circuit, in accordance with the present invention,

FIG. 2 schematically shows an example of an electrostatic discharge device which can be employed in a circuit, in accordance with the present invention;

FIG. 3 shows an apparatus employing the electric circuit, in accordance with the present invention.

FIG. 1 shows an electric circuit 100 comprising a voltage regulator REG, connected to a battery BATT (or, alternatively, to another type of generator) with lock-out circuit VAMIC_AMP provided with an output terminal 2 for a voltage to be supplied to a user circuit, not shown in FIG. 1 .

The voltage regulator REG is connected to a first supply terminal 3 , which supplies a first battery voltage VBAT derived from the battery BATT. The voltage regulator REG may take an active state, in which it supplies to a first terminal 1 thereof a supply voltage VDD, and an inactive state, in which it supplies to the first terminal 1 a resting voltage, that is the ground voltage. The switching between the active and the inactive states (in which the voltage regulator REG is turned off or in stand-by), and vice versa, is controlled by an enabling signal EN_REG.

Advantageously, the voltage regulator REG provides to the first terminal 1 the low noise supply voltage VDD (which represents a reference voltage for the lock-out circuit VAMIC_AMP) and, therefore, operates a rejection of the battery voltage VBAT noises.

The lock-out circuit VAMIC_AMP is also switchable between an active state and an inactive state, and it can be supplied through the supply voltage VDD in order to generate, in the active state, an output voltage VAMIC on its output terminal 2 . As it will be clarified herein below, the circuit 100 in the inactive state is such as to make the output terminal 2 having an high impedance or, correspondently, to have the output terminal 2 “floating”, thereby making that the same lock-out circuit does not impose voltage values to such output terminal.

The lock-out circuit VAMIC_AMP is provided with a respective input terminal 4 connected to a supply node VDDAMIC on which the supply voltage VDD is provided, as will be clarified herein below.

The lock-out circuit VAMIC_AMP, for example, is a signal amplifier and can be, in particular and without limitation, an amplifier which can be used to provide a voltage signal VAMIC to a microphone (not shown) such as that of a cellular telephone.

The lock-out circuit VAMIC_AMP has an activation terminal to receive a first control signal EN_VAMIC adapted to take an activation value (for example, high logic value) and an inactivation value (for example, low logic value). In accordance with the particular example of FIG. 1 , such first control signal EN_VAMIC is generated by a first inverter IV 1 so that the activation value may be equal to the battery voltage VBAT, and the inactivation value may be equal to the ground voltage GND.

The possibility to bring both the voltage regulator REG and the lock-out circuit VAMIC_AMP in an inactive state is particularly advantageous, since it allows for an economy in the power drawn from the battery BATT, when the user circuit is not operative.

The electric circuit 100 is further provided with an electronic circuit ESPR 1 for the protection of the output terminal 2 against electrostatic overvoltages. Such first protection circuit ESPR 1 allows to discharge to a ground terminal GND the electrostatic charges which may be present at the output terminal 2 , for example, charges brought to the output terminal 2 through a contact with a clamp of a user circuit, or a direct hand contact by a user.

According to an exemplary embodiment, the protection circuit ESPR 1 comprises at least one first diode device and, in particular, it is provided with a first diode D 1 and a second diode D 2 . In greater detail, the first diode D 1 has a first terminal T 1 connected to the supply node VDDAMIC, and a second terminal T 2 connected to the output terminal 2 . Advantageously, the terminal T 1 of the first diode D 1 is a negative terminal (that is of the N type) of the same diode, while the second terminal T 2 is the positive terminal (of the P type). The second diode D 2 has a respective first terminal T 3 (of the N type) connected to the output terminal 2 and a respective second terminal T 4 (of the P type) connected to the ground terminal GND.

Furthermore, the protection circuit ESPR 1 comprises a first electrostatic discharge device ESD 1 , located, according to the example, in parallel to the D 1 and D 2 diodes array and, thus, connected to the first terminal T 1 of the first diode D 1 , common to the supply node VDDAMIC, and the ground terminal GND. The first electrostatic discharge device ESD 1 , is to represent, under standard conditions, (that is, substantially in the absence of current due to electrostatic charge), an open circuit, and to constitute a connection between the first terminal T 1 of the diode D 1 and the ground terminal GND, when a current amount due to the electrostatic charge at the first terminal T 1 above a preset value is detected, allowing to discharge the current to the ground. A particular embodiment of the electrostatic discharge device ESD 1 will be described below with reference to FIG. 2 .

The electric circuit 100 is also provided with a cut-off electronic lock ITRB to connect, in the inactive state, the supply node VDDAMIC—and thus the input terminal 4 —to the first supply terminal 3 , by reverse biasing the first diode D 1 . By reverse biasing the first diode D 1 , the output terminal 2 is isolated from the supply node VDDAMIC, thus making it floating, that is, inducing such output terminal 2 to have a high impedance.

Furthermore, according to the example, the cut-off electronic lock ITRB is to disconnect, in the active state, the supply node VDDAMIC from the first supply terminal 3 .

Advantageously, the cut-off electronic lock ITRB is to connect/disconnect (in the active and inactive states, respectively) the first terminal 1 of the voltage regulator REG from the supply node VDDAMIC, and therefore from the input terminal for the supply 4 of the lock-out circuit VAMIC_AMP. Preferably, the cut-off electronic lock ITRB comprises a first switch M 1 having a first input I 1 connected to the first supply terminal 3 (where the battery voltage VBAT is located), and a first output O 1 connected to the supply node VDDAMIC of the lock-out circuit VAMIC_AMP.

The first switch M 1 is controlled to be open (by inhibiting the conduction between I 1 and O 1 ) during the active state, and to be closed (conduction enabled between I 1 and O 1 ) during the inactive state, in order to substantially carry the battery voltage VBAT to the supply node VDDAMIC. The first switch M 1 has a respective control terminal to receive, for example, the above-mentioned signal EN_VAMIC as the control signal, resulting in a suitable synchronization with the transitions from the active to the passive states of the regulator REG and the lock-out circuit VAMIC_AMP.

In particular, the cut-off electronic lock ITRB comprises a second switch M 2 having a second input I 2 connected to the first terminal 1 , and a second output O 2 connected to the supply node VDDAMIC of the lock-out circuit VAMIC_AMP. The second switch M 2 is controlled to be closed (that is, it enables the conduction between I 2 and O 2 ) during the active state to carry the supply voltage VDD to the supply node VDDAMIC. The second switch M 2 is controlled to be open (by inhibiting the conduction between I 2 and O 2 ) when the regulator REG and the lock-out circuit VAMIC_AMP are in the inactive state.

The second switch M 2 has a respective control terminal to receive a second control signal such as, in accordance with the example, the denied signal of EN_VAMIC, resulting in a suitable synchronization with the transitions of the regulator REG and the lock-out circuit VAMIC_AMP from the active to the passive states, and vice versa. In particular, the denied signal of EN_VAMIC is generated by a second inverter IV 2 connected in output to the first inverter IV 1 , and such as to take the voltages VBAT and GND.

According to a preferred exemplary embodiment, at least one of the switches M 1 and M 2 includes a respective transistor MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or, in short, MOS. In particular, taking into account that the circuit 100 can be made (for example) by the semiconductor integrated technology and, preferably, by the MOS technology, the first and the second switches M 1 and M 2 are preferably P-channel MOS transistors. The control signals EN_VAMIC and the denied signal thereof are applied to respective gate terminals of the two MOS transistors M 1 and M 2 .

It shall be noted that, according to the particular embodiment described, the electric circuit 100 is such that the battery voltage VBAT is the voltage value that the nodes and terminals of the same circuit can reach. Advantageously, to ensure a proper functioning of the first MOS transistor M 1 , this has (as schematically outlined in FIG. 1 ) its own body or substrate terminal B 1 connected to the input I 1 , that is connected to the first supply terminal 3 where the battery voltage VBAT is available.

The second MOS transistor M 2 has its own body terminal B 2 connected to the supply node VDDAMIC, where the battery voltage VBAT is available, when the lock-out circuit VAMIC_AMP is in the inactive state.

Advantageously, the electric circuit 100 comprises a second electrostatic discharge device ESD 2 , which can be made similarly to the first device ESD 1 , connected between the first terminal 1 and the ground terminal GND in order to discharge to the ground the electrostatic charge which is present at the first terminal 1 . The electrostatic discharge device ESD 2 , or another equivalent protection form, allows protecting the supply node VDDAMIC (connectable to the first terminal 1 ) and the ground terminal GND.

FIG. 2 schematically shows a particular embodiment of an electrostatic discharge device ESD (which can be made in MOS technology), the basic architecture of which can be employed for the implementation of the first and the second electrostatic discharge devices ESD 1 and ESD 2 .

The electrostatic discharge device ESD comprises a transistor, for example, a MOS transistor M (in particular, of the N-channel type), having a source terminal S connected to the ground terminal GND, a drain terminal D connected to a supply terminal Vd, and a gate terminal G connected to a terminal of a resistor X, having another terminal connected to the ground terminal GND.

Furthermore, the electrostatic discharge device ESD is provided with a capacitor C connected between the supply terminal Vd and the gate terminal G.

In a standard operative condition, a preset voltage Vd is applied, and the resistor R brings the gate voltage G of the transistor M to the ground value. In this circumstance, the capacitor C remains charged between the ground and the Vd voltages, and the transistor M is inactive. This condition may be maintained for some degree of variations of the voltage Vd.

In the case a rapid variation of the voltage Vd occurs (as happens for electrostatic discharges) the capacitor C raises the gate terminal G voltage to the activation of the MOS transistor M, which closes, thus allowing a discharging of the charge inputted into the device ESD to the ground terminal GND. Once the discharge is run down, the voltage is lowered at the gate terminal G, and the transistor M opens again.

On the basis of FIG. 2 , those of ordinary skill in the art will be easily able to design electrostatic discharge devices which are suitable also for currents associated to electrostatic charges having a sign opposite to the one examined in the previous example.

With reference to the electric circuit 100 functioning, a condition is to be taken into account in which the voltage regulator REG and the lock-out circuit VAMIC_AMP are in the active state (for example, the first control signal EN_VAMIC and the enabling signal EN-REG are equal to VBAT).

In such condition, the first transistor M 1 is open, while the second transistor M 2 is closed, thus allowing an electric connection between the first terminal 1 , on which the supply voltage VDD is available, and the supply node VDDAMIC. The lock-out circuit VAMIC_AMP, which substantially receives the supply voltage VDD—suitably stabilized by the regulator REG—at the terminal 4 thereof, operates by supplying the output voltage VAMIC on the output terminal 2 . Such output voltage VAMIC will be able to be used by a user circuit in the modes provided for by the particular application. The lock-out circuit VAMIC_AMP is sized so as the voltage VAMIC is able to take values within a specific range.

In the case where the user circuit is not operative anymore, and does not require the voltage VAMIC, both the lock-out circuit VAMIC_AMP and the voltage regulator REG are brought to the inactive state by the first control signal EN_VAMIC (which takes the GND value), and by the enabling signal EN_REG (which takes the GND value), so as to result in an energy saving. The voltage regulator REG brings the first terminal 1 to the ground voltage GND.

The first transistor M 1 switches from the open to the closed state, making the battery voltage VBAT (the positive voltage, according to the example) to be supplied at the supply node VDDAMIC, thereby ensuring that the first diode D 1 is inversely biased, so as to avoid an electric connection between the output terminal 2 and the supply node VDDAMIC. In such condition, the output terminal 2 is isolated from the supply node VDDAMIC and the first terminal 3 ; therefore, it is floating, representing a high-impedance node.

Furthermore, the second transistor M 2 switches from the closed to the open states, thus interrupting the electric connection between the first terminal 1 and the supply node VDDAMIC.

It shall be noted that the switching of the second transistor M 2 to the open state prevents the ground voltage GND which is present at the first terminal 1 from causing an activation of the first diode D 1 (by lowering the voltage of its N-type terminal T 1 ), putting in electric connection the first terminal 1 and the output terminal 2 . If, in the inactive state, the electric connection between the first terminal 1 and the output terminal 2 would occur, on the latter the voltage taken by the first terminal 1 may be imposed.

Furthermore, the fact that the first switch M 1 carries the supply node VDDAMIC to the battery voltage VBAT induces a possible undesired current which passes through the second switch M 2 in the open state to not be able to cause the direct biasing of the first diode D 3 .

With regard to the behaviour toward electrostatic discharges, the electric circuit 100 is to be considered. In the case where an overvoltage at the output terminal 2 is inputted, for example, such to introduce a positive electric charge, this raises the output terminal 2 and the second terminal T 2 potentials of the first diode D 1 , thus causing the direct biasing thereof. In this way, the positive charge introduced by the output terminal 2 reaches the first terminal T 1 of the first diode D 1 , thus activating the first discharge device ESD 1 which allows it to flow out towards the ground terminal GND. In the case of a negative charge inserted by the output terminal 2 , this induces a direct biasing of the second diode D 2 , so as to allow to the same charge to be discharged towards the ground GND.

In the case where a charge is inputted by the first terminal 1 , the charge will be able to be readily discharged towards the ground terminal GND by the second electrostatic discharge device ESD 2 . In particular applications, it is useful that the output terminal 2 remains floating in the inactive state.

To this regard, with reference to FIG. 3 , an apparatus 600 is shown (for example, a mobile telephone) comprising the electric circuit 100 described above, a control device 300 , a measurement device 400 , and a user circuit 500 , all connected to the electric circuit 100 output terminal 2 . Furthermore, the apparatus 600 comprises a checking device CU connected to the measurement device 400 .

When the lock-out circuit VAMIC_AMP ( FIG. 1 ) is activated, it supplies on the output terminal 2 the voltage VAMIC which is used by the user circuit 500 , for example a microphone connected to an earpiece which can be coupled to the mobile telephone. When the lock-out circuit VAMIC_AMP is inactive and the output terminal 2 is left floating, such terminal is free to take the voltage imposed by the control circuit 300 .

For example, the control circuit 300 can supply a voltage having a first value VA, and indicative of a first control imparted by a user of the apparatus 600 . Alternatively, the control circuit 300 can supply a second voltage value VB indicative of another control imparted by the user through the control circuit 300 .

The measurement device 400 may be able to measure the voltage applied to the output terminal 2 by the control device 300 so as to evaluate the type of control imparted by the user. On the basis of the type of control recognized by the measurement device, the checking device CU (for example, a microprocessor) may be able to generate checking signals of the apparatus 600 such as, for example, the enabling signal EN_REG and the control signal EN_VAMIC, so as to bring the electric circuit 100 back in the active state.

The teachings of the present invention are particularly advantageous, since they allow combining the protection of the output terminal 2 against electrostatic discharges with the possibility to let the same output terminal floating, when the lock-out circuit VAMIC_AMP is in the inactive state.

This allows connecting not only the user circuit, but also other circuits intended to function to the same output terminal when the lock-out circuit VAAMIC_AMP is inactive.

It shall be noted that the employment of an electrostatic discharge device, such as the first device ESD 1 , connected between inner nodes of the electric circuit 100 and not connected, as typically occurs, between the supply terminals and a ground terminal, constitutes an innovative use of such discharge device.

The protection against electrostatic discharges can be advantageously carried out also for the first supply terminal 1 through the second discharge device ESD 2 . Furthermore, the preferred use of switches M 1 and M 2 of the P-MOS type with the relative body terminal connected to the node for which the maximum electric voltage is applied ensures a proper biasing of these devices.