Semiconductor memory device and method for fabricating semiconductor memory device

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. JP2006-265561, filed Sep. 28, 2006, the entire contents of which are incorporated herein by reference.

The present invention relates to a semiconductor memory device and fabricating for the semiconductor memory device.

A non-volatile semiconductor memory device in next generation has been developed. The non-volatile semiconductor memory device in next generation has characteristics such as a capability of high speed rewriting and a rewriting number being over five figures as comparing with a conventional EEPROM or flash memory. The non-volatile semiconductor memory device in next generation has also an aim to realize capacity, speed and cost comparable in quality to a DRAM. An FeRAM (Ferroelectric Random Access Memory), a MRAM (Magnetic Random Access Memory), a PRAM (Phase Change Random Access Memory), a RRAM (Resistive Random Access Memory) or the like has been developed as the next-generation non-volatile semiconductor memory device.

The PRAM records information by using different crystalline states of a phase-change element. Actually, when a phase-change element is changed from a poly-crystalline state with lower resistance of “1” state to an amorphous state with higher resistance of “0”, so called reset operation, comparatively large current (reset current) is flowed to the phase-change element SR 1 so as to rise up a temperature of the phase-change element over melting point (Tm), subsequently, the phase-change element is rapidly cooled. On the other hand, when the phase-change element is changed from the amorphous state with higher resistance of “0” to the poly-crystalline state with lower resistance of “1”, so called set operation, comparatively small current (set current) is flowed to the phase-change element so as to retain the phase-change element at a crystallizing temperature (Tc) below Tm as shown in Japanese Patent Publication (Kokai) No. 2004-158854.

The reset current flowing in the phase-change element of the memory cell is comparatively larger, for example 0.5-1 mA. Therefore, generated joule heat or the like in the phase-change element cause difficulty on highly integrating the phase-change memory. Further, necessity of precisely writing in information and reading out information in a low voltage region generates difficulty in the PRAM as disclosed in Japanese Patent Publication (Kokai) No. 2004-158854 (P14 and FIGS. 1 and 2).

According to an aspect of the invention, there is provided, a semiconductor memory device, including, a semiconductor substrate, a phase-change element formed on the semiconductor substrate, the phase-change element including a phase-change film and electrode films, a joule heat portion contacting with the electrode film, the phase-change film being formed around the joule heat portion, and a radiation-shield film suppressing dissipation of thermal radiation emitted from the joule heat portion.

Further, another aspect of the invention, there is provided, A method for fabricating a semiconductor memory device, including, forming an interconnection layer on a semiconductor substrate, a memory transistor being formed in the semiconductor substrate, a drain or a source of the memory transistor connecting with the interconnection layer, forming an interlayer dielectric film on the interconnection layer, etching the interlayer dielectric film on the interconnection layer so as to form an opening exposing the interconnection layer, forming a radiation-shield film on a side-wall of the opening, forming an insulator on the side-wall of the opening so as to cover the radiation-shield film, forming a lower electrode film on the opening formed the radiation-shield film and the insulator on the side-wall, forming a phase-change film on the lower electrode film, and forming an upper electrode film on the phase-change film.

Further, another aspect of the invention, there is provided a method for fabricating a semiconductor memory device, including, forming a interconnection layer on a semiconductor substrate, a memory transistor being formed in the semiconductor substrate, a drain or a source of the memory transistor connecting with the interconnection layer, forming a first interlayer dielectric film on the interconnection layer, etching the first interlayer dielectric film on the interconnection layer so as to an opening exposing the interconnection layer, forming a lower electrode film of the phase-change element in the opening, forming an insulator onside-wall of the opening with the lower electrode film, forming a phase-change film on the lower electrode film without the insulator, forming an upper electrode film on the phase-change film, forming a second interlayer dielectric film on the first interlayer dielectric film, the phase-change film and the upper electrode film, and forming a radiation-shield film on the second interlayer dielectric film.

FIG. 1 is a circuit diagram showing a PRAM memory cell in a first embodiment of the present invention;

FIG. 2 is a schematic diagram showing an operation of a set and a reset of a phase-change element in the first embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a memory cell portion of a phase-change memory in the first embodiment of the present invention;

FIG. 4 is a cross-sectional view showing processing steps of the phase-change memory in the first embodiment of the present invention;

FIG. 5 is a cross-sectional view showing the processing steps of the phase-change memory in the first embodiment of the present invention;

FIG. 6 is a cross-sectional view showing the processing steps of the phase-change memory in the first embodiment of the present invention;

FIG. 7 is a cross-sectional view showing the processing steps of the phase-change memory in the first embodiment of the present invention;

FIG. 8 is a cross-sectional view showing the processing steps of the phase-change memory in the first embodiment of the present invention;

FIG. 9 is a cross-sectional view showing the processing steps of the phase-change memory in the first embodiment of the present invention;

FIG. 10 is a cross-sectional view showing a phase-change element of a phase-change memory in a second embodiment of the present invention;

FIG. 11 is a cross-sectional view showing processing steps of the phase-change memory in the second embodiment of the present invention;

FIG. 12 is a cross-sectional view showing processing steps of the phase-change memory in the second embodiment of the present invention;

FIG. 13 is a cross-sectional view showing processing steps of the phase-change memory in the second embodiment of the present invention;

FIG. 14 is a cross-sectional view showing processing steps of the phase-change memory in the second embodiment of the present invention;

FIG. 15 is a cross-sectional view showing a phase-change element of a phase-change memory in a third embodiment of the present invention.

Embodiments of the present invention will be described below in detail with reference to the attached drawings. It should be noted that the present invention is not restricted to the embodiments but covers their equivalents. Throughout the attached drawings, similar or same reference numerals show similar, equivalent or same components.

First Embodiment

First, a semiconductor memory device and a method for fabricating the semiconductor memory device according to a first embodiment of the present invention will be described below in detail with reference to figures.

FIG. 1 is a circuit diagram showing a PRAM memory cell. FIG. 2 is a schematic diagram showing an operation of a set and a reset of a phase-change element. FIG. 3 is a cross-sectional view showing a memory cell portion of a phase-change memory.

In this embodiment, a radiation-shield film suppresses and shields dissipation of thermal radiation emitted from joule heat portion where a phase-change film contacts with a lower electrode film.

As shown in FIG. 1 , a PRAM (Phase Change Random Access Memory) memory cell 40 is composed of a phase-change element SR 1 , a transistor TR 1 as a memory transistor. Further, the PRAM is called a phase-change memory. The transistor TR 1 is composed of, for example, N-ch MISFET (Metal Insulator Semiconductor Field Effect Transistor). A gate of the transistor TR 1 is connected with a word line WL and a source of the transistor TR 1 is connected with a low potential power supply (earth potential) Vss. One end of the phase-change element SR 1 is connected with the bit line BL and the other end of the phase-change element SR 1 is connected with the drain of the transistor TR 1 . On the other hand, the source of the transistor TR 1 may be connected with a plate line instead of a low potential power supply (earth potential) Vss, as a result, the PRAM memory cell may be used. Further, the phase-change element may be provided between the memory transistor and the plate line, and the drain of the memory cell transistor may be connected with the bit line so that the PRAM memory cell may be used. In this case, the source of the memory cell transistor is connected with the phase-change element.

As shown in FIG. 2 , when the phase-change element SR 1 is changed from a poly-crystalline state with lower resistance of “1” state to an amorphous state with higher resistance of “0”, so called reset operation, a reset pulse signal of a period t 1 with below 1 ns, for example, is applied to the phase-change element SR 1 . Flowing comparatively large current (reset current) to the phase-change element SR 1 causes to rise up a temperature of the phase-change element SR 1 over melting point (Tm), subsequently, the phase-change element SR 1 is rapidly cooled.

On the other hand, when the phase-change element SR 1 is changed from the amorphous state with higher resistance of “0” to the poly-crystalline state with lower resistance of “1”, so called set operation, the reset pulse signal of a period t 2 with above 10 ns, for example, is applied to the phase-change element SR 1 . Flowing comparatively small current (set current) to the phase-change element SR 1 causes to lower down a temperature of the phase-change element SR 1 below Tm, subsequently, the phase-change element SR 1 is retained at over crystallization temperature (Tc) in a predetermined period.

As shown in FIG. 3 , a STI (Shallow Trench Isolation) 2 isolating the memory transistor in the PRAM memory cell 40 is embedded at an upper potion of a semiconductor substrate 1 . A surface of the STI 2 is formed at the same level as a surface of the semiconductor substrate 1 . A source/drain region 3 of the memory transistor with the conductive type being reverse to the semiconductor substrate 1 is selectively formed between the plurality of STI 2 . A gate electrode film 5 being a gate electrode of the transistor TR 1 is selectively formed over an upper portion of a region between the source/drain regions 3 in the semiconductor substrate 1 via a gate insulator 4 . An interlayer dielectric film 6 is formed to cover the STI 2 , the source/drain region 3 , the gate insulator 4 and a gate electrode film 54 .

An opening in the interlayer dielectric film 6 is formed on the source/drain region 3 so as to expose a portion of the source/drain region 3 . A via-plug 7 is embedded in the opening. An interconnection layer 8 being connected with the via-plug 7 is formed on the via-plug 7 . In addition, the interconnection layer 8 configured at the right side of transistor TR 1 is connected with the low potential power supply Vss and the phase-change element SR 1 is formed on the interconnection layer 8 .

An interlayer dielectric film 9 is formed to cover the interconnection layer 8 expect the region of the interlayer dielectric film 6 and the phase-change element SR 1 . A lower electrode film 10 of the phase-change element SR 1 is formed over the interconnection layer 8 and a phase-change film 13 is formed on the lower electrode film 10 . An insulator 12 is formed on side-walls of the lower electrode film 10 and the side-walls in the lower portion of the phase-change film 13 . A radiation-shield film 11 is formed via a joule heat portion and the insulator 12 . An upper electrode film 14 is formed on the phase-change film 13 .

An interlayer dielectric film 15 is formed on the interlayer dielectric film 9 and upper electrode film 14 . An opening is formed in the interlayer dielectric film 15 to expose a portion of the upper electrode film 14 . A via-plug 16 is embedded in the opening. An interconnection layer 17 being a bit line BL is formed on the interlayer dielectric film 15 and the via-plug 16 and is connected with the-via plug 16 .

Here, when the reset pulse or the set pulse is applied to the phase-change element SR 1 , a portion where the phase-change film 13 contacts with the lower electrode film 10 becomes a joule heat portion. The radiation-shield film 11 suppresses and shields dissipation of thermal radiation emitted from joule heat portion. Therefore, a surface opposed to the joule heat portion of the radiation-shield film 11 is desirably a mirror finished surface to reflect the thermal radiation. The radiation-shield film 11 also is desirably a cylindrical shape to suppress and shield dissipation of thermal radiation emitted from the joule heat portion, or a cylindrical shape with the upper portion or the lower portion being formed as R state to shorten between the upper portion or the lower portion and the joule heat portion. Moreover, a square prism or a polygonal prism with central portion being empty may be used instead of the cylindrical shape.

Next, a method for fabricating phase-change memory will be described below in detail with reference to FIGS. 3-9 . The processing steps on the phase-change memory are described as cross-sectional views in FIGS. 3-9 .

As shown in FIG. 4 , the STI 2 is embedded at an upper portion of the semiconductor substrate 1 . The gate insulator 4 and the gate electrode film 5 are selectively stacked on the semiconductor substrate 1 in layer. The source/drain region 3 is formed to sandwich a portion where the gate insulator 4 and the gate electrode film 5 are stacked in layer. The interlayer dielectric film 6 is formed on the STI 2 , the source/drain region 3 , the gate insulator 4 and the gate electrode film 5 . The interlayer dielectric film 6 formed on the source/drain region is etched and the via-plug 7 , for example W (tungsten), is embedded in the opening partially exposed on the source/drain region 3 .

The interconnection layer 8 is formed on the via-plug 7 , and the interlayer dielectric film 9 is formed on the interlayer dielectric film 6 and the interconnection layer 8 . The interlayer dielectric film 9 on the interconnection layer 8 in a portion of the phase-change element SR 1 is etched and the opening exposed a portion of the interconnection layer 8 is formed. The radiation-shield film 11 is formed on the opening and the interlayer dielectric film 9 . Here, W is used as the radiation-shield film 11 , however, AL (aluminum) or another metals being able to suppress and shield dissipation of thermal radiation may also be used. Further, a film except a metal film may be used as the radiation-shield film 11 . For example, Al 2 O 3 , SiN, SiC, ZrO 2 or the like can be nominated as a material with suppressing thermal diffusion by lattice vibration.

As shown in FIG. 5 , the radiation-shield film 11 is etched by RIE (Reactive Ion Etching), for example, so that the radiation-shield film 11 is remained on a side portion except the upper part of the opening. A higher etching rate (larger selective ratio) to the interlayer dielectric film 9 is favorably used on RIE process of the radiation-shield film 11 .

As shown in FIG. 6 , the insulator 12 is formed on the interconnection layer 8 , the interlayer dielectric film 9 and the radiation-shield film 11 remained. The insulator 12 is etched by RIE, for example, and the insulator 12 is remained on the side-wall of the opening so that the radiation-shield film 11 is covered with the radiation-shield film 11 . Consequently, the opening 8 on the interconnection layer is narrowed. The lower electrode film 10 is formed on the opening narrowed.

As shown in FIG. 7 , the insulator 12 is again formed on the interlayer dielectric film 9 , the lower electrode film 10 and the insulator 12 remained. The insulator 12 is etched by RIE, for example, so that the insulator 12 is remained on the upper end portion of the lower electrode film 10 .

As shown in FIG. 8 , the phase-change film 13 and the upper electrode film 14 are stacked on the interlayer dielectric film 9 , the lower electrode film 10 and the insulator 12 in layer. Here, TiN (titanium nitride) is used as the lower electrode film 10 and the upper electrode film 14 , however, TiAlN (titanium-aluminum nitride), TiSiN (titanium-silicon nitride), TaAlN (tantalum-aluminum nitride), TaSiN (tantalum-silicon nitride) or the like also can be used. A SiON film is used as the insulator 12 , however, a silicon oxide film (SiO2), a SiN film (silicon nitride film), SiOC or another low-k materials may also be used. A GST (GeSbTe-chalcogenate) is used as the phase-change film 13 , however, AsSbTe, SeSbTe, doped-AsSbTe or doped-SeSbTe may be used. In this case, O (oxygen), N (nitrogen) or Si (silicon) may be used as a doping material.

As shown in FIG. 9 , the phase-change film 13 and the upper electrode film 14 stacked in layer are etched by RIE, for example, the portion of the phase-change element SR 1 in the phase-change film 13 and the upper electrode film 14 are remained the interlayer dielectric film 9 is again formed on the interlayer dielectric film, the phase-change film 13 and the upper electrode film 14 , the interlayer dielectric film 9 is polished by CMP (Chemical Mechanical Polishing), for example, so that the upper electrode film 14 is exposed.

Furthermore, the interlayer dielectric film 15 is formed on the interlayer dielectric film 9 and the upper electrode film 14 . An opening is formed in the interlayer dielectric film 15 to expose a portion of the upper electrode film 14 , subsequently the via-plug 16 is embedded in the opening. The interconnection layer 17 is formed on the interlayer dielectric film 15 and the via-plug 16 . the interconnection layer 17 becomes the bit line BL being connected with the via-plug 16 . After forming the interconnection layer 17 , the interlayer dielectric film and the interconnection layer are formed by using well-known technique so as to complete the PRAM.

As mentioned above, the phase-change element SR 1 and the memory transistor are formed in the PRAM memory cell 40 in this embodiment of semiconductor memory device and the fabrication method. The phase-change element SR 1 is composed of the lower electrode film 10 , the phase-change film 13 and the upper electrode film 14 . The lower electrode film 10 is connected with the drain of the memory transistor via the interconnection layer 8 and the via-plug 7 . When the reset pulse or the set pulse is applied on the phase-change element SR 1 , the portion where the phase-change film 13 contacts with the lower electrode film 10 is heated up. When the reset pulse is applied, the reset current, relatively large current flows in the phase-change element SR 1 so that the phase-change film 13 is melted to change to the amorphous state. On the other hand, when the set pulse is applied, relatively small current flows in the phase-change element SR 1 so that the phase-change film 13 is crystallized to change to the poly-crystalline state. The radiation-shield film 11 is formed around the joule heat portion. The radiation-shield film 11 reflects thermal radiation emitted from the joule heat portion through the insulator 12 so as to suppress and shield dissipation of thermal radiation.

The phase-change element SR 1 is exchanged from a poly-crystalline state with lower resistance of “1” state to an amorphous state with higher resistance of “0”, therefore, the reset current, comparatively large current, can be decreased. Furthermore, the set current, comparatively small current, can be also decreased. The phase-change element SR 1 is changed from the amorphous state with higher resistance of “0” to the poly-crystalline state with lower resistance of “1” state. Accordingly, the phase-change memory can be highly integrated and information in the phase-change memory can precisely be written in and read out at low voltage. Moreover, decrease with consumption current on writing and reading can easily cause to an on-chip device of CMOS circuit or the like.

Furthermore, the insulator 12 is formed between the lower electrode film 10 and the radiation-shield film 11 by using two-step RIE technique in this embodiment, however, the insulator 12 may be remained and formed by conventional one-step RIE technique.

Second Embodiment

Next, a semiconductor memory device and a method for fabricating the semiconductor memory device according to a second embodiment of the present invention will be described below in detail with reference to figures.

FIG. 10 is a cross-sectional view showing a phase-change element of a phase-change. A setting position of a radiation-shield film is changed as comparing with the position of the first embodiment. The radiation-shield film suppresses and shields dissipation of thermal radiation emitted from a joule heat portion where a phase-change film contacts with a lower electrode film.

The second embodiment will be described below in detail with reference to the attached drawings. Throughout the attached drawings, similar or same reference numerals show similar, equivalent or same components.

As shown in FIG. 10 , in a PRAM memory cell, a phase-change element SR 1 a is formed on the interconnection layer 8 . In the PRAM cell of this embodiment, as a portion under the interconnection layer is the same structure as the first embodiment, the description of the same or similar parts and elements will be omitted

The lower electrode film 10 of the phase-change element SR 1 a is formed on the interconnection layer 8 having a side-wall covered with a interlayer dielectric film 21 . The upper electrode film 14 of the phase-change film 13 and the phase-change element SR 1 a are stacked on the lower electrode film 10 in layer. The insulator 12 is formed on both side-walls of the lower electrode film 10 and both side-walls of the under part of the phase-change film 13 . the via-plug 16 is formed on the center portion of the upper electrode film 14 , an insulator 24 is formed on the both ends of the via-plug 16 . The radiation-shield film 11 is embedded in a interlayer dielectric film 22 . The both ends of the radiation-shield film 11 are formed on the interlayer dielectric film 21 , the both side-walls of the radiation-shield film 11 is formed to oppose to the phase-change element SR 1 a via the interlayer dielectric film 22 . The upper portion of the radiation-shield film 11 is formed to oppose to the upper electrode film 14 via the interlayer dielectric film 22 , as a result, the radiation-shield film 11 is formed apart from the via-plug 16 via the insulator 24 . The interconnection layer 17 is formed on the interlayer dielectric film 22 and the via-plug 16 to become the bit line BL being connected with the via-plug 16 .

Here, when the reset pulse or the set pulse is applied to the phase-change element SR 1 a , a portion where the phase-change film 13 contacts with the lower electrode film 10 becomes a joule heat portion. The radiation-shield film 11 suppresses and shields dissipation of thermal radiation emitted from joule heat portion. Therefore, a surface opposed to the joule heat portion, especially the side portion, of the radiation-shield film 11 is desirably a mirror finished surface to reflect the thermal radiation. The side-wall of the radiation-shield film 11 also is desirably a cylindrical shape to suppress and shield dissipation of thermal radiation emitted from the joule heat portion. Moreover, a square prism or a polygonal prism with central portion being empty may be used as the side-wall instead of the cylindrical shape.

Next, processing steps on the phase-change memory are described as cross-sectional views in FIGS. 11-14 . Here, processing steps of forming a transistor of the PRAM memory cell and the via-plug 7 are omitted, because the processing steps are the same as the first embodiment.

As shown in FIG. 11 , interconnection layer 8 is formed on the via-plug 7 and the interlayer dielectric film 21 is formed on the side-wall of the interconnection layer 8 . The interlayer dielectric film 22 is formed on the interconnection layer 8 and the interlayer dielectric film 21 . The interlayer dielectric film 22 on the interconnection layer 8 is etched to form the opening with exposing the interconnection layer 8 . The lower electrode film 10 of the phase-change element SR 1 a is embedded in the bottom of the opening. the insulator 12 is formed on the lower electrode film 10 and the interlayer dielectric film 22 . The insulator 12 is etched by RIE, for example, to remain the insulator 12 on the side-wall portion of the opening. The phase-change film 13 and the upper electrode film 14 of the phase-change element SR 1 a are stacked on the lower electrode film 10 , the insulator 12 and the interlayer dielectric film 22 in layer.

As shown in FIG. 12 , the upper electrode film 14 , the phase-change film 13 and the interlayer dielectric film 22 are etched by RIE, for example, to form the upper electrode film 14 in the phase-change element SR 1 and the phase-change film 13 .

As shown in FIG. 13 , the interlayer dielectric film 22 is formed on the upper electrode film 14 , the phase-change film 13 and the interlayer dielectric film 21 . Subsequently, the radiation-shield film 11 is formed on the interlayer dielectric film. The interlayer dielectric film 22 is electrically isolated between the upper electrode film 14 and the radiation-shield film 11 , and between the phase-change film 13 and the radiation-shield film 11 .

As shown in FIG. 14 , the interlayer dielectric film 22 is formed on the radiation-shield film 11 . The interlayer dielectric film 22 and the radiation-shield film 11 on the upper electrode film 14 are etched to form the opening with exposing the upper electrode film 14 .

Furthermore, the insulator 24 is formed on the interlayer dielectric film 22 and the opening. The insulator 24 is etched by RIE, for example, to remain the insulator 24 on the side-wall of the opening. The via-plug 16 is embedded in the opening being formed on the side-wall. The interconnection layer 17 is formed on the via-plug 16 and the interlayer dielectric film 22 to be formed as the bit line BL being connected with the via-plug 16 . After forming the interconnection layer 17 , the interlayer dielectric film and the interconnection layer are formed by using well-known technique so as to complete the PRAM.

As mentioned above, the phase-change element SR 1 a and the memory transistor are formed in the PRAM memory cell in this embodiment of semiconductor memory device and the fabrication method. The phase-change element SR 1 a is composed of the lower electrode film 10 , the phase-change film 13 and the upper electrode film 14 . When the reset pulse or the set pulse is applied on the phase-change element SR 1 a , the portion where the phase-change film 13 contacts with the lower electrode film 10 is heated up. When the reset pulse is applied, the reset current, relatively large current flows in the phase-change element SR 1 a so that the phase-change film 13 is melted to change to the amorphous state. On the other hand, when the set pulse is applied, relatively small current flows in the phase-change element SR 1 a so that the phase-change film 13 is melted to change to the poly-crystalline state. The radiation-shield film 11 is formed over the both sides and the upper side of the joule heat portion through the insulator 12 and the interlayer dielectric film 22 . The radiation-shield film 11 reflects thermal radiation emitted from the joule heat portion through the insulator 12 and the interlayer dielectric film 22 so as to suppress and shield dissipation of thermal radiation.

Therefore, the reset current, comparatively large current, can be decreased. The phase-change element SR 1 a is changed from a poly-crystalline state with lower resistance of “1” state to an amorphous state with higher resistance of “0”. Furthermore, the set current, comparatively small current, can be also decreased. The phase-change element SR 1 a is exchanged from the amorphous state with higher resistance of “0” to the poly-crystalline state with lower resistance of “1” state. Accordingly, the phase-change memory can be highly integrated and information in the phase-change memory can precisely be written in and read out at low voltage.

Furthermore, the height of the both end portions in the radiation-shield film 11 is set about the same height of the electrode film 10 in this embodiment, however, may be formed in the interlayer dielectric film 21 so as to be formed at a side being lower than the lower electrode film 10 , namely, being a side of the semiconductor substrate 1 under the lower electrode film 10 .

Third Embodiment

Next, a semiconductor memory device according to a third embodiment of the present invention will be described below in detail with reference to figures.

FIG. 15 is a cross-sectional view showing a phase-change element of a phase-change. A structure of a radiation-shield film is changed as comparing with the structure of the first embodiment. The radiation-shield film suppresses and shields dissipation of thermal radiation emitted from a joule heat portion where a phase-change film contacts with a lower electrode film.

The third embodiment will be described below in detail with reference to the attached drawings. Throughout the attached drawings, similar or same reference numerals show similar, equivalent or same components.

As shown in FIG. 15 , in a PRAM memory cell, a phase-change element SR 1 b is formed on the interconnection layer 8 . In the PRAM cell of this embodiment, as a portion under the interconnection layer is the same structure as the first embodiment, the description of the same or similar parts and elements will be omitted.

First, the lower electrode film 10 of the phase-change element SR 1 b is formed on the interconnection layer 8 . The upper electrode film 14 of the phase-change film 13 and the phase-change element SR 1 b are stacked on the lower electrode film 10 in layer.

A pair of radiation-shield film 11 a and an insulator 12 a is periodically formed in lateral direction through the joule heat portion and the insulator 12 a . The interlayer dielectric film 9 is formed on the side-wall of the insulator 12 on the interconnection layer 8 .

Here, the radiation-shield film 11 a is periodically formed five layers, a film thickness T 1 of the radiation-shield film 11 a , for example, is formed as 1 nm and a interval T 2 between the radiation-shield films 11 a , for example, is formed as 1 nm. Therefore, the plurality of the radiation-shield film 11 a can effectively reflect thermal radiation so as to suppress and shield dissipation of the thermal radiation. As the radiation-shield film 11 a is formed apart in the range of 10 nm from the joule heat portion where the phase-change film 13 contact with the lower electrode film 10 , the radiation-shield film 11 a is retained at a comparatively lower temperature. Accordingly, a metal with comparatively lower melting point can be used as the radiation-shield film 11 a . Furthermore, the radiation-shield film 11 a may be a film expect metal which suppress thermal diffusion by lattice vibration. As a material, for example, Al 2 O 3 , SiN, SiC, ZrO 2 or the like is nominated. The pair of the radiation-shield film 11 a and the insulator 12 a formed periodically in lateral direction may surround the joule heat portion as a cylindrical shape. Further, a square prism and a polygonal prism also may be in stead of the cylindrical shape.

As mentioned above, the phase-change element SR 1 b and the memory transistor are formed in the PRAM memory cell in this embodiment of semiconductor memory device and the fabrication method. The phase-change element SR 1 b is composed of the lower electrode film 10 , the phase-change film 13 and the upper electrode film 14 . When the reset pulse or the set pulse is applied on the phase-change element SR 1 b , the portion where the phase-change film 13 contacts with the lower electrode film 10 is heated up. When the reset pulse is applied, the reset current, relatively large current flows in the phase-change element SR 1 b so that the phase-change film 13 is melted to change to the amorphous state. On the other hand, when the set pulse is applied, relatively small current flows in the phase-change element SR 1 b so that the phase-change film 13 is melted to change to the poly-crystalline state. The radiation-shield film 11 a is formed around the joule heat portion via the insulator 12 a , the insulator 12 a formed periodically reflects thermal radiation emitted from so as to suppress and shield dissipation of thermal radiation.

Therefore, the reset current, comparatively large current, can be decreased. The phase-change element SR 1 b is exchanged from a poly-crystalline state with lower resistance of “1” state to an amorphous state with higher resistance of “0”. Furthermore, the set current, comparatively small current, can be also decreased. The phase-change element SR 1 b is exchanged from the amorphous state with higher resistance of “0” to the poly-crystalline state with lower resistance of “1” state. Accordingly, the phase-change memory can be highly integrated and information in the phase-change memory can precisely be written in and read out at low voltage.

Other embodiments of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and example embodiments be considered as exemplary only, with a true scope and spirit of the invention being indicated by the claims that follow. The invention can be carried out by being variously modified within a range not deviated from the gist of the invention.

For example, the radiation-shield film is applied to the PRAM memory cell in this embodiment, however, the radiation-shield film can also be a chain-type PRAM.